def dsub_1 : SubRegIndex<64, 64>;
def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>;
def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>;
-def dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>;
}
// Registers are identified with 5-bit ID numbers.
}
-def FPR8 : RegisterClass<"AArch64", [i8, v1i8], 8,
+def FPR8 : RegisterClass<"AArch64", [v1i8], 8,
(sequence "B%u", 0, 31)> {
}
(sequence "H%u", 0, 31)> {
}
-def FPR32 : RegisterClass<"AArch64", [f32, v1i32, v1f32], 32,
+def FPR32 : RegisterClass<"AArch64", [f32, v1i32], 32,
(sequence "S%u", 0, 31)> {
}
//===----------------------------------------------------------------------===//
// Consecutive vector registers
//===----------------------------------------------------------------------===//
-// 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D30_D31
+// 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D31_D0
def Tuples2D : RegisterTuples<[dsub_0, dsub_1],
[(rotl FPR64, 0), (rotl FPR64, 1)]>;
let Name = PREFIX # LAYOUT # Count;
let RenderMethod = "addVectorListOperands";
let PredicateMethod =
- "isVectorList<A64Layout::_" # LAYOUT # ", " # Count # ">";
+ "isVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">";
let ParserMethod = "ParseVectorList";
}
def _operand : RegisterOperand<RegList,
- "printVectorList<A64Layout::_" # LAYOUT # ", " # Count # ">"> {
+ "printVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">"> {
let ParserMatchClass =
!cast<AsmOperandClass>(PREFIX # LAYOUT # "_asmoperand");
}
defm VOne : VectorList_BHSD<"VOne", 1, FPR64, FPR128>;
defm VPair : VectorList_BHSD<"VPair", 2, DPair, QPair>;
defm VTriple : VectorList_BHSD<"VTriple", 3, DTriple, QTriple>;
-defm VQuad : VectorList_BHSD<"VQuad", 4, DQuad, QQuad>;
\ No newline at end of file
+defm VQuad : VectorList_BHSD<"VQuad", 4, DQuad, QQuad>;