//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "aarch64-isel"
#include "AArch64.h"
#include "AArch64InstrInfo.h"
#include "AArch64Subtarget.h"
using namespace llvm;
+#define DEBUG_TYPE "aarch64-isel"
+
//===--------------------------------------------------------------------===//
/// AArch64 specific code to select AArch64 machine instructions for
/// SelectionDAG operations.
Subtarget(&TM.getSubtarget<AArch64Subtarget>()) {
}
- virtual const char *getPassName() const {
+ const char *getPassName() const override {
return "AArch64 Instruction Selection";
}
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
- std::vector<SDValue> &OutOps);
+ std::vector<SDValue> &OutOps) override;
bool SelectLogicalImm(SDValue N, SDValue &Imm);
SDNode *LowerToFPLitPool(SDNode *Node);
SDNode *SelectToLitPool(SDNode *N);
- SDNode* Select(SDNode*);
+ SDNode* Select(SDNode*) override;
private:
/// Get the opcode for table lookup instruction
unsigned getTBLOpc(bool IsExt, bool Is64Bit, unsigned NumOfVec);
} else {
// Can't handle it in one instruction. There's scope for permitting two (or
// more) instructions, but that'll need more thought.
- return NULL;
+ return nullptr;
}
ResNode = CurDAG->getMachineNode(MOVOpcode, dl, MOVType,
Ops.push_back(CurDAG->getTargetConstant(AN->getOrdering(), MVT::i32));
Ops.push_back(AN->getOperand(0)); // Chain moves to the end
- return CurDAG->SelectNodeTo(Node, Op,
- AN->getValueType(0), MVT::Other,
- &Ops[0], Ops.size());
+ return CurDAG->SelectNodeTo(Node, Op, AN->getValueType(0), MVT::Other, Ops);
}
SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
if (isUpdating)
ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
- return NULL;
+ return nullptr;
}
SDNode *AArch64DAGToDAGISel::SelectVST(SDNode *N, bool isUpdating,
ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
if (isUpdating)
ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
- return NULL;
+ return nullptr;
}
// We only have 128-bit vector type of load/store lane instructions.
ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
if (isUpdating)
ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
- return NULL;
+ return nullptr;
}
unsigned AArch64DAGToDAGISel::getTBLOpc(bool IsExt, bool Is64Bit,
if (Node->isMachineOpcode()) {
DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
Node->setNodeId(-1);
- return NULL;
+ return nullptr;
}
switch (Node->getOpcode()) {
return CurDAG->SelectNodeTo(Node, AArch64::ADDxxi_lsl0_s, PtrTy,
TFI, CurDAG->getTargetConstant(0, PtrTy));
}
- case ISD::ConstantPool: {
- // Constant pools are fine, just create a Target entry.
- ConstantPoolSDNode *CN = cast<ConstantPoolSDNode>(Node);
- const Constant *C = CN->getConstVal();
- SDValue CP = CurDAG->getTargetConstantPool(C, CN->getValueType(0));
-
- ReplaceUses(SDValue(Node, 0), CP);
- return NULL;
- }
case ISD::Constant: {
- SDNode *ResNode = 0;
+ SDNode *ResNode = nullptr;
if (cast<ConstantSDNode>(Node)->getZExtValue() == 0) {
// XZR and WZR are probably even better than an actual move: most of the
// time they can be folded into another instruction with *no* cost.
SDNode *ResNode = SelectCode(Node);
DEBUG(dbgs() << "=> ";
- if (ResNode == NULL || ResNode == Node)
+ if (ResNode == nullptr || ResNode == Node)
Node->dump(CurDAG);
else
ResNode->dump(CurDAG);