// features they correspond to (use getFPUFeatures).
// FIXME: TableGen this.
// The entries must appear in the order listed in ARM::FPUKind for correct indexing
-struct {
+static const struct {
const char *NameCStr;
size_t NameLength;
ARM::FPUKind ID;
// of the triples and are not conforming with their official names.
// Check to see if the expectation should be changed.
// FIXME: TableGen this.
-struct {
+static const struct {
const char *NameCStr;
size_t NameLength;
ARM::ArchKind ID;
const char *SubArchCStr;
size_t SubArchLength;
ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
+ unsigned DefaultFPU;
unsigned ArchBaseExtensions;
StringRef getName() const { return StringRef(NameCStr, NameLength); }
// Sub-Arch name.
StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); }
} ARCHNames[] = {
-#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_BASE_EXT) \
+#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \
{NAME, sizeof(NAME) - 1, ID, CPU_ATTR, sizeof(CPU_ATTR) - 1, SUB_ARCH, \
- sizeof(SUB_ARCH) - 1, ARCH_ATTR, ARCH_BASE_EXT},
+ sizeof(SUB_ARCH) - 1, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT},
#include "llvm/Support/ARMTargetParser.def"
};
// List of Arch Extension names.
// FIXME: TableGen this.
-struct {
+static const struct {
const char *NameCStr;
size_t NameLength;
unsigned ID;
// List of HWDiv names (use getHWDivSynonym) and which architectural
// features they correspond to (use getHWDivFeatures).
// FIXME: TableGen this.
-struct {
+static const struct {
const char *NameCStr;
size_t NameLength;
unsigned ID;
// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
// When this becomes table-generated, we'd probably need two tables.
// FIXME: TableGen this.
-struct {
+static const struct {
const char *NameCStr;
size_t NameLength;
ARM::ArchKind ArchID;
return FPUNames[FPUKind].Restriction;
}
-unsigned llvm::ARM::getDefaultFPU(StringRef CPU) {
+unsigned llvm::ARM::getDefaultFPU(StringRef CPU, unsigned ArchKind) {
+ if (CPU == "generic")
+ return ARCHNames[ArchKind].DefaultFPU;
+
return StringSwitch<unsigned>(CPU)
#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
.Case(NAME, DEFAULT_FPU)
.Default(ARM::FK_INVALID);
}
+unsigned llvm::ARM::getDefaultExtensions(StringRef CPU, unsigned ArchKind) {
+ if (CPU == "generic")
+ return ARCHNames[ArchKind].ArchBaseExtensions;
+
+ return StringSwitch<unsigned>(CPU)
+#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
+ .Case(NAME, ARCHNames[ID].ArchBaseExtensions | DEFAULT_EXT)
+#include "llvm/Support/ARMTargetParser.def"
+ .Default(ARM::AEK_INVALID);
+}
+
bool llvm::ARM::getHWDivFeatures(unsigned HWDivKind,
std::vector<const char *> &Features) {
return StringRef();
}
-unsigned llvm::ARM::getDefaultExtensions(StringRef CPU) {
- for (const auto C : CPUNames) {
- if (CPU == C.getName())
- return (ARCHNames[C.ArchID].ArchBaseExtensions | C.DefaultExtensions);
- }
- return ARM::AEK_INVALID;
-}
-
StringRef llvm::ARM::getDefaultCPU(StringRef Arch) {
unsigned AK = parseArch(Arch);
if (AK == ARM::AK_INVALID)
if (CPU.ArchID == AK && CPU.Default)
return CPU.getName();
}
- return StringRef();
+
+ // If we can't find a default then target the architecture instead
+ return "generic";
}
// ======================================================= //
.Case("v5e", "v5te")
.Case("v6hl", "v6k")
.Cases("v6m", "v6sm", "v6s-m", "v6-m")
+ .Cases("v6z", "v6zk", "v6kz")
.Cases("v7", "v7a", "v7hl", "v7l", "v7-a")
.Case("v7r", "v7-r")
.Case("v7m", "v7-m")
case ARM::AK_ARMV6J:
case ARM::AK_ARMV6K:
case ARM::AK_ARMV6T2:
- case ARM::AK_ARMV6Z:
- case ARM::AK_ARMV6ZK:
+ case ARM::AK_ARMV6KZ:
case ARM::AK_ARMV6M:
return 6;
case ARM::AK_ARMV7A: