//===----------------------------------------------------------------------===//
#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/SubtargetFeature.h"
-#include "llvm/ADT/StringRef.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
using namespace llvm;
-void MCSubtargetInfo::InitMCSubtargetInfo(StringRef CPU, StringRef FS,
- const SubtargetFeatureKV *PF,
- const SubtargetFeatureKV *PD,
- const SubtargetInfoKV *PI,
- const InstrStage *IS,
- const unsigned *OC,
- const unsigned *FP,
- unsigned NF, unsigned NP) {
- ProcFeatures = PF;
- ProcDesc = PD;
- ProcItins = PI;
- Stages = IS;
- OperandCycles = OC;
- ForwardingPathes = FP;
- NumFeatures = NF;
- NumProcs = NP;
-
+static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
+ ArrayRef<SubtargetFeatureKV> ProcDesc,
+ ArrayRef<SubtargetFeatureKV> ProcFeatures) {
SubtargetFeatures Features(FS);
- FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
- ProcFeatures, NumFeatures);
+ return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
}
+void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
+ FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
+ if (!CPU.empty())
+ CPUSchedModel = &getSchedModelForCPU(CPU);
+ else
+ CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
+}
-/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
-/// feature string) and recompute feature bits.
-uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) {
- SubtargetFeatures Features(FS);
- FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
- ProcFeatures, NumFeatures);
+void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
+ FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
+}
+
+MCSubtargetInfo::MCSubtargetInfo(
+ const Triple &TT, StringRef C, StringRef FS,
+ ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
+ const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
+ const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
+ const InstrStage *IS, const unsigned *OC, const unsigned *FP)
+ : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
+ ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
+ ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
+ InitMCProcessorInfo(CPU, FS);
+}
+
+/// ToggleFeature - Toggle a feature and returns the re-computed feature
+/// bits. This version does not change the implied bits.
+FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
+ FeatureBits.flip(FB);
return FeatureBits;
}
-InstrItineraryData
-MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
- assert(ProcItins && "Instruction itineraries information not available!");
+FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
+ FeatureBits ^= FB;
+ return FeatureBits;
+}
-#ifndef NDEBUG
- for (size_t i = 1; i < NumProcs; i++) {
- assert(strcmp(ProcItins[i - 1].Key, ProcItins[i].Key) < 0 &&
- "Itineraries table is not sorted");
- }
-#endif
+/// ToggleFeature - Toggle a feature and returns the re-computed feature
+/// bits. This version will also change all implied bits.
+FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
+ SubtargetFeatures::ToggleFeature(FeatureBits, FS, ProcFeatures);
+ return FeatureBits;
+}
+
+FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
+ SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
+ return FeatureBits;
+}
+
+const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
+ assert(ProcSchedModels && "Processor machine model not available!");
+
+ ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
+
+ assert(std::is_sorted(SchedModels.begin(), SchedModels.end(),
+ [](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
+ return strcmp(LHS.Key, RHS.Key) < 0;
+ }) &&
+ "Processor machine model table is not sorted");
// Find entry
- SubtargetInfoKV KV;
- KV.Key = CPU.data();
- const SubtargetInfoKV *Found =
- std::lower_bound(ProcItins, ProcItins+NumProcs, KV);
- if (Found == ProcItins+NumProcs || StringRef(Found->Key) != CPU) {
- errs() << "'" << CPU
- << "' is not a recognized processor for this target"
- << " (ignoring processor)\n";
- return InstrItineraryData();
+ auto Found =
+ std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
+ if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
+ if (CPU != "help") // Don't error if the user asked for help.
+ errs() << "'" << CPU
+ << "' is not a recognized processor for this target"
+ << " (ignoring processor)\n";
+ return MCSchedModel::GetDefaultSchedModel();
}
+ assert(Found->Value && "Missing processor SchedModel value");
+ return *(const MCSchedModel *)Found->Value;
+}
+
+InstrItineraryData
+MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
+ const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
+ return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
+}
- return InstrItineraryData(Stages, OperandCycles, ForwardingPathes,
- (InstrItinerary *)Found->Value);
+/// Initialize an InstrItineraryData instance.
+void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
+ InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
+ ForwardingPaths);
}
projects / oota-llvm.git / blobdiff