#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
-#include <iostream>
using namespace llvm;
-namespace {
- static Statistic<> NumTwoAddressInstrs("twoaddressinstruction",
- "Number of two-address instructions");
- static Statistic<> NumCommuted("twoaddressinstruction",
- "Number of instructions commuted to coalesce");
- static Statistic<> NumConvertedTo3Addr("twoaddressinstruction",
- "Number of instructions promoted to 3-address");
+STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
+STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
+STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
+namespace {
struct VISIBILITY_HIDDEN TwoAddressInstructionPass
: public MachineFunctionPass {
+ static char ID; // Pass identification, replacement for typeid
+ TwoAddressInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
+
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
/// runOnMachineFunction - pass entry point
bool runOnMachineFunction(MachineFunction&);
};
+ char TwoAddressInstructionPass::ID = 0;
RegisterPass<TwoAddressInstructionPass>
X("twoaddressinstruction", "Two-Address instruction pass");
}
/// operands.
///
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
- DEBUG(std::cerr << "Machine Function\n");
+ DOUT << "Machine Function\n";
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo &MRI = *TM.getRegisterInfo();
const TargetInstrInfo &TII = *TM.getInstrInfo();
+ const MRegisterInfo &MRI = *TM.getRegisterInfo();
LiveVariables &LV = getAnalysis<LiveVariables>();
bool MadeChange = false;
- DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
- DEBUG(std::cerr << "********** Function: "
- << MF.getFunction()->getName() << '\n');
+ DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n";
+ DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
mbbi != mbbe; ++mbbi) {
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
mi != me; ++mi) {
- unsigned opcode = mi->getOpcode();
+ const TargetInstrDescriptor *TID = mi->getInstrDescriptor();
bool FirstTied = true;
- for (unsigned si = 1, e = TII.getNumOperands(opcode); si < e; ++si) {
- int ti = TII.getOperandConstraint(opcode, si, TargetInstrInfo::TIED_TO);
+ for (unsigned si = 1, e = TID->numOperands; si < e; ++si) {
+ int ti = TID->getOperandConstraint(si, TOI::TIED_TO);
if (ti == -1)
continue;
if (FirstTied) {
++NumTwoAddressInstrs;
- DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
+ DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM));
}
FirstTied = false;
// allow us to coalesce A and B together, eliminating the copy we are
// about to insert.
if (!LV.KillsRegister(mi, regB)) {
- const TargetInstrDescriptor &TID = TII.get(opcode);
-
// If this instruction is commutative, check to see if C dies. If
// so, swap the B and C operands. This makes the live ranges of A
// and C joinable.
// FIXME: This code also works for A := B op C instructions.
- if ((TID.Flags & M_COMMUTABLE) && mi->getNumOperands() == 3) {
+ if ((TID->Flags & M_COMMUTABLE) && mi->getNumOperands() >= 3) {
assert(mi->getOperand(3-si).isRegister() &&
"Not a proper commutative instruction!");
unsigned regC = mi->getOperand(3-si).getReg();
if (LV.KillsRegister(mi, regC)) {
- DEBUG(std::cerr << "2addr: COMMUTING : " << *mi);
+ DOUT << "2addr: COMMUTING : " << *mi;
MachineInstr *NewMI = TII.commuteInstruction(mi);
if (NewMI == 0) {
- DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n");
+ DOUT << "2addr: COMMUTING FAILED!\n";
} else {
- DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI);
+ DOUT << "2addr: COMMUTED TO: " << *NewMI;
// If the instruction changed to commute it, update livevar.
if (NewMI != mi) {
LV.instructionChanged(mi, NewMI); // Update live variables
// If this instruction is potentially convertible to a true
// three-address instruction,
- if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
+ if (TID->Flags & M_CONVERTIBLE_TO_3_ADDR) {
// FIXME: This assumes there are no more operands which are tied
// to another register.
#ifndef NDEBUG
- for (unsigned i = si+1, e = TII.getNumOperands(opcode); i < e; ++i)
- assert(TII.getOperandConstraint(opcode, i,
- TargetInstrInfo::TIED_TO) == -1);
+ for (unsigned i = si+1, e = TID->numOperands; i < e; ++i)
+ assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1);
#endif
- if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
- DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
- DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New);
- LV.instructionChanged(mi, New); // Update live variables
- mbbi->insert(mi, New); // Insert the new inst
+ if (MachineInstr *New = TII.convertToThreeAddress(mbbi, mi, LV)) {
+ DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
+ DOUT << "2addr: TO 3-ADDR: " << *New;
mbbi->erase(mi); // Nuke the old inst.
mi = New;
++NumConvertedTo3Addr;
// Done with this instruction.
break;
}
+ }
}
InstructionRearranged:
const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
- MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
+ MRI.copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
MachineBasicBlock::iterator prevMi = prior(mi);
- DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
+ DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
// Update live variables for regA
LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
varInfo.DefInst = prevMi;
- // update live variables for regB
if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
LV.addVirtualRegisterKilled(regB, prevMi);
mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
MadeChange = true;
- DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
+ DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM));
}
}
}
projects / oota-llvm.git / blobdiff