- bool IsImpDef = true;
- SmallVector<unsigned, 4> RealSrcs;
- SmallSet<unsigned, 4> Seen;
- for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
- // Nothing needs to be inserted for <undef> operands.
- if (MI->getOperand(i).isUndef()) {
- MI->getOperand(i).setReg(0);
- continue;
- }
- unsigned SrcReg = MI->getOperand(i).getReg();
- unsigned SrcSubIdx = MI->getOperand(i).getSubReg();
- unsigned SubIdx = MI->getOperand(i+1).getImm();
- // DefMI of NULL means the value does not have a vreg in this block
- // i.e., its a physical register or a subreg.
- // In either case we force a copy to be generated.
- MachineInstr *DefMI = NULL;
- if (!MI->getOperand(i).getSubReg() &&
- !TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
- DefMI = MRI->getUniqueVRegDef(SrcReg);
- }
-
- if (DefMI && DefMI->isImplicitDef()) {
- DefMI->eraseFromParent();
- continue;
- }
- IsImpDef = false;
-
- // Remember COPY sources. These might be candidate for coalescing.
- if (DefMI && DefMI->isCopy() && DefMI->getOperand(1).getSubReg())
- RealSrcs.push_back(DefMI->getOperand(1).getReg());
-
- bool isKill = MI->getOperand(i).isKill();
- if (!DefMI || !Seen.insert(SrcReg) ||
- MI->getParent() != DefMI->getParent() ||
- !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) ||
- !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg),
- MRI->getRegClass(SrcReg), SubIdx)) {
- // REG_SEQUENCE cannot have duplicated operands, add a copy.
- // Also add an copy if the source is live-in the block. We don't want
- // to end up with a partial-redef of a livein, e.g.
- // BB0:
- // reg1051:10<def> =
- // ...
- // BB1:
- // ... = reg1051:10
- // BB2:
- // reg1051:9<def> =
- // LiveIntervalAnalysis won't like it.
- //
- // If the REG_SEQUENCE doesn't kill its source, keeping live variables
- // correctly up to date becomes very difficult. Insert a copy.
-
- // Defer any kill flag to the last operand using SrcReg. Otherwise, we
- // might insert a COPY that uses SrcReg after is was killed.
- if (isKill)
- for (unsigned j = i + 2; j < e; j += 2)
- if (MI->getOperand(j).getReg() == SrcReg) {
- MI->getOperand(j).setIsKill();
- isKill = false;
- break;
- }
-
- MachineBasicBlock::iterator InsertLoc = MI;
- MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc,
- MI->getDebugLoc(), TII->get(TargetOpcode::COPY))
- .addReg(DstReg, RegState::Define, SubIdx)
- .addReg(SrcReg, getKillRegState(isKill), SrcSubIdx);
- MI->getOperand(i).setReg(0);
- if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
- LV->replaceKillInstruction(SrcReg, MI, CopyMI);
- DEBUG(dbgs() << "Inserted: " << *CopyMI);
- }
- }
-
- for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
- unsigned SrcReg = MI->getOperand(i).getReg();
- if (!SrcReg) continue;
- unsigned SubIdx = MI->getOperand(i+1).getImm();
- UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
- }
-
- // Set <def,undef> flags on the first DstReg def in the basic block.
- // It marks the beginning of the live range. All the other defs are
- // read-modify-write.
- if (MachineInstr *Def = findFirstDef(DstReg, MRI)) {
- for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = Def->getOperand(i);
- if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
- MO.setIsUndef();
- }
- // Make sure there is a full non-subreg imp-def operand on the
- // instruction. This shouldn't be necessary, but it seems that at least
- // RAFast requires it.
- Def->addRegisterDefined(DstReg, TRI);
- DEBUG(dbgs() << "First def: " << *Def);
- }
-
- if (IsImpDef) {
- DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
- MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
- for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
- MI->RemoveOperand(j);
- } else {
- DEBUG(dbgs() << "Eliminated: " << *MI);
- MI->eraseFromParent();
- }