#define DEBUG_TYPE "spiller"
#include "Spiller.h"
-#include "VirtRegMap.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
using namespace llvm;
+namespace {
+ enum SpillerName { trivial, inline_ };
+}
+
+static cl::opt<SpillerName>
+spillerOpt("spiller",
+ cl::desc("Spiller to use: (default: standard)"),
+ cl::Prefix,
+ cl::values(clEnumVal(trivial, "trivial spiller"),
+ clEnumValN(inline_, "inline", "inline spiller"),
+ clEnumValEnd),
+ cl::init(trivial));
+
+// Spiller virtual destructor implementation.
Spiller::~Spiller() {}
namespace {
/// Utility class for spillers.
class SpillerBase : public Spiller {
protected:
-
+ MachineFunctionPass *pass;
MachineFunction *mf;
+ VirtRegMap *vrm;
LiveIntervals *lis;
- LiveStacks *ls;
MachineFrameInfo *mfi;
MachineRegisterInfo *mri;
const TargetInstrInfo *tii;
- VirtRegMap *vrm;
-
- /// Construct a spiller base.
- SpillerBase(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, VirtRegMap *vrm) :
- mf(mf), lis(lis), ls(ls), vrm(vrm)
- {
- mfi = mf->getFrameInfo();
- mri = &mf->getRegInfo();
- tii = mf->getTarget().getInstrInfo();
- }
-
- /// Insert a store of the given vreg to the given stack slot immediately
- /// after the given instruction. Returns the base index of the inserted
- /// instruction. The caller is responsible for adding an appropriate
- /// LiveInterval to the LiveIntervals analysis.
- unsigned insertStoreFor(MachineInstr *mi, unsigned ss,
- unsigned newVReg,
- const TargetRegisterClass *trc) {
- MachineBasicBlock::iterator nextInstItr(mi);
- ++nextInstItr;
-
- if (!lis->hasGapAfterInstr(lis->getInstructionIndex(mi))) {
- lis->scaleNumbering(2);
- ls->scaleNumbering(2);
- }
-
- unsigned miIdx = lis->getInstructionIndex(mi);
-
- assert(lis->hasGapAfterInstr(miIdx));
-
- tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, newVReg,
- true, ss, trc);
- MachineBasicBlock::iterator storeInstItr(mi);
- ++storeInstItr;
- MachineInstr *storeInst = &*storeInstItr;
- unsigned storeInstIdx = miIdx + LiveInterval::InstrSlots::NUM;
-
- assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
- "Store inst index already in use.");
-
- lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
-
- return storeInstIdx;
- }
-
- /// Insert a load of the given veg from the given stack slot immediately
- /// before the given instruction. Returns the base index of the inserted
- /// instruction. The caller is responsible for adding an appropriate
- /// LiveInterval to the LiveIntervals analysis.
- unsigned insertLoadFor(MachineInstr *mi, unsigned ss,
- unsigned newVReg,
- const TargetRegisterClass *trc) {
- MachineBasicBlock::iterator useInstItr(mi);
-
- if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) {
- lis->scaleNumbering(2);
- ls->scaleNumbering(2);
- }
-
- unsigned miIdx = lis->getInstructionIndex(mi);
+ const TargetRegisterInfo *tri;
- assert(lis->hasGapBeforeInstr(miIdx));
-
- tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, newVReg, ss, trc);
- MachineBasicBlock::iterator loadInstItr(mi);
- --loadInstItr;
- MachineInstr *loadInst = &*loadInstItr;
- unsigned loadInstIdx = miIdx - LiveInterval::InstrSlots::NUM;
-
- assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
- "Load inst index already in use.");
-
- lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
-
- return loadInstIdx;
+ /// Construct a spiller base.
+ SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
+ : pass(&pass), mf(&mf), vrm(&vrm)
+ {
+ lis = &pass.getAnalysis<LiveIntervals>();
+ mfi = mf.getFrameInfo();
+ mri = &mf.getRegInfo();
+ tii = mf.getTarget().getInstrInfo();
+ tri = mf.getTarget().getRegisterInfo();
}
-
/// Add spill ranges for every use/def of the live interval, inserting loads
- /// immediately before each use, and stores after each def. No folding is
- /// attempted.
- std::vector<LiveInterval*> trivialSpillEverywhere(LiveInterval *li) {
- DOUT << "Spilling everywhere " << *li << "\n";
+ /// immediately before each use, and stores after each def. No folding or
+ /// remat is attempted.
+ void trivialSpillEverywhere(LiveRangeEdit& LRE) {
+ LiveInterval* li = &LRE.getParent();
+
+ DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
assert(li->weight != HUGE_VALF &&
"Attempting to spill already spilled value.");
- assert(!li->isStackSlot() &&
+ assert(!TargetRegisterInfo::isStackSlot(li->reg) &&
"Trying to spill a stack slot.");
- std::vector<LiveInterval*> added;
-
+ DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
+
const TargetRegisterClass *trc = mri->getRegClass(li->reg);
unsigned ss = vrm->assignVirt2StackSlot(li->reg);
+ // Iterate over reg uses/defs.
for (MachineRegisterInfo::reg_iterator
regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
+ // Grab the use/def instr.
MachineInstr *mi = &*regItr;
+
+ DEBUG(dbgs() << " Processing " << *mi);
+
+ // Step regItr to the next use/def instr.
do {
++regItr;
} while (regItr != mri->reg_end() && (&*regItr == mi));
-
+
+ // Collect uses & defs for this instr.
SmallVector<unsigned, 2> indices;
bool hasUse = false;
bool hasDef = false;
-
for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
MachineOperand &op = mi->getOperand(i);
-
if (!op.isReg() || op.getReg() != li->reg)
continue;
-
hasUse |= mi->getOperand(i).isUse();
hasDef |= mi->getOperand(i).isDef();
-
indices.push_back(i);
}
- unsigned newVReg = mri->createVirtualRegister(trc);
- vrm->grow();
- vrm->assignVirt2StackSlot(newVReg, ss);
+ // Create a new virtual register for the load and/or store.
+ unsigned NewVReg = LRE.create();
- LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
- newLI->weight = HUGE_VALF;
-
+ // Update the reg operands & kill flags.
for (unsigned i = 0; i < indices.size(); ++i) {
- mi->getOperand(indices[i]).setReg(newVReg);
-
- if (mi->getOperand(indices[i]).isUse()) {
- mi->getOperand(indices[i]).setIsKill(true);
+ unsigned mopIdx = indices[i];
+ MachineOperand &mop = mi->getOperand(mopIdx);
+ mop.setReg(NewVReg);
+ if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
+ mop.setIsKill(true);
}
}
-
assert(hasUse || hasDef);
+ // Insert reload if necessary.
+ MachineBasicBlock::iterator miItr(mi);
if (hasUse) {
- unsigned loadInstIdx = insertLoadFor(mi, ss, newVReg, trc);
- unsigned start = lis->getDefIndex(loadInstIdx),
- end = lis->getUseIndex(lis->getInstructionIndex(mi));
+ MachineInstrSpan MIS(miItr);
- VNInfo *vni =
- newLI->getNextValue(loadInstIdx, 0, lis->getVNInfoAllocator());
- vni->kills.push_back(lis->getInstructionIndex(mi));
- LiveRange lr(start, end, vni);
-
- newLI->addRange(lr);
+ tii->loadRegFromStackSlot(*mi->getParent(), miItr, NewVReg, ss, trc,
+ tri);
+ lis->InsertMachineInstrRangeInMaps(MIS.begin(), miItr);
}
+ // Insert store if necessary.
if (hasDef) {
- unsigned storeInstIdx = insertStoreFor(mi, ss, newVReg, trc);
- unsigned start = lis->getDefIndex(lis->getInstructionIndex(mi)),
- end = lis->getUseIndex(storeInstIdx);
-
- VNInfo *vni =
- newLI->getNextValue(storeInstIdx, 0, lis->getVNInfoAllocator());
- vni->kills.push_back(storeInstIdx);
- LiveRange lr(start, end, vni);
-
- newLI->addRange(lr);
- }
+ MachineInstrSpan MIS(miItr);
- added.push_back(newLI);
+ tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), NewVReg,
+ true, ss, trc, tri);
+ lis->InsertMachineInstrRangeInMaps(llvm::next(miItr), MIS.end());
+ }
}
-
-
- return added;
}
-
};
+} // end anonymous namespace
+
+namespace {
/// Spills any live range using the spill-everywhere method with no attempt at
/// folding.
class TrivialSpiller : public SpillerBase {
public:
- TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, VirtRegMap *vrm) :
- SpillerBase(mf, lis, ls, vrm) {}
- std::vector<LiveInterval*> spill(LiveInterval *li) {
- return trivialSpillEverywhere(li);
- }
+ TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf,
+ VirtRegMap &vrm)
+ : SpillerBase(pass, mf, vrm) {}
+ void spill(LiveRangeEdit &LRE) {
+ // Ignore spillIs - we don't use it.
+ trivialSpillEverywhere(LRE);
+ }
};
-}
+} // end anonymous namespace
+
+void Spiller::anchor() { }
-llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
- LiveStacks *ls, VirtRegMap *vrm) {
- return new TrivialSpiller(mf, lis, ls, vrm);
+llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
+ MachineFunction &mf,
+ VirtRegMap &vrm) {
+ switch (spillerOpt) {
+ case trivial: return new TrivialSpiller(pass, mf, vrm);
+ case inline_: return createInlineSpiller(pass, mf, vrm);
+ }
+ llvm_unreachable("Invalid spiller optimization");
}
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