MachineBasicBlock *MBB,
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
#ifndef NDEBUG
- errs() << "If a target marks an instruction with "
+ dbgs() << "If a target marks an instruction with "
"'usesCustomInserter', it must implement "
"TargetLowering::EmitInstrWithCustomInserter!";
#endif
else
GFI = 0;
RegInfo = &MF->getRegInfo();
- DEBUG(errs() << "\n\n\n=== " << Fn.getName() << "\n");
+ DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
/// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
/// attached with this instruction.
-static void SetDebugLoc(unsigned MDDbgKind,
- MetadataContext &TheMetadata,
- Instruction *I,
+static void SetDebugLoc(unsigned MDDbgKind, Instruction *I,
SelectionDAGBuilder *SDB,
- FastISel *FastIS,
- MachineFunction *MF) {
- if (!isa<DbgInfoIntrinsic>(I))
- if (MDNode *Dbg = TheMetadata.getMD(MDDbgKind, I)) {
- DILocation DILoc(Dbg);
- DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
-
- SDB->setCurDebugLoc(Loc);
-
- if (FastIS)
- FastIS->setCurDebugLoc(Loc);
-
- // If the function doesn't have a default debug location yet, set
- // it. This is kind of a hack.
- if (MF->getDefaultDebugLoc().isUnknown())
- MF->setDefaultDebugLoc(Loc);
- }
+ FastISel *FastIS, MachineFunction *MF) {
+ if (isa<DbgInfoIntrinsic>(I)) return;
+
+ if (MDNode *Dbg = I->getMetadata(MDDbgKind)) {
+ DILocation DILoc(Dbg);
+ DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
+
+ SDB->setCurDebugLoc(Loc);
+
+ if (FastIS)
+ FastIS->setCurDebugLoc(Loc);
+
+ // If the function doesn't have a default debug location yet, set
+ // it. This is kind of a hack.
+ if (MF->getDefaultDebugLoc().isUnknown())
+ MF->setDefaultDebugLoc(Loc);
+ }
}
/// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
-static void ResetDebugLoc(SelectionDAGBuilder *SDB,
- FastISel *FastIS) {
+static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
SDB->setCurDebugLoc(DebugLoc::getUnknownLoc());
if (FastIS)
- SDB->setCurDebugLoc(DebugLoc::getUnknownLoc());
+ FastIS->setCurDebugLoc(DebugLoc::getUnknownLoc());
}
void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
BasicBlock::iterator End,
bool &HadTailCall) {
SDB->setCurrentBasicBlock(BB);
- MetadataContext &TheMetadata = LLVMBB->getParent()->getContext().getMetadata();
- unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
+ unsigned MDDbgKind = LLVMBB->getContext().getMDKindID("dbg");
// Lower all of the non-terminator instructions. If a call is emitted
// as a tail call, cease emitting nodes for this block.
for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
- if (MDDbgKind)
- SetDebugLoc(MDDbgKind, TheMetadata, I, SDB, 0, MF);
+ SetDebugLoc(MDDbgKind, I, SDB, 0, MF);
if (!isa<TerminatorInst>(I)) {
SDB->visit(*I);
HandlePHINodesInSuccessorBlocks(LLVMBB);
// Lower the terminator after the copies are emitted.
- SetDebugLoc(MDDbgKind, TheMetadata, LLVMBB->getTerminator(), SDB, 0, MF);
+ SetDebugLoc(MDDbgKind, LLVMBB->getTerminator(), SDB, 0, MF);
SDB->visit(*LLVMBB->getTerminator());
ResetDebugLoc(SDB, 0);
}
SDB->clear();
}
+/// ShrinkDemandedOps - A late transformation pass that shrink expressions
+/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
+/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
+void SelectionDAGISel::ShrinkDemandedOps() {
+ SmallVector<SDNode*, 128> Worklist;
+
+ // Add all the dag nodes to the worklist.
+ Worklist.reserve(CurDAG->allnodes_size());
+ for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
+ E = CurDAG->allnodes_end(); I != E; ++I)
+ Worklist.push_back(I);
+
+ APInt Mask;
+ APInt KnownZero;
+ APInt KnownOne;
+
+ TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
+ while (!Worklist.empty()) {
+ SDNode *N = Worklist.pop_back_val();
+
+ if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
+ CurDAG->DeleteNode(N);
+ continue;
+ }
+
+ // Run ShrinkDemandedOp on scalar binary operations.
+ if (N->getNumValues() == 1 &&
+ N->getValueType(0).isSimple() && N->getValueType(0).isInteger()) {
+ unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
+ APInt Demanded = APInt::getAllOnesValue(BitWidth);
+ APInt KnownZero, KnownOne;
+ if (TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
+ KnownZero, KnownOne, TLO)) {
+ // Revisit the node.
+ Worklist.erase(std::remove(Worklist.begin(), Worklist.end(), N),
+ Worklist.end());
+ Worklist.push_back(N);
+
+ // Replace the old value with the new one.
+ DEBUG(errs() << "\nReplacing ";
+ TLO.Old.getNode()->dump(CurDAG);
+ errs() << "\nWith: ";
+ TLO.New.getNode()->dump(CurDAG);
+ errs() << '\n');
+
+ Worklist.push_back(TLO.New.getNode());
+ CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
+
+ if (TLO.Old.getNode()->use_empty()) {
+ for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
+ i != e; ++i) {
+ SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
+ if (OpNode->hasOneUse()) {
+ Worklist.erase(std::remove(Worklist.begin(), Worklist.end(),
+ OpNode),
+ Worklist.end());
+ Worklist.push_back(TLO.Old.getNode()->getOperand(i).getNode());
+ }
+ }
+
+ Worklist.erase(std::remove(Worklist.begin(), Worklist.end(),
+ TLO.Old.getNode()),
+ Worklist.end());
+ CurDAG->DeleteNode(TLO.Old.getNode());
+ }
+ }
+ }
+ }
+}
+
void SelectionDAGISel::ComputeLiveOutVRegInfo() {
SmallPtrSet<SDNode*, 128> VisitedNodes;
SmallVector<SDNode*, 128> Worklist;
APInt KnownZero;
APInt KnownOne;
- while (!Worklist.empty()) {
- SDNode *N = Worklist.back();
- Worklist.pop_back();
+ do {
+ SDNode *N = Worklist.pop_back_val();
// If we've already seen this node, ignore it.
if (!VisitedNodes.insert(N))
LOI.KnownOne = KnownOne;
LOI.KnownZero = KnownZero;
}
- }
+ } while (!Worklist.empty());
}
void SelectionDAGISel::CodeGenAndEmitDAG() {
BlockName = MF->getFunction()->getNameStr() + ":" +
BB->getBasicBlock()->getNameStr();
- DEBUG(errs() << "Initial selection DAG:\n");
+ DEBUG(dbgs() << "Initial selection DAG:\n");
DEBUG(CurDAG->dump());
if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
CurDAG->Combine(Unrestricted, *AA, OptLevel);
}
- DEBUG(errs() << "Optimized lowered selection DAG:\n");
+ DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
DEBUG(CurDAG->dump());
// Second step, hack on the DAG until it only uses operations and types that
Changed = CurDAG->LegalizeTypes();
}
- DEBUG(errs() << "Type-legalized selection DAG:\n");
+ DEBUG(dbgs() << "Type-legalized selection DAG:\n");
DEBUG(CurDAG->dump());
if (Changed) {
CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
}
- DEBUG(errs() << "Optimized type-legalized selection DAG:\n");
+ DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
DEBUG(CurDAG->dump());
}
if (Changed) {
if (TimePassesIsEnabled) {
NamedRegionTimer T("Type Legalization 2", GroupName);
- Changed = CurDAG->LegalizeTypes();
+ CurDAG->LegalizeTypes();
} else {
- Changed = CurDAG->LegalizeTypes();
+ CurDAG->LegalizeTypes();
}
if (ViewDAGCombineLT)
CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
}
- DEBUG(errs() << "Optimized vector-legalized selection DAG:\n");
+ DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
DEBUG(CurDAG->dump());
}
CurDAG->Legalize(OptLevel);
}
- DEBUG(errs() << "Legalized selection DAG:\n");
+ DEBUG(dbgs() << "Legalized selection DAG:\n");
DEBUG(CurDAG->dump());
if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
}
- DEBUG(errs() << "Optimized legalized selection DAG:\n");
+ DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
DEBUG(CurDAG->dump());
if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
- if (OptLevel != CodeGenOpt::None)
+ if (OptLevel != CodeGenOpt::None) {
+ ShrinkDemandedOps();
ComputeLiveOutVRegInfo();
+ }
// Third, instruction select all of the operations to machine code, adding the
// code to the MachineBasicBlock.
InstructionSelect();
}
- DEBUG(errs() << "Selected selection DAG:\n");
+ DEBUG(dbgs() << "Selected selection DAG:\n");
DEBUG(CurDAG->dump());
if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
delete Scheduler;
}
- DEBUG(errs() << "Selected machine code:\n");
+ DEBUG(dbgs() << "Selected machine code:\n");
DEBUG(BB->dump());
}
#endif
);
- MetadataContext &TheMetadata = Fn.getContext().getMetadata();
- unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
+ unsigned MDDbgKind = Fn.getContext().getMDKindID("dbg");
// Iterate over all basic blocks in the function.
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
I != E; ++I, ++j)
if (Fn.paramHasAttr(j, Attribute::ByVal)) {
if (EnableFastISelVerbose || EnableFastISelAbort)
- errs() << "FastISel skips entry block due to byval argument\n";
+ dbgs() << "FastISel skips entry block due to byval argument\n";
SuppressFastISel = true;
break;
}
if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
ResetDebugLoc(SDB, FastIS);
if (EnableFastISelVerbose || EnableFastISelAbort) {
- errs() << "FastISel miss: ";
+ dbgs() << "FastISel miss: ";
BI->dump();
}
assert(!EnableFastISelAbort &&
break;
}
- if (MDDbgKind)
- SetDebugLoc(MDDbgKind, TheMetadata, BI, SDB, FastIS, &MF);
+ SetDebugLoc(MDDbgKind, BI, SDB, FastIS, &MF);
// First try normal tablegen-generated "fast" selection.
if (FastIS->SelectInstruction(BI)) {
// Then handle certain instructions as single-LLVM-Instruction blocks.
if (isa<CallInst>(BI)) {
if (EnableFastISelVerbose || EnableFastISelAbort) {
- errs() << "FastISel missed call: ";
+ dbgs() << "FastISel missed call: ";
BI->dump();
}
- if (BI->getType() != Type::getVoidTy(*CurDAG->getContext())) {
+ if (!BI->getType()->isVoidTy()) {
unsigned &R = FuncInfo->ValueMap[BI];
if (!R)
R = FuncInfo->CreateRegForValue(BI);
// For now, be a little lenient about non-branch terminators.
if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
if (EnableFastISelVerbose || EnableFastISelAbort) {
- errs() << "FastISel miss: ";
+ dbgs() << "FastISel miss: ";
BI->dump();
}
if (EnableFastISelAbort)
void
SelectionDAGISel::FinishBasicBlock() {
- DEBUG(errs() << "Target-post-processed machine code:\n");
+ DEBUG(dbgs() << "Target-post-processed machine code:\n");
DEBUG(BB->dump());
- DEBUG(errs() << "Total amount of phi nodes to update: "
+ DEBUG(dbgs() << "Total amount of phi nodes to update: "
<< SDB->PHINodesToUpdate.size() << "\n");
DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
- errs() << "Node " << i << " : ("
+ dbgs() << "Node " << i << " : ("
<< SDB->PHINodesToUpdate[i].first
<< ", " << SDB->PHINodesToUpdate[i].second << ")\n");
}
// Add this to the output node.
- EVT IntPtrTy = TLI.getPointerTy();
Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
- IntPtrTy));
+ MVT::i32));
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
i += 2;
}
return !isNonImmUse(Root, N, U);
}
-SDNode *SelectionDAGISel::Select_INLINEASM(SDValue N) {
- std::vector<SDValue> Ops(N.getNode()->op_begin(), N.getNode()->op_end());
+SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
+ std::vector<SDValue> Ops(N->op_begin(), N->op_end());
SelectInlineAsmMemoryOperands(Ops);
std::vector<EVT> VTs;
VTs.push_back(MVT::Other);
VTs.push_back(MVT::Flag);
- SDValue New = CurDAG->getNode(ISD::INLINEASM, N.getDebugLoc(),
+ SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
VTs, &Ops[0], Ops.size());
return New.getNode();
}
-SDNode *SelectionDAGISel::Select_UNDEF(const SDValue &N) {
- return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::IMPLICIT_DEF,
- N.getValueType());
-}
-
-SDNode *SelectionDAGISel::Select_DBG_LABEL(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- unsigned C = cast<LabelSDNode>(N)->getLabelID();
- SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::DBG_LABEL,
- MVT::Other, Tmp, Chain);
+SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
+ return CurDAG->SelectNodeTo(N, TargetInstrInfo::IMPLICIT_DEF,
+ N->getValueType(0));
}
-SDNode *SelectionDAGISel::Select_EH_LABEL(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *SelectionDAGISel::Select_EH_LABEL(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
unsigned C = cast<LabelSDNode>(N)->getLabelID();
SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EH_LABEL,
+ return CurDAG->SelectNodeTo(N, TargetInstrInfo::EH_LABEL,
MVT::Other, Tmp, Chain);
}
-void SelectionDAGISel::CannotYetSelect(SDValue N) {
+void SelectionDAGISel::CannotYetSelect(SDNode *N) {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Cannot yet select: ";
- N.getNode()->print(Msg, CurDAG);
+ N->print(Msg, CurDAG);
llvm_report_error(Msg.str());
}
-void SelectionDAGISel::CannotYetSelectIntrinsic(SDValue N) {
- errs() << "Cannot yet select: ";
+void SelectionDAGISel::CannotYetSelectIntrinsic(SDNode *N) {
+ dbgs() << "Cannot yet select: ";
unsigned iid =
- cast<ConstantSDNode>(N.getOperand(N.getOperand(0).getValueType() == MVT::Other))->getZExtValue();
+ cast<ConstantSDNode>(N->getOperand(N->getOperand(0).getValueType() == MVT::Other))->getZExtValue();
if (iid < Intrinsic::num_intrinsics)
llvm_report_error("Cannot yet select: intrinsic %" + Intrinsic::getName((Intrinsic::ID)iid));
else if (const TargetIntrinsicInfo *tii = TM.getIntrinsicInfo())
projects / oota-llvm.git / blobdiff