//
// The LLVM Compiler Infrastructure
//
-// This file was developed by James M. Laskey and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "sched"
+#define DEBUG_TYPE "pre-RA-sched"
+#include "llvm/Type.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
-#include <iostream>
using namespace llvm;
+ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
+ const TargetMachine &tm)
+ : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) {
+ TII = TM.getInstrInfo();
+ MRI = TM.getRegisterInfo();
+ ConstPool = BB->getParent()->getConstantPool();
+}
+
+/// CheckForPhysRegDependency - Check if the dependency between def and use of
+/// a specified operand is a physical register dependency. If so, returns the
+/// register and the cost of copying the register.
+static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op,
+ const MRegisterInfo *MRI,
+ const TargetInstrInfo *TII,
+ unsigned &PhysReg, int &Cost) {
+ if (Op != 2 || Use->getOpcode() != ISD::CopyToReg)
+ return;
+
+ unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
+ if (MRegisterInfo::isVirtualRegister(Reg))
+ return;
+
+ unsigned ResNo = Use->getOperand(2).ResNo;
+ if (Def->isTargetOpcode()) {
+ const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode());
+ if (ResNo >= II.numDefs &&
+ II.ImplicitDefs[ResNo - II.numDefs] == Reg) {
+ PhysReg = Reg;
+ const TargetRegisterClass *RC =
+ MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg);
+ Cost = RC->getCopyCost();
+ }
+ }
+}
+
+SUnit *ScheduleDAG::Clone(SUnit *Old) {
+ SUnit *SU = NewSUnit(Old->Node);
+ for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i)
+ SU->FlaggedNodes.push_back(SU->FlaggedNodes[i]);
+ SU->InstanceNo = SUnitMap[Old->Node].size();
+ SU->Latency = Old->Latency;
+ SU->isTwoAddress = Old->isTwoAddress;
+ SU->isCommutable = Old->isCommutable;
+ SU->hasPhysRegDefs = Old->hasPhysRegDefs;
+ SUnitMap[Old->Node].push_back(SU);
+ return SU;
+}
+
/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
/// This SUnit graph is similar to the SelectionDAG, but represents flagged
// invalidated.
SUnits.reserve(std::distance(DAG.allnodes_begin(), DAG.allnodes_end()));
- const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
-
for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
E = DAG.allnodes_end(); NI != E; ++NI) {
if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
continue;
// If this node has already been processed, stop now.
- if (SUnitMap[NI]) continue;
+ if (SUnitMap[NI].size()) continue;
SUnit *NodeSUnit = NewSUnit(NI);
// Scan up, adding flagged preds to FlaggedNodes.
SDNode *N = NI;
- while (N->getNumOperands() &&
- N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
- N = N->getOperand(N->getNumOperands()-1).Val;
- NodeSUnit->FlaggedNodes.push_back(N);
- SUnitMap[N] = NodeSUnit;
+ if (N->getNumOperands() &&
+ N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
+ do {
+ N = N->getOperand(N->getNumOperands()-1).Val;
+ NodeSUnit->FlaggedNodes.push_back(N);
+ SUnitMap[N].push_back(NodeSUnit);
+ } while (N->getNumOperands() &&
+ N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
+ std::reverse(NodeSUnit->FlaggedNodes.begin(),
+ NodeSUnit->FlaggedNodes.end());
}
// Scan down, adding this node and any flagged succs to FlaggedNodes if they
if (FlagVal.isOperand(*UI)) {
HasFlagUse = true;
NodeSUnit->FlaggedNodes.push_back(N);
- SUnitMap[N] = NodeSUnit;
+ SUnitMap[N].push_back(NodeSUnit);
N = *UI;
break;
}
- if (!HasFlagUse) break;
+ if (!HasFlagUse) break;
}
// Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
// Update the SUnit
NodeSUnit->Node = N;
- SUnitMap[N] = NodeSUnit;
-
- // Compute the latency for the node. We use the sum of the latencies for
- // all nodes flagged together into this SUnit.
- if (InstrItins.isEmpty()) {
- // No latency information.
- NodeSUnit->Latency = 1;
- } else {
- NodeSUnit->Latency = 0;
- if (N->isTargetOpcode()) {
- unsigned SchedClass = TII->getSchedClass(N->getTargetOpcode());
- InstrStage *S = InstrItins.begin(SchedClass);
- InstrStage *E = InstrItins.end(SchedClass);
- for (; S != E; ++S)
- NodeSUnit->Latency += S->Cycles;
- }
- for (unsigned i = 0, e = NodeSUnit->FlaggedNodes.size(); i != e; ++i) {
- SDNode *FNode = NodeSUnit->FlaggedNodes[i];
- if (FNode->isTargetOpcode()) {
- unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
- InstrStage *S = InstrItins.begin(SchedClass);
- InstrStage *E = InstrItins.end(SchedClass);
- for (; S != E; ++S)
- NodeSUnit->Latency += S->Cycles;
- }
- }
- }
+ SUnitMap[N].push_back(NodeSUnit);
+
+ ComputeLatency(NodeSUnit);
}
// Pass 2: add the preds, succs, etc.
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
- if (TII->isTwoAddrInstr(Opc))
- SU->isTwoAddress = true;
- if (TII->isCommutableInstr(Opc))
+ const TargetInstrDescriptor &TID = TII->get(Opc);
+ for (unsigned i = 0; i != TID.numOperands; ++i) {
+ if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
+ SU->isTwoAddress = true;
+ break;
+ }
+ }
+ if (TID.Flags & M_COMMUTABLE)
SU->isCommutable = true;
}
for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
SDNode *N = SU->FlaggedNodes[n];
+ if (N->isTargetOpcode() &&
+ TII->getImplicitDefs(N->getTargetOpcode()) &&
+ CountResults(N) > (unsigned)TII->getNumDefs(N->getTargetOpcode()))
+ SU->hasPhysRegDefs = true;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
SDNode *OpN = N->getOperand(i).Val;
if (isPassiveNode(OpN)) continue; // Not scheduled.
- SUnit *OpSU = SUnitMap[OpN];
+ SUnit *OpSU = SUnitMap[OpN].front();
assert(OpSU && "Node has no SUnit!");
if (OpSU == SU) continue; // In the same group.
MVT::ValueType OpVT = N->getOperand(i).getValueType();
assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
bool isChain = OpVT == MVT::Other;
-
- if (SU->Preds.insert(std::make_pair(OpSU, isChain)).second) {
- if (!isChain) {
- SU->NumPreds++;
- SU->NumPredsLeft++;
- } else {
- SU->NumChainPredsLeft++;
- }
- }
- if (OpSU->Succs.insert(std::make_pair(SU, isChain)).second) {
- if (!isChain) {
- OpSU->NumSuccs++;
- OpSU->NumSuccsLeft++;
- } else {
- OpSU->NumChainSuccsLeft++;
- }
- }
+
+ unsigned PhysReg = 0;
+ int Cost = 1;
+ // Determine if this is a physical register dependency.
+ CheckForPhysRegDependency(OpN, N, i, MRI, TII, PhysReg, Cost);
+ SU->addPred(OpSU, isChain, false, PhysReg, Cost);
}
}
return;
}
-static void CalculateDepths(SUnit *SU, unsigned Depth) {
- if (SU->Depth == 0 || Depth > SU->Depth) {
- SU->Depth = Depth;
- for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Succs.begin(),
- E = SU->Succs.end(); I != E; ++I)
- CalculateDepths(I->first, Depth+1);
+void ScheduleDAG::ComputeLatency(SUnit *SU) {
+ const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
+
+ // Compute the latency for the node. We use the sum of the latencies for
+ // all nodes flagged together into this SUnit.
+ if (InstrItins.isEmpty()) {
+ // No latency information.
+ SU->Latency = 1;
+ } else {
+ SU->Latency = 0;
+ if (SU->Node->isTargetOpcode()) {
+ unsigned SchedClass = TII->getSchedClass(SU->Node->getTargetOpcode());
+ InstrStage *S = InstrItins.begin(SchedClass);
+ InstrStage *E = InstrItins.end(SchedClass);
+ for (; S != E; ++S)
+ SU->Latency += S->Cycles;
+ }
+ for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i) {
+ SDNode *FNode = SU->FlaggedNodes[i];
+ if (FNode->isTargetOpcode()) {
+ unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
+ InstrStage *S = InstrItins.begin(SchedClass);
+ InstrStage *E = InstrItins.end(SchedClass);
+ for (; S != E; ++S)
+ SU->Latency += S->Cycles;
+ }
+ }
}
}
void ScheduleDAG::CalculateDepths() {
- SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
- ::CalculateDepths(Entry, 0U);
+ std::vector<std::pair<SUnit*, unsigned> > WorkList;
for (unsigned i = 0, e = SUnits.size(); i != e; ++i)
- if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
- ::CalculateDepths(&SUnits[i], 0U);
+ if (SUnits[i].Preds.size() == 0)
+ WorkList.push_back(std::make_pair(&SUnits[i], 0U));
+
+ while (!WorkList.empty()) {
+ SUnit *SU = WorkList.back().first;
+ unsigned Depth = WorkList.back().second;
+ WorkList.pop_back();
+ if (SU->Depth == 0 || Depth > SU->Depth) {
+ SU->Depth = Depth;
+ for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
+ I != E; ++I)
+ WorkList.push_back(std::make_pair(I->Dep, Depth+1));
}
-}
-
-static void CalculateHeights(SUnit *SU, unsigned Height) {
- if (SU->Height == 0 || Height > SU->Height) {
- SU->Height = Height;
- for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
- E = SU->Preds.end(); I != E; ++I)
- CalculateHeights(I->first, Height+1);
}
}
+
void ScheduleDAG::CalculateHeights() {
- SUnit *Root = SUnitMap[DAG.getRoot().Val];
- ::CalculateHeights(Root, 0U);
+ std::vector<std::pair<SUnit*, unsigned> > WorkList;
+ SUnit *Root = SUnitMap[DAG.getRoot().Val].front();
+ WorkList.push_back(std::make_pair(Root, 0U));
+
+ while (!WorkList.empty()) {
+ SUnit *SU = WorkList.back().first;
+ unsigned Height = WorkList.back().second;
+ WorkList.pop_back();
+ if (SU->Height == 0 || Height > SU->Height) {
+ SU->Height = Height;
+ for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
+ I != E; ++I)
+ WorkList.push_back(std::make_pair(I->Dep, Height+1));
+ }
+ }
}
/// CountResults - The results of target nodes have register or immediate
/// operands first, then an optional chain, and optional flag operands (which do
/// not go into the machine instrs.)
-static unsigned CountResults(SDNode *Node) {
+unsigned ScheduleDAG::CountResults(SDNode *Node) {
unsigned N = Node->getNumValues();
while (N && Node->getValueType(N - 1) == MVT::Flag)
--N;
/// CountOperands The inputs to target nodes have any actual inputs first,
/// followed by an optional chain operand, then flag operands. Compute the
/// number of actual operands that will go into the machine instr.
-static unsigned CountOperands(SDNode *Node) {
+unsigned ScheduleDAG::CountOperands(SDNode *Node) {
unsigned N = Node->getNumOperands();
while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
--N;
return N;
}
-static unsigned CreateVirtualRegisters(MachineInstr *MI,
- unsigned NumResults,
- SSARegMap *RegMap,
- const TargetInstrInfo *TII,
- const TargetInstrDescriptor &II) {
- // Create the result registers for this node and add the result regs to
- // the machine instruction.
- unsigned ResultReg =
- RegMap->createVirtualRegister(TII->getInstrOperandRegClass(&II, 0));
- MI->addRegOperand(ResultReg, MachineOperand::Def);
- for (unsigned i = 1; i != NumResults; ++i) {
- const TargetRegisterClass *RC = TII->getInstrOperandRegClass(&II, i);
- assert(RC && "Isn't a register operand!");
- MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
+static const TargetRegisterClass *getInstrOperandRegClass(
+ const MRegisterInfo *MRI,
+ const TargetInstrInfo *TII,
+ const TargetInstrDescriptor *II,
+ unsigned Op) {
+ if (Op >= II->numOperands) {
+ assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
+ return NULL;
+ }
+ const TargetOperandInfo &toi = II->OpInfo[Op];
+ return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
+ ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
+}
+
+void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
+ unsigned InstanceNo, unsigned SrcReg,
+ DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ unsigned VRBase = 0;
+ if (MRegisterInfo::isVirtualRegister(SrcReg)) {
+ // Just use the input register directly!
+ if (InstanceNo > 0)
+ VRBaseMap.erase(SDOperand(Node, ResNo));
+ bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo),SrcReg));
+ assert(isNew && "Node emitted out of order - early");
+ return;
+ }
+
+ // If the node is only used by a CopyToReg and the dest reg is a vreg, use
+ // the CopyToReg'd destination register instead of creating a new vreg.
+ bool MatchReg = true;
+ for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
+ UI != E; ++UI) {
+ SDNode *Use = *UI;
+ bool Match = true;
+ if (Use->getOpcode() == ISD::CopyToReg &&
+ Use->getOperand(2).Val == Node &&
+ Use->getOperand(2).ResNo == ResNo) {
+ unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
+ if (MRegisterInfo::isVirtualRegister(DestReg)) {
+ VRBase = DestReg;
+ Match = false;
+ } else if (DestReg != SrcReg)
+ Match = false;
+ } else {
+ for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
+ SDOperand Op = Use->getOperand(i);
+ if (Op.Val != Node || Op.ResNo != ResNo)
+ continue;
+ MVT::ValueType VT = Node->getValueType(Op.ResNo);
+ if (VT != MVT::Other && VT != MVT::Flag)
+ Match = false;
+ }
+ }
+ MatchReg &= Match;
+ if (VRBase)
+ break;
+ }
+
+ const TargetRegisterClass *TRC = 0;
+ // Figure out the register class to create for the destreg.
+ if (VRBase)
+ TRC = RegInfo.getRegClass(VRBase);
+ else
+ TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg);
+
+ // If all uses are reading from the src physical register and copying the
+ // register is either impossible or very expensive, then don't create a copy.
+ if (MatchReg && TRC->getCopyCost() < 0) {
+ VRBase = SrcReg;
+ } else {
+ // Create the reg, emit the copy.
+ VRBase = RegInfo.createVirtualRegister(TRC);
+ TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
+ }
+
+ if (InstanceNo > 0)
+ VRBaseMap.erase(SDOperand(Node, ResNo));
+ bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo), VRBase));
+ assert(isNew && "Node emitted out of order - early");
+}
+
+void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
+ MachineInstr *MI,
+ const TargetInstrDescriptor &II,
+ DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ for (unsigned i = 0; i < II.numDefs; ++i) {
+ // If the specific node value is only used by a CopyToReg and the dest reg
+ // is a vreg, use the CopyToReg'd destination register instead of creating
+ // a new vreg.
+ unsigned VRBase = 0;
+ for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
+ UI != E; ++UI) {
+ SDNode *Use = *UI;
+ if (Use->getOpcode() == ISD::CopyToReg &&
+ Use->getOperand(2).Val == Node &&
+ Use->getOperand(2).ResNo == i) {
+ unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
+ if (MRegisterInfo::isVirtualRegister(Reg)) {
+ VRBase = Reg;
+ MI->addOperand(MachineOperand::CreateReg(Reg, true));
+ break;
+ }
+ }
+ }
+
+ // Create the result registers for this node and add the result regs to
+ // the machine instruction.
+ if (VRBase == 0) {
+ const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
+ assert(RC && "Isn't a register operand!");
+ VRBase = RegInfo.createVirtualRegister(RC);
+ MI->addOperand(MachineOperand::CreateReg(VRBase, true));
+ }
+
+ bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase));
+ assert(isNew && "Node emitted out of order - early");
}
- return ResultReg;
}
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
-static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) {
- std::map<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
+static unsigned getVR(SDOperand Op, DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDOperand, unsigned>::iterator I = VRBaseMap.find(Op);
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
- return I->second + Op.ResNo;
+ return I->second;
}
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
const TargetInstrDescriptor *II,
- std::map<SDNode*, unsigned> &VRBaseMap) {
+ DenseMap<SDOperand, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addRegOperand(VReg, MachineOperand::Use);
+ const TargetInstrDescriptor *TID = MI->getDesc();
+ bool isOptDef = (IIOpNum < TID->numOperands)
+ ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
+ MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
- const TargetRegisterClass *RC = TII->getInstrOperandRegClass(II, IIOpNum);
+ const TargetRegisterClass *RC =
+ getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == RC &&
- "Register class of operand and regclass of use don't agree!");
+ const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
+ if (VRC != RC) {
+ cerr << "Register class of operand and regclass of use don't agree!\n";
+#ifndef NDEBUG
+ cerr << "Operand = " << IIOpNum << "\n";
+ cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
+ cerr << "MI = "; MI->print(cerr);
+ cerr << "VReg = " << VReg << "\n";
+ cerr << "VReg RegClass size = " << VRC->getSize()
+ << ", align = " << VRC->getAlignment() << "\n";
+ cerr << "Expected RegClass size = " << RC->getSize()
+ << ", align = " << RC->getAlignment() << "\n";
+#endif
+ cerr << "Fatal error, aborting.\n";
+ abort();
+ }
}
- } else if (ConstantSDNode *C =
- dyn_cast<ConstantSDNode>(Op)) {
- MI->addImmOperand(C->getValue());
- } else if (RegisterSDNode*R =
- dyn_cast<RegisterSDNode>(Op)) {
- MI->addRegOperand(R->getReg(), MachineOperand::Use);
- } else if (GlobalAddressSDNode *TGA =
- dyn_cast<GlobalAddressSDNode>(Op)) {
- MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
- } else if (BasicBlockSDNode *BB =
- dyn_cast<BasicBlockSDNode>(Op)) {
- MI->addMachineBasicBlockOperand(BB->getBasicBlock());
- } else if (FrameIndexSDNode *FI =
- dyn_cast<FrameIndexSDNode>(Op)) {
- MI->addFrameIndexOperand(FI->getIndex());
- } else if (JumpTableSDNode *JT =
- dyn_cast<JumpTableSDNode>(Op)) {
- MI->addJumpTableIndexOperand(JT->getIndex());
- } else if (ConstantPoolSDNode *CP =
- dyn_cast<ConstantPoolSDNode>(Op)) {
+ } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateImm(C->getValue()));
+ } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
+ } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
+ } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
+ } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
+ } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
+ } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
int Offset = CP->getOffset();
unsigned Align = CP->getAlignment();
+ const Type *Type = CP->getType();
// MachineConstantPool wants an explicit alignment.
if (Align == 0) {
- if (CP->get()->getType() == Type::DoubleTy)
- Align = 3; // always 8-byte align doubles.
- else {
- Align = TM.getTargetData()
- ->getTypeAlignmentShift(CP->get()->getType());
- if (Align == 0) {
- // Alignment of packed types. FIXME!
- Align = TM.getTargetData()->getTypeSize(CP->get()->getType());
- Align = Log2_64(Align);
- }
+ Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
+ if (Align == 0) {
+ // Alignment of vector types. FIXME!
+ Align = TM.getTargetData()->getABITypeSize(Type);
+ Align = Log2_64(Align);
}
}
- unsigned Idx = ConstPool->getConstantPoolIndex(CP->get(), Align);
- MI->addConstantPoolIndexOperand(Idx, Offset);
- } else if (ExternalSymbolSDNode *ES =
- dyn_cast<ExternalSymbolSDNode>(Op)) {
- MI->addExternalSymbolOperand(ES->getSymbol());
+ unsigned Idx;
+ if (CP->isMachineConstantPoolEntry())
+ Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
+ else
+ Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
+ MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
+ } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
+ MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
} else {
assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addRegOperand(VReg, MachineOperand::Use);
+ MI->addOperand(MachineOperand::CreateReg(VReg, false));
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
- const TargetRegisterClass *RC = TII->getInstrOperandRegClass(II, IIOpNum);
+ const TargetRegisterClass *RC =
+ getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == RC &&
+ assert(RegInfo.getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
}
}
}
+// Returns the Register Class of a subregister
+static const TargetRegisterClass *getSubRegisterRegClass(
+ const TargetRegisterClass *TRC,
+ unsigned SubIdx) {
+ // Pick the register class of the subregister
+ MRegisterInfo::regclass_iterator I = TRC->subregclasses_begin() + SubIdx-1;
+ assert(I < TRC->subregclasses_end() &&
+ "Invalid subregister index for register class");
+ return *I;
+}
+
+static const TargetRegisterClass *getSuperregRegisterClass(
+ const TargetRegisterClass *TRC,
+ unsigned SubIdx,
+ MVT::ValueType VT) {
+ // Pick the register class of the superegister for this type
+ for (MRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
+ E = TRC->superregclasses_end(); I != E; ++I)
+ if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
+ return *I;
+ assert(false && "Couldn't find the register class");
+ return 0;
+}
+
+/// EmitSubregNode - Generate machine code for subreg nodes.
+///
+void ScheduleDAG::EmitSubregNode(SDNode *Node,
+ DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ unsigned VRBase = 0;
+ unsigned Opc = Node->getTargetOpcode();
+ if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
+ // If the node is only used by a CopyToReg and the dest reg is a vreg, use
+ // the CopyToReg'd destination register instead of creating a new vreg.
+ for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
+ UI != E; ++UI) {
+ SDNode *Use = *UI;
+ if (Use->getOpcode() == ISD::CopyToReg &&
+ Use->getOperand(2).Val == Node) {
+ unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
+ if (MRegisterInfo::isVirtualRegister(DestReg)) {
+ VRBase = DestReg;
+ break;
+ }
+ }
+ }
+
+ unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue();
+
+ // TODO: If the node is a use of a CopyFromReg from a physical register
+ // fold the extract into the copy now
+
+ // Create the extract_subreg machine instruction.
+ MachineInstr *MI =
+ new MachineInstr(BB, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
+
+ // Figure out the register class to create for the destreg.
+ unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
+ const TargetRegisterClass *TRC = RegInfo.getRegClass(VReg);
+ const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
+
+ if (VRBase) {
+ // Grab the destination register
+ const TargetRegisterClass *DRC = 0;
+ DRC = RegInfo.getRegClass(VRBase);
+ assert(SRC == DRC &&
+ "Source subregister and destination must have the same class");
+ } else {
+ // Create the reg
+ VRBase = RegInfo.createVirtualRegister(SRC);
+ }
+
+ // Add def, source, and subreg index
+ MI->addOperand(MachineOperand::CreateReg(VRBase, true));
+ AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
+ MI->addOperand(MachineOperand::CreateImm(SubIdx));
+
+ } else if (Opc == TargetInstrInfo::INSERT_SUBREG) {
+ assert((Node->getNumOperands() == 2 || Node->getNumOperands() == 3) &&
+ "Malformed insert_subreg node");
+ bool isUndefInput = (Node->getNumOperands() == 2);
+ unsigned SubReg = 0;
+ unsigned SubIdx = 0;
+
+ if (isUndefInput) {
+ SubReg = getVR(Node->getOperand(0), VRBaseMap);
+ SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue();
+ } else {
+ SubReg = getVR(Node->getOperand(1), VRBaseMap);
+ SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
+ }
+
+ // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
+ // to allow coalescing in the allocator
+
+ // If the node is only used by a CopyToReg and the dest reg is a vreg, use
+ // the CopyToReg'd destination register instead of creating a new vreg.
+ // If the CopyToReg'd destination register is physical, then fold the
+ // insert into the copy
+ for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
+ UI != E; ++UI) {
+ SDNode *Use = *UI;
+ if (Use->getOpcode() == ISD::CopyToReg &&
+ Use->getOperand(2).Val == Node) {
+ unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
+ if (MRegisterInfo::isVirtualRegister(DestReg)) {
+ VRBase = DestReg;
+ break;
+ }
+ }
+ }
+
+ // Create the insert_subreg machine instruction.
+ MachineInstr *MI =
+ new MachineInstr(BB, TII->get(TargetInstrInfo::INSERT_SUBREG));
+
+ // Figure out the register class to create for the destreg.
+ const TargetRegisterClass *TRC = 0;
+ if (VRBase) {
+ TRC = RegInfo.getRegClass(VRBase);
+ } else {
+ TRC = getSuperregRegisterClass(RegInfo.getRegClass(SubReg), SubIdx,
+ Node->getValueType(0));
+ assert(TRC && "Couldn't determine register class for insert_subreg");
+ VRBase = RegInfo.createVirtualRegister(TRC); // Create the reg
+ }
+
+ MI->addOperand(MachineOperand::CreateReg(VRBase, true));
+ AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
+ if (!isUndefInput)
+ AddOperand(MI, Node->getOperand(1), 0, 0, VRBaseMap);
+ MI->addOperand(MachineOperand::CreateImm(SubIdx));
+ } else
+ assert(0 && "Node is not a subreg insert or extract");
+
+ bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0), VRBase));
+ assert(isNew && "Node emitted out of order - early");
+}
/// EmitNode - Generate machine code for an node and needed dependencies.
///
-void ScheduleDAG::EmitNode(SDNode *Node,
- std::map<SDNode*, unsigned> &VRBaseMap) {
- unsigned VRBase = 0; // First virtual register for node
-
+void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
+ DenseMap<SDOperand, unsigned> &VRBaseMap) {
// If machine instruction
if (Node->isTargetOpcode()) {
unsigned Opc = Node->getTargetOpcode();
+
+ // Handle subreg insert/extract specially
+ if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
+ Opc == TargetInstrInfo::INSERT_SUBREG) {
+ EmitSubregNode(Node, VRBaseMap);
+ return;
+ }
+
const TargetInstrDescriptor &II = TII->get(Opc);
unsigned NumResults = CountResults(Node);
unsigned NodeOperands = CountOperands(Node);
unsigned NumMIOperands = NodeOperands + NumResults;
+ bool HasPhysRegOuts = (NumResults > II.numDefs) && II.ImplicitDefs;
#ifndef NDEBUG
- assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
+ assert((unsigned(II.numOperands) == NumMIOperands ||
+ HasPhysRegOuts || (II.Flags & M_VARIABLE_OPS)) &&
"#operands for dag node doesn't match .td file!");
#endif
// Create the new machine instruction.
- MachineInstr *MI = new MachineInstr(Opc, NumMIOperands);
+ MachineInstr *MI = new MachineInstr(II);
// Add result register values for things that are defined by this
// instruction.
-
- // If the node is only used by a CopyToReg and the dest reg is a vreg, use
- // the CopyToReg'd destination register instead of creating a new vreg.
- if (NumResults == 1) {
- for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
- UI != E; ++UI) {
- SDNode *Use = *UI;
- if (Use->getOpcode() == ISD::CopyToReg &&
- Use->getOperand(2).Val == Node) {
- unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(Reg)) {
- VRBase = Reg;
- MI->addRegOperand(Reg, MachineOperand::Def);
- break;
- }
- }
- }
- }
-
- // Otherwise, create new virtual registers.
- if (NumResults && VRBase == 0)
- VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, TII, II);
+ if (NumResults)
+ CreateVirtualRegisters(Node, MI, II, VRBaseMap);
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.
for (unsigned i = 0; i != NodeOperands; ++i)
- AddOperand(MI, Node->getOperand(i), i+NumResults, &II, VRBaseMap);
+ AddOperand(MI, Node->getOperand(i), i+II.numDefs, &II, VRBaseMap);
// Commute node if it has been determined to be profitable.
if (CommuteSet.count(Node)) {
MachineInstr *NewMI = TII->commuteInstruction(MI);
if (NewMI == 0)
- DEBUG(std::cerr << "Sched: COMMUTING FAILED!\n");
+ DOUT << "Sched: COMMUTING FAILED!\n";
else {
- DEBUG(std::cerr << "Sched: COMMUTED TO: " << *NewMI);
- MI = NewMI;
+ DOUT << "Sched: COMMUTED TO: " << *NewMI;
+ if (MI != NewMI) {
+ delete MI;
+ MI = NewMI;
+ }
}
}
// taking some custom action.
BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
}
+
+ // Additional results must be an physical register def.
+ if (HasPhysRegOuts) {
+ for (unsigned i = II.numDefs; i < NumResults; ++i) {
+ unsigned Reg = II.ImplicitDefs[i - II.numDefs];
+ if (Node->hasAnyUseOfValue(i))
+ EmitCopyFromReg(Node, i, InstanceNo, Reg, VRBaseMap);
+ }
+ }
} else {
switch (Node->getOpcode()) {
default:
- Node->dump();
+#ifndef NDEBUG
+ Node->dump(&DAG);
+#endif
assert(0 && "This target-independent node should have been selected!");
case ISD::EntryToken: // fall thru
case ISD::TokenFactor:
+ case ISD::LABEL:
break;
case ISD::CopyToReg: {
- unsigned InReg = getVR(Node->getOperand(2), VRBaseMap);
+ unsigned InReg;
+ if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(2)))
+ InReg = R->getReg();
+ else
+ InReg = getVR(Node->getOperand(2), VRBaseMap);
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
- if (InReg != DestReg) // Coalesced away the copy?
- MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
- RegMap->getRegClass(InReg));
+ if (InReg != DestReg) {// Coalesced away the copy?
+ const TargetRegisterClass *TRC = 0;
+ // Get the target register class
+ if (MRegisterInfo::isVirtualRegister(InReg))
+ TRC = RegInfo.getRegClass(InReg);
+ else
+ TRC =
+ MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
+ InReg);
+ TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
+ }
break;
}
case ISD::CopyFromReg: {
unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(SrcReg)) {
- VRBase = SrcReg; // Just use the input register directly!
- break;
- }
-
- // If the node is only used by a CopyToReg and the dest reg is a vreg, use
- // the CopyToReg'd destination register instead of creating a new vreg.
- for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
- UI != E; ++UI) {
- SDNode *Use = *UI;
- if (Use->getOpcode() == ISD::CopyToReg &&
- Use->getOperand(2).Val == Node) {
- unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
- if (MRegisterInfo::isVirtualRegister(DestReg)) {
- VRBase = DestReg;
- break;
- }
- }
- }
-
- // Figure out the register class to create for the destreg.
- const TargetRegisterClass *TRC = 0;
- if (VRBase) {
- TRC = RegMap->getRegClass(VRBase);
- } else {
-
- // Pick the register class of the right type that contains this physreg.
- for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
- E = MRI->regclass_end(); I != E; ++I)
- if ((*I)->hasType(Node->getValueType(0)) &&
- (*I)->contains(SrcReg)) {
- TRC = *I;
- break;
- }
- assert(TRC && "Couldn't find register class for reg copy!");
-
- // Create the reg, emit the copy.
- VRBase = RegMap->createVirtualRegister(TRC);
- }
- MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
+ EmitCopyFromReg(Node, 0, InstanceNo, SrcReg, VRBaseMap);
break;
}
case ISD::INLINEASM: {
// Create the inline asm machine instruction.
MachineInstr *MI =
- new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
+ new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
// Add the asm string as an external symbol operand.
const char *AsmStr =
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
- MI->addExternalSymbolOperand(AsmStr);
+ MI->addOperand(MachineOperand::CreateES(AsmStr));
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps;) {
unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
unsigned NumVals = Flags >> 3;
- MI->addImmOperand(Flags);
+ MI->addOperand(MachineOperand::CreateImm(Flags));
++i; // Skip the ID value.
switch (Flags & 7) {
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addRegOperand(Reg, MachineOperand::Use);
+ MI->addOperand(MachineOperand::CreateReg(Reg, false));
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addRegOperand(Reg, MachineOperand::Def);
+ MI->addOperand(MachineOperand::CreateReg(Reg, true));
}
break;
case 3: { // Immediate.
- assert(NumVals == 1 && "Unknown immediate value!");
- uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
- MI->addImmOperand(Val);
- ++i;
+ for (; NumVals; --NumVals, ++i) {
+ if (ConstantSDNode *CS =
+ dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
+ MI->addOperand(MachineOperand::CreateImm(CS->getValue()));
+ } else if (GlobalAddressSDNode *GA =
+ dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
+ MI->addOperand(MachineOperand::CreateGA(GA->getGlobal(),
+ GA->getOffset()));
+ } else {
+ BasicBlockSDNode *BB =cast<BasicBlockSDNode>(Node->getOperand(i));
+ MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
+ }
+ }
break;
}
case 4: // Addressing mode.
}
}
}
-
- assert(!VRBaseMap.count(Node) && "Node emitted out of order - early");
- VRBaseMap[Node] = VRBase;
}
void ScheduleDAG::EmitNoop() {
TII->insertNoop(*BB, BB->end());
}
+void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap) {
+ for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
+ I != E; ++I) {
+ if (I->isCtrl) continue; // ignore chain preds
+ if (!I->Dep->Node) {
+ // Copy to physical register.
+ DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->Dep);
+ assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
+ // Find the destination physical register.
+ unsigned Reg = 0;
+ for (SUnit::const_succ_iterator II = SU->Succs.begin(),
+ EE = SU->Succs.end(); II != EE; ++II) {
+ if (I->Reg) {
+ Reg = I->Reg;
+ break;
+ }
+ }
+ assert(I->Reg && "Unknown physical register!");
+ TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
+ SU->CopyDstRC, SU->CopySrcRC);
+ } else {
+ // Copy from physical register.
+ assert(I->Reg && "Unknown physical register!");
+ unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC);
+ bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
+ assert(isNew && "Node emitted out of order - early");
+ TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
+ SU->CopyDstRC, SU->CopySrcRC);
+ }
+ break;
+ }
+}
+
/// EmitSchedule - Emit the machine code in scheduled order.
void ScheduleDAG::EmitSchedule() {
// If this is the first basic block in the function, and if it has live ins
// that need to be copied into vregs, emit the copies into the top of the
// block before emitting the code for the block.
MachineFunction &MF = DAG.getMachineFunction();
- if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
- for (MachineFunction::livein_iterator LI = MF.livein_begin(),
- E = MF.livein_end(); LI != E; ++LI)
- if (LI->second)
- MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
- LI->first, RegMap->getRegClass(LI->second));
+ if (&MF.front() == BB) {
+ for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(),
+ E = RegInfo.livein_end(); LI != E; ++LI)
+ if (LI->second) {
+ const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second);
+ TII->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
+ LI->first, RC, RC);
+ }
}
// Finally, emit the code for all of the scheduled instructions.
- std::map<SDNode*, unsigned> VRBaseMap;
+ DenseMap<SDOperand, unsigned> VRBaseMap;
+ DenseMap<SUnit*, unsigned> CopyVRBaseMap;
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i]) {
- for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)
- EmitNode(SU->FlaggedNodes[j], VRBaseMap);
- EmitNode(SU->Node, VRBaseMap);
+ for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; ++j)
+ EmitNode(SU->FlaggedNodes[j], SU->InstanceNo, VRBaseMap);
+ if (SU->Node)
+ EmitNode(SU->Node, SU->InstanceNo, VRBaseMap);
+ else
+ EmitCrossRCCopy(SU, CopyVRBaseMap);
} else {
// Null SUnit* is a noop.
EmitNoop();
if (SUnit *SU = Sequence[i])
SU->dump(&DAG);
else
- std::cerr << "**** NOOP ****\n";
+ cerr << "**** NOOP ****\n";
}
}
/// Run - perform scheduling.
///
MachineBasicBlock *ScheduleDAG::Run() {
- TII = TM.getInstrInfo();
- MRI = TM.getRegisterInfo();
- RegMap = BB->getParent()->getSSARegMap();
- ConstPool = BB->getParent()->getConstantPool();
-
Schedule();
return BB;
}
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
/// a group of nodes flagged together.
void SUnit::dump(const SelectionDAG *G) const {
- std::cerr << "SU(" << NodeNum << "): ";
- Node->dump(G);
- std::cerr << "\n";
+ cerr << "SU(" << NodeNum << "): ";
+ if (Node)
+ Node->dump(G);
+ else
+ cerr << "CROSS RC COPY ";
+ cerr << "\n";
if (FlaggedNodes.size() != 0) {
for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
- std::cerr << " ";
+ cerr << " ";
FlaggedNodes[i]->dump(G);
- std::cerr << "\n";
+ cerr << "\n";
}
}
}
void SUnit::dumpAll(const SelectionDAG *G) const {
dump(G);
- std::cerr << " # preds left : " << NumPredsLeft << "\n";
- std::cerr << " # succs left : " << NumSuccsLeft << "\n";
- std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
- std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
- std::cerr << " Latency : " << Latency << "\n";
- std::cerr << " Depth : " << Depth << "\n";
- std::cerr << " Height : " << Height << "\n";
+ cerr << " # preds left : " << NumPredsLeft << "\n";
+ cerr << " # succs left : " << NumSuccsLeft << "\n";
+ cerr << " Latency : " << Latency << "\n";
+ cerr << " Depth : " << Depth << "\n";
+ cerr << " Height : " << Height << "\n";
if (Preds.size() != 0) {
- std::cerr << " Predecessors:\n";
- for (std::set<std::pair<SUnit*,bool> >::const_iterator I = Preds.begin(),
- E = Preds.end(); I != E; ++I) {
- if (I->second)
- std::cerr << " ch ";
+ cerr << " Predecessors:\n";
+ for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
+ I != E; ++I) {
+ if (I->isCtrl)
+ cerr << " ch #";
else
- std::cerr << " val ";
- I->first->dump(G);
+ cerr << " val #";
+ cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";
+ if (I->isSpecial)
+ cerr << " *";
+ cerr << "\n";
}
}
if (Succs.size() != 0) {
- std::cerr << " Successors:\n";
- for (std::set<std::pair<SUnit*, bool> >::const_iterator I = Succs.begin(),
- E = Succs.end(); I != E; ++I) {
- if (I->second)
- std::cerr << " ch ";
+ cerr << " Successors:\n";
+ for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
+ I != E; ++I) {
+ if (I->isCtrl)
+ cerr << " ch #";
else
- std::cerr << " val ";
- I->first->dump(G);
+ cerr << " val #";
+ cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";
+ if (I->isSpecial)
+ cerr << " *";
+ cerr << "\n";
}
}
- std::cerr << "\n";
+ cerr << "\n";
}
projects / oota-llvm.git / blobdiff