bug 2812: Segmentation fault on a big emdiam processor.

[oota-llvm.git] / lib / CodeGen / SelectionDAG / LegalizeDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index cf471cb59f4fd2e1df8de231a430d61c404e266c..75dd644cb84f5094f82c89d1d713546b130aca88 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -249,7 +249,7 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
           if (InOp.getOpcode() == ISD::UNDEF)
             Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
           else {
-            unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
+            unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
             Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
           }
         }
@@ -442,7 +442,7 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
   // an FP extending load is the same cost as a normal load (such as on the x87
   // fp stack or PPC FP unit).
   MVT VT = CFP->getValueType(0);
-  ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
+  ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
   if (!UseCP) {
     if (VT!=MVT::f64 && VT!=MVT::f32)
       assert(0 && "Invalid type expansion");
@@ -467,12 +467,13 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
   }
 
   SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
+  unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
   if (Extend)
     return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
                           CPIdx, PseudoSourceValue::getConstantPool(),
-                          0, VT);
+                          0, VT, false, Alignment);
   return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
-                     PseudoSourceValue::getConstantPool(), 0);
+                     PseudoSourceValue::getConstantPool(), 0, false, Alignment);
 }
 
 
@@ -1376,7 +1377,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Tmp1 = LegalizeOp(Node->getOperand(0));
       ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
       assert(idx && "Operand must be a constant");
-      Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+      Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
     }
     break;
@@ -1385,7 +1386,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Tmp2 = LegalizeOp(Node->getOperand(1));      
       ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
       assert(idx && "Operand must be a constant");
-      Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+      Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
     }
     break;      
@@ -1451,7 +1452,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           // elt 0 of the RHS.
           SmallVector<SDValue, 8> ShufOps;
           for (unsigned i = 0; i != NumElts; ++i) {
-            if (i != InsertPos->getValue())
+            if (i != InsertPos->getZExtValue())
               ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
             else
               ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
@@ -1527,7 +1528,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
         } else {
           assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-          unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
+          unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
           if (Idx < NumElems)
             Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
                                       DAG.getConstant(Idx, PtrVT)));
@@ -1687,7 +1688,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       SDValue Size  = Tmp2.getOperand(1);
       SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
       Chain = SP.getValue(1);
-      unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
+      unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
       unsigned StackAlign =
         TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
       if (Align > StackAlign)
@@ -1734,7 +1735,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
 
     bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
     for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
-      unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
+      unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
       for (++i; NumVals; ++i, --NumVals) {
         SDValue Op = LegalizeOp(Ops[i]);
         if (Op != Ops[i]) {
@@ -2168,7 +2169,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     switch (getTypeAction(OpTy)) {
     default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
     case Legal:
-      if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
+      if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
         // 1 -> Hi
         Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
                              DAG.getConstant(OpTy.getSizeInBits()/2,
@@ -2183,7 +2184,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case Expand:
       // Get both the low and high parts.
       ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
-      if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
+      if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
         Result = Tmp2;  // 1 -> Hi
       else
         Result = Tmp1;  // 0 -> Lo
@@ -2480,7 +2481,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           ExpandOp(ST->getValue(), Lo, Hi);
           IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
 
-          if (TLI.isBigEndian())
+          if (Hi.getNode() && TLI.isBigEndian())
             std::swap(Lo, Hi);
         }
 
@@ -4554,11 +4555,11 @@ SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
     ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
     SDValue Lo, Hi;
     SplitVectorOp(Vec, Lo, Hi);
-    if (CIdx->getValue() < NumLoElts) {
+    if (CIdx->getZExtValue() < NumLoElts) {
       Vec = Lo;
     } else {
       Vec = Hi;
-      Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
+      Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
                             Idx.getValueType());
     }
   
@@ -4606,11 +4607,12 @@ SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
   ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
   SDValue Lo, Hi;
   SplitVectorOp(Vec, Lo, Hi);
-  if (CIdx->getValue() < NumElems/2) {
+  if (CIdx->getZExtValue() < NumElems/2) {
     Vec = Lo;
   } else {
     Vec = Hi;
-    Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
+    Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
+                          Idx.getValueType());
   }
   
   // It's now an extract from the appropriate high or low part.  Recurse.
@@ -4983,10 +4985,10 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
     for (unsigned i = 0, e = NumElems; i != e; ++i) {
       if (ConstantFPSDNode *V = 
           dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
-        CV.push_back(ConstantFP::get(V->getValueAPF()));
+        CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
       } else if (ConstantSDNode *V = 
                    dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
-        CV.push_back(ConstantInt::get(V->getAPIntValue()));
+        CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
       } else {
         assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
         const Type *OpNTy = 
@@ -4996,8 +4998,10 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
     }
     Constant *CP = ConstantVector::get(CV);
     SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
+    unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
     return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
-                       PseudoSourceValue::getConstantPool(), 0);
+                       PseudoSourceValue::getConstantPool(), 0,
+                       false, Alignment);
   }
   
   if (SplatValue.getNode()) {   // Splat of one value?
@@ -5138,7 +5142,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
 
   // Handle the case when Amt is an immediate.
   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
-    unsigned Cst = CN->getValue();
+    unsigned Cst = CN->getZExtValue();
     // Expand the incoming operand to be shifted, so that we have its parts
     SDValue InL, InH;
     ExpandOp(Op, InL, InH);
@@ -5432,17 +5436,20 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
     static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
 
     SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
+    unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
     CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
+    Alignment = std::min(Alignment, 4u);
     SDValue FudgeInReg;
     if (DestTy == MVT::f32)
       FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
-                               PseudoSourceValue::getConstantPool(), 0);
+                               PseudoSourceValue::getConstantPool(), 0,
+                               false, Alignment);
     else if (DestTy.bitsGT(MVT::f32))
       // FIXME: Avoid the extend by construction the right constantpool?
       FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
                                   CPIdx,
                                   PseudoSourceValue::getConstantPool(), 0,
-                                  MVT::f32);
+                                  MVT::f32, false, Alignment);
     else 
       assert(0 && "Unexpected conversion");
 
@@ -5581,17 +5588,20 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
   static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
 
   SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
+  unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
   CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
+  Alignment = std::min(Alignment, 4u);
   SDValue FudgeInReg;
   if (DestVT == MVT::f32)
     FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
-                             PseudoSourceValue::getConstantPool(), 0);
+                             PseudoSourceValue::getConstantPool(), 0,
+                             false, Alignment);
   else {
     FudgeInReg =
       LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
                                 DAG.getEntryNode(), CPIdx,
                                 PseudoSourceValue::getConstantPool(), 0,
-                                MVT::f32));
+                                MVT::f32, false, Alignment));
   }
 
   return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
@@ -5876,7 +5886,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     abort();
   case ISD::EXTRACT_ELEMENT:
     ExpandOp(Node->getOperand(0), Lo, Hi);
-    if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
+    if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
       return ExpandOp(Hi, Lo, Hi);
     return ExpandOp(Lo, Lo, Hi);
   case ISD::EXTRACT_VECTOR_ELT:
@@ -6863,7 +6873,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
   case ISD::INSERT_VECTOR_ELT: {
     if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
       SplitVectorOp(Node->getOperand(0), Lo, Hi);
-      unsigned Index = Idx->getValue();
+      unsigned Index = Idx->getZExtValue();
       SDValue ScalarOp = Node->getOperand(1);
       if (Index < NewNumElts_Lo)
         Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
@@ -6894,7 +6904,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
         Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
         continue;
       }
-      unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
+      unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
       SDValue InVec = Node->getOperand(0);
       if (Idx >= NumElements) {
         InVec = Node->getOperand(1);
@@ -6912,7 +6922,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
         Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
         continue;
       }
-      unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
+      unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
       SDValue InVec = Node->getOperand(0);
       if (Idx >= NumElements) {
         InVec = Node->getOperand(1);
@@ -7240,7 +7250,7 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
   case ISD::VECTOR_SHUFFLE: {
     // Figure out if the scalar is the LHS or RHS and return it.
     SDValue EltNum = Node->getOperand(2).getOperand(0);
-    if (cast<ConstantSDNode>(EltNum)->getValue())
+    if (cast<ConstantSDNode>(EltNum)->getZExtValue())
       Result = ScalarizeVectorOp(Node->getOperand(1));
     else
       Result = ScalarizeVectorOp(Node->getOperand(0));