// some kind of hint from the target that int div is expensive.
// various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
//
-// FIXME: Should add a corresponding version of fold AND with
-// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
-// we don't have yet.
-//
// FIXME: select C, pow2, pow2 -> something smart
// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
// FIXME: Dead stores -> nuke
// FIXME: mul (x, const) -> shifts + adds
// FIXME: undef values
// FIXME: make truncate see through SIGN_EXTEND and AND
-// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
-// FIXME: verify that getNode can't return extends with an operand whose type
-// is >= to that of the extend.
// FIXME: divide by zero is currently left unfolded. do we want to turn this
// into an undef?
// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetLowering.h"
+#include "llvm/Support/Visibility.h"
#include <algorithm>
#include <cmath>
#include <iostream>
using namespace llvm;
namespace {
- Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
+ static Statistic<> NodesCombined ("dagcombiner",
+ "Number of dag nodes combined");
- class DAGCombiner {
+ class VISIBILITY_HIDDEN DAGCombiner {
SelectionDAG &DAG;
TargetLowering &TLI;
bool AfterLegalize;
}
/// removeFromWorkList - remove all instances of N from the worklist.
+ ///
void removeFromWorkList(SDNode *N) {
WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
WorkList.end());
}
+ public:
+ void AddToWorkList(SDNode *N) {
+ WorkList.push_back(N);
+ }
+
SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
++NodesCombined;
DEBUG(std::cerr << "\nReplacing "; N->dump();
- std::cerr << "\nWith: "; To[0].Val->dump();
+ std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
std::cerr << " and " << To.size()-1 << " other values\n");
std::vector<SDNode*> NowDead;
DAG.ReplaceAllUsesWith(N, To, &NowDead);
return SDOperand(N, 0);
}
+ SDOperand CombineTo(SDNode *N, SDOperand Res) {
+ std::vector<SDOperand> To;
+ To.push_back(Res);
+ return CombineTo(N, To);
+ }
+
+ SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
+ std::vector<SDOperand> To;
+ To.push_back(Res0);
+ To.push_back(Res1);
+ return CombineTo(N, To);
+ }
+ private:
+
/// SimplifyDemandedBits - Check the specified integer node value to see if
- /// it can be simplified or if things is uses can be simplified by bit
+ /// it can be simplified or if things it uses can be simplified by bit
/// propagation. If so, return true.
bool SimplifyDemandedBits(SDOperand Op) {
TargetLowering::TargetLoweringOpt TLO(DAG);
// Replace the old value with the new one.
++NodesCombined;
DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
- std::cerr << "\nWith: "; TLO.New.Val->dump());
+ std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG));
std::vector<SDNode*> NowDead;
DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
- // Push the new node and any (now) users onto the worklist.
+ // Push the new node and any (possibly new) users onto the worklist.
WorkList.push_back(TLO.New.Val);
AddUsersToWorkList(TLO.New.Val);
// Nodes can end up on the worklist more than once. Make sure we do
// not process a node that has been replaced.
- removeFromWorkList(TLO.Old.Val);
for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
removeFromWorkList(NowDead[i]);
- // Finally, since the node is now dead, remove it from the graph.
- DAG.DeleteNode(TLO.Old.Val);
+ // Finally, if the node is now dead, remove it from the graph. The node
+ // may not be dead if the replacement process recursively simplified to
+ // something else needing this node.
+ if (TLO.Old.Val->use_empty()) {
+ removeFromWorkList(TLO.Old.Val);
+ DAG.DeleteNode(TLO.Old.Val);
+ }
return true;
}
- SDOperand CombineTo(SDNode *N, SDOperand Res) {
- std::vector<SDOperand> To;
- To.push_back(Res);
- return CombineTo(N, To);
- }
-
- SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
- std::vector<SDOperand> To;
- To.push_back(Res0);
- To.push_back(Res1);
- return CombineTo(N, To);
- }
-
/// visit - call the node-specific routine that knows how to fold each
/// particular type of node.
SDOperand visit(SDNode *N);
SDOperand visitAND(SDNode *N);
SDOperand visitOR(SDNode *N);
SDOperand visitXOR(SDNode *N);
+ SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
SDOperand visitSHL(SDNode *N);
SDOperand visitSRA(SDNode *N);
SDOperand visitSRL(SDNode *N);
SDOperand visitSETCC(SDNode *N);
SDOperand visitSIGN_EXTEND(SDNode *N);
SDOperand visitZERO_EXTEND(SDNode *N);
+ SDOperand visitANY_EXTEND(SDNode *N);
SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
SDOperand visitTRUNCATE(SDNode *N);
SDOperand visitBIT_CONVERT(SDNode *N);
+ SDOperand visitVBIT_CONVERT(SDNode *N);
SDOperand visitFADD(SDNode *N);
SDOperand visitFSUB(SDNode *N);
SDOperand visitFMUL(SDNode *N);
SDOperand visitFDIV(SDNode *N);
SDOperand visitFREM(SDNode *N);
+ SDOperand visitFCOPYSIGN(SDNode *N);
SDOperand visitSINT_TO_FP(SDNode *N);
SDOperand visitUINT_TO_FP(SDNode *N);
SDOperand visitFP_TO_SINT(SDNode *N);
SDOperand visitFNEG(SDNode *N);
SDOperand visitFABS(SDNode *N);
SDOperand visitBRCOND(SDNode *N);
- SDOperand visitBRCONDTWOWAY(SDNode *N);
SDOperand visitBR_CC(SDNode *N);
- SDOperand visitBRTWOWAY_CC(SDNode *N);
SDOperand visitLOAD(SDNode *N);
+ SDOperand visitXEXTLOAD(SDNode *N);
SDOperand visitSTORE(SDNode *N);
+ SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
+ SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
+ SDOperand visitVBUILD_VECTOR(SDNode *N);
+ SDOperand visitVECTOR_SHUFFLE(SDNode *N);
+ SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
+ SDOperand XformToShuffleWithZero(SDNode *N);
SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
+ SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
SDOperand N3, ISD::CondCode CC);
SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
ISD::CondCode Cond, bool foldBooleans = true);
-
+ SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
SDOperand BuildSDIV(SDNode *N);
SDOperand BuildUDIV(SDNode *N);
public:
};
}
-struct ms {
- int64_t m; // magic number
- int64_t s; // shift amount
-};
-
-struct mu {
- uint64_t m; // magic number
- int64_t a; // add indicator
- int64_t s; // shift amount
-};
-
-/// magic - calculate the magic numbers required to codegen an integer sdiv as
-/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
-/// or -1.
-static ms magic32(int32_t d) {
- int32_t p;
- uint32_t ad, anc, delta, q1, r1, q2, r2, t;
- const uint32_t two31 = 0x80000000U;
- struct ms mag;
-
- ad = abs(d);
- t = two31 + ((uint32_t)d >> 31);
- anc = t - 1 - t%ad; // absolute value of nc
- p = 31; // initialize p
- q1 = two31/anc; // initialize q1 = 2p/abs(nc)
- r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
- q2 = two31/ad; // initialize q2 = 2p/abs(d)
- r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
- do {
- p = p + 1;
- q1 = 2*q1; // update q1 = 2p/abs(nc)
- r1 = 2*r1; // update r1 = rem(2p/abs(nc))
- if (r1 >= anc) { // must be unsigned comparison
- q1 = q1 + 1;
- r1 = r1 - anc;
- }
- q2 = 2*q2; // update q2 = 2p/abs(d)
- r2 = 2*r2; // update r2 = rem(2p/abs(d))
- if (r2 >= ad) { // must be unsigned comparison
- q2 = q2 + 1;
- r2 = r2 - ad;
- }
- delta = ad - r2;
- } while (q1 < delta || (q1 == delta && r1 == 0));
-
- mag.m = (int32_t)(q2 + 1); // make sure to sign extend
- if (d < 0) mag.m = -mag.m; // resulting magic number
- mag.s = p - 32; // resulting shift
- return mag;
-}
-
-/// magicu - calculate the magic numbers required to codegen an integer udiv as
-/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
-static mu magicu32(uint32_t d) {
- int32_t p;
- uint32_t nc, delta, q1, r1, q2, r2;
- struct mu magu;
- magu.a = 0; // initialize "add" indicator
- nc = - 1 - (-d)%d;
- p = 31; // initialize p
- q1 = 0x80000000/nc; // initialize q1 = 2p/nc
- r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
- q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
- r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
- do {
- p = p + 1;
- if (r1 >= nc - r1 ) {
- q1 = 2*q1 + 1; // update q1
- r1 = 2*r1 - nc; // update r1
- }
- else {
- q1 = 2*q1; // update q1
- r1 = 2*r1; // update r1
- }
- if (r2 + 1 >= d - r2) {
- if (q2 >= 0x7FFFFFFF) magu.a = 1;
- q2 = 2*q2 + 1; // update q2
- r2 = 2*r2 + 1 - d; // update r2
- }
- else {
- if (q2 >= 0x80000000) magu.a = 1;
- q2 = 2*q2; // update q2
- r2 = 2*r2 + 1; // update r2
- }
- delta = d - 1 - r2;
- } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
- magu.m = q2 + 1; // resulting magic number
- magu.s = p - 32; // resulting shift
- return magu;
-}
-
-/// magic - calculate the magic numbers required to codegen an integer sdiv as
-/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
-/// or -1.
-static ms magic64(int64_t d) {
- int64_t p;
- uint64_t ad, anc, delta, q1, r1, q2, r2, t;
- const uint64_t two63 = 9223372036854775808ULL; // 2^63
- struct ms mag;
-
- ad = d >= 0 ? d : -d;
- t = two63 + ((uint64_t)d >> 63);
- anc = t - 1 - t%ad; // absolute value of nc
- p = 63; // initialize p
- q1 = two63/anc; // initialize q1 = 2p/abs(nc)
- r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
- q2 = two63/ad; // initialize q2 = 2p/abs(d)
- r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
- do {
- p = p + 1;
- q1 = 2*q1; // update q1 = 2p/abs(nc)
- r1 = 2*r1; // update r1 = rem(2p/abs(nc))
- if (r1 >= anc) { // must be unsigned comparison
- q1 = q1 + 1;
- r1 = r1 - anc;
- }
- q2 = 2*q2; // update q2 = 2p/abs(d)
- r2 = 2*r2; // update r2 = rem(2p/abs(d))
- if (r2 >= ad) { // must be unsigned comparison
- q2 = q2 + 1;
- r2 = r2 - ad;
- }
- delta = ad - r2;
- } while (q1 < delta || (q1 == delta && r1 == 0));
-
- mag.m = q2 + 1;
- if (d < 0) mag.m = -mag.m; // resulting magic number
- mag.s = p - 64; // resulting shift
- return mag;
-}
-
-/// magicu - calculate the magic numbers required to codegen an integer udiv as
-/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
-static mu magicu64(uint64_t d)
-{
- int64_t p;
- uint64_t nc, delta, q1, r1, q2, r2;
- struct mu magu;
- magu.a = 0; // initialize "add" indicator
- nc = - 1 - (-d)%d;
- p = 63; // initialize p
- q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
- r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
- q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
- r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
- do {
- p = p + 1;
- if (r1 >= nc - r1 ) {
- q1 = 2*q1 + 1; // update q1
- r1 = 2*r1 - nc; // update r1
- }
- else {
- q1 = 2*q1; // update q1
- r1 = 2*r1; // update r1
- }
- if (r2 + 1 >= d - r2) {
- if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
- q2 = 2*q2 + 1; // update q2
- r2 = 2*r2 + 1 - d; // update r2
- }
- else {
- if (q2 >= 0x8000000000000000ull) magu.a = 1;
- q2 = 2*q2; // update q2
- r2 = 2*r2 + 1; // update r2
- }
- delta = d - 1 - r2;
- } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
- magu.m = q2 + 1; // resulting magic number
- magu.s = p - 64; // resulting shift
- return magu;
+//===----------------------------------------------------------------------===//
+// TargetLowering::DAGCombinerInfo implementation
+//===----------------------------------------------------------------------===//
+
+void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
+ ((DAGCombiner*)DC)->AddToWorkList(N);
}
+SDOperand TargetLowering::DAGCombinerInfo::
+CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
+ return ((DAGCombiner*)DC)->CombineTo(N, To);
+}
+
+SDOperand TargetLowering::DAGCombinerInfo::
+CombineTo(SDNode *N, SDOperand Res) {
+ return ((DAGCombiner*)DC)->CombineTo(N, Res);
+}
+
+
+SDOperand TargetLowering::DAGCombinerInfo::
+CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
+ return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
+}
+
+
+
+
+//===----------------------------------------------------------------------===//
+
+
// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
// that selects between the values 1 and 0, making it equivalent to a setcc.
// Also, set the incoming LHS, RHS, and CC references to the appropriate
if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
if (isa<ConstantSDNode>(N1)) {
SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
- WorkList.push_back(OpNode.Val);
+ AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
} else if (N0.hasOneUse()) {
SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
- WorkList.push_back(OpNode.Val);
+ AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
}
}
if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
if (isa<ConstantSDNode>(N0)) {
SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
- WorkList.push_back(OpNode.Val);
+ AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
} else if (N1.hasOneUse()) {
SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
- WorkList.push_back(OpNode.Val);
+ AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
}
}
// changes of the root.
HandleSDNode Dummy(DAG.getRoot());
+
+ /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
+ TargetLowering::DAGCombinerInfo
+ DagCombineInfo(DAG, !RunningAfterLegalize, this);
+
// while the worklist isn't empty, inspect the node on the end of it and
// try and combine it.
while (!WorkList.empty()) {
}
SDOperand RV = visit(N);
+
+ // If nothing happened, try a target-specific DAG combine.
+ if (RV.Val == 0) {
+ assert(N->getOpcode() != ISD::DELETED_NODE &&
+ "Node was deleted but visit returned NULL!");
+ if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
+ TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
+ RV = TLI.PerformDAGCombine(N, DagCombineInfo);
+ }
+
if (RV.Val) {
++NodesCombined;
// If we get back the same node we passed in, rather than a new node or
// CombineTo was used. Since CombineTo takes care of the worklist
// mechanics for us, we have no work to do in this case.
if (RV.Val != N) {
+ assert(N->getOpcode() != ISD::DELETED_NODE &&
+ RV.Val->getOpcode() != ISD::DELETED_NODE &&
+ "Node was deleted but visit returned new node!");
+
DEBUG(std::cerr << "\nReplacing "; N->dump();
- std::cerr << "\nWith: "; RV.Val->dump();
+ std::cerr << "\nWith: "; RV.Val->dump(&DAG);
std::cerr << '\n');
std::vector<SDNode*> NowDead;
DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
case ISD::SETCC: return visitSETCC(N);
case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
+ case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
case ISD::TRUNCATE: return visitTRUNCATE(N);
case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
+ case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
case ISD::FADD: return visitFADD(N);
case ISD::FSUB: return visitFSUB(N);
case ISD::FMUL: return visitFMUL(N);
case ISD::FDIV: return visitFDIV(N);
case ISD::FREM: return visitFREM(N);
+ case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
case ISD::FNEG: return visitFNEG(N);
case ISD::FABS: return visitFABS(N);
case ISD::BRCOND: return visitBRCOND(N);
- case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
case ISD::BR_CC: return visitBR_CC(N);
- case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
case ISD::LOAD: return visitLOAD(N);
+ case ISD::EXTLOAD:
+ case ISD::SEXTLOAD:
+ case ISD::ZEXTLOAD: return visitXEXTLOAD(N);
case ISD::STORE: return visitSTORE(N);
+ case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
+ case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
+ case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
+ case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
+ case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
+ case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
+ case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
+ case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
+ case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
+ case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
+ case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
+ case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
+ case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
}
return SDOperand();
}
// If the token factor has two operands and one is the entry token, replace
// the token factor with the other operand.
if (N->getNumOperands() == 2) {
- if (N->getOperand(0).getOpcode() == ISD::EntryToken)
+ if (N->getOperand(0).getOpcode() == ISD::EntryToken ||
+ N->getOperand(0) == N->getOperand(1))
return N->getOperand(1);
if (N->getOperand(1).getOpcode() == ISD::EntryToken)
return N->getOperand(0);
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
SDOperand Op = N->getOperand(i);
if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
+ AddToWorkList(Op.Val); // Remove dead node.
Changed = true;
for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
Ops.push_back(Op.getOperand(j));
- } else {
+ } else if (i == 0 || N->getOperand(i) != N->getOperand(i-1)) {
Ops.push_back(Op);
+ } else {
+ // Deleted an operand that was the same as the last one.
+ Changed = true;
}
}
if (Changed)
// fold (A+(B-A)) -> B
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
return N1.getOperand(0);
- //
- if (SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand();
+
+ if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
+ return SDOperand(N, 0);
+
+ // fold (a+b) -> (a|b) iff a and b share no bits.
+ if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
+ uint64_t LHSZero, LHSOne;
+ uint64_t RHSZero, RHSOne;
+ uint64_t Mask = MVT::getIntVTBitMask(VT);
+ TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
+ if (LHSZero) {
+ TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
+
+ // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
+ // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
+ if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
+ (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
+ return DAG.getNode(ISD::OR, VT, N0, N1);
+ }
+ }
+
return SDOperand();
}
DAG.getConstant(Log2_64(-N1C->getSignExtended()),
TLI.getShiftAmountTy())));
}
+
+ // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
+ if (N1C && N0.getOpcode() == ISD::SHL &&
+ isa<ConstantSDNode>(N0.getOperand(1))) {
+ SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
+ AddToWorkList(C3.Val);
+ return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
+ }
+
+ // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
+ // use.
+ {
+ SDOperand Sh(0,0), Y(0,0);
+ // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
+ if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
+ N0.Val->hasOneUse()) {
+ Sh = N0; Y = N1;
+ } else if (N1.getOpcode() == ISD::SHL &&
+ isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
+ Sh = N1; Y = N0;
+ }
+ if (Sh.Val) {
+ SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
+ return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
+ }
+ }
+ // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
+ if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
+ isa<ConstantSDNode>(N0.getOperand(1))) {
+ return DAG.getNode(ISD::ADD, VT,
+ DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
+ DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
+ }
+
// reassociate mul
SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
if (RMUL.Val != 0)
SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
DAG.getConstant(MVT::getSizeInBits(VT)-1,
TLI.getShiftAmountTy()));
- WorkList.push_back(SGN.Val);
+ AddToWorkList(SGN.Val);
// Add (N0 < 0) ? abs2 - 1 : 0;
SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
TLI.getShiftAmountTy()));
SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
- WorkList.push_back(SRL.Val);
- WorkList.push_back(ADD.Val); // Divide by pow2
+ AddToWorkList(SRL.Val);
+ AddToWorkList(ADD.Val); // Divide by pow2
SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
DAG.getConstant(lg2, TLI.getShiftAmountTy()));
// If we're dividing by a positive value, we're done. Otherwise, we must
// negate the result.
if (pow2 > 0)
return SRA;
- WorkList.push_back(SRA.Val);
+ AddToWorkList(SRA.Val);
return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
}
// if integer divide is expensive and we satisfy the requirements, emit an
SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
DAG.getConstant(Log2_64(SHC->getValue()),
ADDVT));
- WorkList.push_back(Add.Val);
+ AddToWorkList(Add.Val);
return DAG.getNode(ISD::SRL, VT, N0, Add);
}
}
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
if (isPowerOf2_64(SHC->getValue())) {
SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
- WorkList.push_back(Add.Val);
+ AddToWorkList(Add.Val);
return DAG.getNode(ISD::AND, VT, N0, Add);
}
}
return SDOperand();
}
+/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
+/// two operands of the same opcode, try to simplify it.
+SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
+ SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
+ MVT::ValueType VT = N0.getValueType();
+ assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
+
+ // For each of OP in AND/OR/XOR:
+ // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
+ // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
+ // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
+ // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
+ if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
+ N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
+ N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
+ SDOperand ORNode = DAG.getNode(N->getOpcode(),
+ N0.getOperand(0).getValueType(),
+ N0.getOperand(0), N1.getOperand(0));
+ AddToWorkList(ORNode.Val);
+ return DAG.getNode(N0.getOpcode(), VT, ORNode);
+ }
+
+ // For each of OP in SHL/SRL/SRA/AND...
+ // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
+ // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
+ // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
+ if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
+ N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
+ N0.getOperand(1) == N1.getOperand(1)) {
+ SDOperand ORNode = DAG.getNode(N->getOpcode(),
+ N0.getOperand(0).getValueType(),
+ N0.getOperand(0), N1.getOperand(0));
+ AddToWorkList(ORNode.Val);
+ return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
+ }
+
+ return SDOperand();
+}
+
SDOperand DAGCombiner::visitAND(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
return N1;
// fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
- unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType());
+ unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
if (TLI.MaskedValueIsZero(N0.getOperand(0),
- ~N1C->getValue() & ((1ULL << InBits)-1))) {
+ ~N1C->getValue() & InMask)) {
+ SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
+ N0.getOperand(0));
+
+ // Replace uses of the AND with uses of the Zero extend node.
+ CombineTo(N, Zext);
+
// We actually want to replace all uses of the any_extend with the
// zero_extend, to avoid duplicating things. This will later cause this
// AND to be folded.
- CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
- N0.getOperand(0)));
- return SDOperand();
+ CombineTo(N0.Val, Zext);
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
}
// fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
// fold (X == 0) & (Y == 0) -> (X|Y == 0)
if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
- WorkList.push_back(ORNode.Val);
+ AddToWorkList(ORNode.Val);
return DAG.getSetCC(VT, ORNode, LR, Op1);
}
// fold (X == -1) & (Y == -1) -> (X&Y == -1)
if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
- WorkList.push_back(ANDNode.Val);
+ AddToWorkList(ANDNode.Val);
return DAG.getSetCC(VT, ANDNode, LR, Op1);
}
// fold (X > -1) & (Y > -1) -> (X|Y > -1)
if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
- WorkList.push_back(ORNode.Val);
+ AddToWorkList(ORNode.Val);
return DAG.getSetCC(VT, ORNode, LR, Op1);
}
}
return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
}
}
- // fold (and (zext x), (zext y)) -> (zext (and x, y))
- if (N0.getOpcode() == ISD::ZERO_EXTEND &&
- N1.getOpcode() == ISD::ZERO_EXTEND &&
- N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
- SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
- N0.getOperand(0), N1.getOperand(0));
- WorkList.push_back(ANDNode.Val);
- return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
- }
- // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
- if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
- (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
- (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
- N0.getOperand(1) == N1.getOperand(1)) {
- SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
- N0.getOperand(0), N1.getOperand(0));
- WorkList.push_back(ANDNode.Val);
- return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
+
+ // Simplify: and (op x...), (op y...) -> (op (and x, y))
+ if (N0.getOpcode() == N1.getOpcode()) {
+ SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
+ if (Tmp.Val) return Tmp;
}
+
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
// fold (and (sra)) -> (and (srl)) when possible.
- if (SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand();
+ if (!MVT::isVector(VT) &&
+ SimplifyDemandedBits(SDOperand(N, 0)))
+ return SDOperand(N, 0);
// fold (zext_inreg (extload x)) -> (zextload x)
if (N0.getOpcode() == ISD::EXTLOAD) {
MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
N0.getOperand(1), N0.getOperand(2),
EVT);
- WorkList.push_back(N);
+ AddToWorkList(N);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
- return SDOperand();
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
}
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
N0.getOperand(1), N0.getOperand(2),
EVT);
- WorkList.push_back(N);
+ AddToWorkList(N);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
- return SDOperand();
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
}
+
+ // fold (and (load x), 255) -> (zextload x, i8)
+ // fold (and (extload x, i16), 255) -> (zextload x, i8)
+ if (N1C &&
+ (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
+ N0.getOpcode() == ISD::ZEXTLOAD) &&
+ N0.hasOneUse()) {
+ MVT::ValueType EVT, LoadedVT;
+ if (N1C->getValue() == 255)
+ EVT = MVT::i8;
+ else if (N1C->getValue() == 65535)
+ EVT = MVT::i16;
+ else if (N1C->getValue() == ~0U)
+ EVT = MVT::i32;
+ else
+ EVT = MVT::Other;
+
+ LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
+ cast<VTSDNode>(N0.getOperand(3))->getVT();
+ if (EVT != MVT::Other && LoadedVT > EVT &&
+ (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
+ MVT::ValueType PtrType = N0.getOperand(1).getValueType();
+ // For big endian targets, we need to add an offset to the pointer to load
+ // the correct bytes. For little endian systems, we merely need to read
+ // fewer bytes from the same pointer.
+ unsigned PtrOff =
+ (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
+ SDOperand NewPtr = N0.getOperand(1);
+ if (!TLI.isLittleEndian())
+ NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
+ DAG.getConstant(PtrOff, PtrType));
+ AddToWorkList(NewPtr.Val);
+ SDOperand Load =
+ DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr,
+ N0.getOperand(2), EVT);
+ AddToWorkList(N);
+ CombineTo(N0.Val, Load, Load.getValue(1));
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ }
+ }
+
return SDOperand();
}
if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
(Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
- WorkList.push_back(ORNode.Val);
+ AddToWorkList(ORNode.Val);
return DAG.getSetCC(VT, ORNode, LR, Op1);
}
// fold (X != -1) | (Y != -1) -> (X&Y != -1)
if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
(Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
- WorkList.push_back(ANDNode.Val);
+ AddToWorkList(ANDNode.Val);
return DAG.getSetCC(VT, ANDNode, LR, Op1);
}
}
return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
}
}
- // fold (or (zext x), (zext y)) -> (zext (or x, y))
- if (N0.getOpcode() == ISD::ZERO_EXTEND &&
- N1.getOpcode() == ISD::ZERO_EXTEND &&
- N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
- SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
- N0.getOperand(0), N1.getOperand(0));
- WorkList.push_back(ORNode.Val);
- return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
- }
- // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y))
- if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
- (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
- (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
- N0.getOperand(1) == N1.getOperand(1)) {
- SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
- N0.getOperand(0), N1.getOperand(0));
- WorkList.push_back(ORNode.Val);
- return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
+
+ // Simplify: or (op x...), (op y...) -> (op (or x, y))
+ if (N0.getOpcode() == N1.getOpcode()) {
+ SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
+ if (Tmp.Val) return Tmp;
}
+
// canonicalize shl to left side in a shl/srl pair, to match rotate
if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
std::swap(N0, N1);
unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
- WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
+ AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
return DAG.getNode(NewOpcode, VT, LHS, RHS);
}
}
unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
- WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
+ AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
return DAG.getNode(NewOpcode, VT, LHS, RHS);
}
}
DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
}
// fold (xor x, x) -> 0
- if (N0 == N1)
- return DAG.getConstant(0, VT);
- // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
- if (N0.getOpcode() == ISD::ZERO_EXTEND &&
- N1.getOpcode() == ISD::ZERO_EXTEND &&
- N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
- SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
- N0.getOperand(0), N1.getOperand(0));
- WorkList.push_back(XORNode.Val);
- return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
+ if (N0 == N1) {
+ if (!MVT::isVector(VT)) {
+ return DAG.getConstant(0, VT);
+ } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
+ // Produce a vector of zeros.
+ SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
+ std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
+ return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
+ }
}
- // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y))
- if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
- (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
- (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
- N0.getOperand(1) == N1.getOperand(1)) {
- SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
- N0.getOperand(0), N1.getOperand(0));
- WorkList.push_back(XORNode.Val);
- return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
+
+ // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
+ if (N0.getOpcode() == N1.getOpcode()) {
+ SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
+ if (Tmp.Val) return Tmp;
}
+
+ // Simplify the expression using non-local knowledge.
+ if (!MVT::isVector(VT) &&
+ SimplifyDemandedBits(SDOperand(N, 0)))
+ return SDOperand(N, 0);
+
return SDOperand();
}
if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
return DAG.getConstant(0, VT);
if (SimplifyDemandedBits(SDOperand(N, 0)))
- return SDOperand();
+ return SDOperand(N, 0);
// fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SHL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
DAG.getConstant(~0ULL << N1C->getValue(), VT));
+ // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
+ if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
+ isa<ConstantSDNode>(N0.getOperand(1))) {
+ return DAG.getNode(ISD::ADD, VT,
+ DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
+ DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
+ }
return SDOperand();
}
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
DAG.getValueType(EVT));
}
+
+ // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
+ if (N1C && N0.getOpcode() == ISD::SRA) {
+ if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+ unsigned Sum = N1C->getValue() + C1->getValue();
+ if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
+ return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
+ DAG.getConstant(Sum, N1C->getValueType(0)));
+ }
+ }
+
+ // Simplify, based on bits shifted out of the LHS.
+ if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
+ return SDOperand(N, 0);
+
+
// If the sign bit is known to be zero, switch this to a SRL.
if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
return DAG.getNode(ISD::SRL, VT, N0, N1);
return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
DAG.getConstant(c1 + c2, N1.getValueType()));
}
+
+ // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
+ if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
+ // Shifting in all undef bits?
+ MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
+ if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
+ return DAG.getNode(ISD::UNDEF, VT);
+
+ SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
+ AddToWorkList(SmallShift.Val);
+ return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
+ }
+
+ // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
+ if (N1C && N0.getOpcode() == ISD::CTLZ &&
+ N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
+ uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
+ TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
+
+ // If any of the input bits are KnownOne, then the input couldn't be all
+ // zeros, thus the result of the srl will always be zero.
+ if (KnownOne) return DAG.getConstant(0, VT);
+
+ // If all of the bits input the to ctlz node are known to be zero, then
+ // the result of the ctlz is "32" and the result of the shift is one.
+ uint64_t UnknownBits = ~KnownZero & Mask;
+ if (UnknownBits == 0) return DAG.getConstant(1, VT);
+
+ // Otherwise, check to see if there is exactly one bit input to the ctlz.
+ if ((UnknownBits & (UnknownBits-1)) == 0) {
+ // Okay, we know that only that the single bit specified by UnknownBits
+ // could be set on input to the CTLZ node. If this bit is set, the SRL
+ // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
+ // to an SRL,XOR pair, which is likely to simplify more.
+ unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
+ SDOperand Op = N0.getOperand(0);
+ if (ShAmt) {
+ Op = DAG.getNode(ISD::SRL, VT, Op,
+ DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
+ AddToWorkList(Op.Val);
+ }
+ return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
+ }
+ }
+
return SDOperand();
}
SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
MVT::ValueType VT = N->getValueType(0);
// fold (ctlz c1) -> c2
- if (N0C)
+ if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::CTLZ, VT, N0);
return SDOperand();
}
SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
MVT::ValueType VT = N->getValueType(0);
// fold (cttz c1) -> c2
- if (N0C)
+ if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::CTTZ, VT, N0);
return SDOperand();
}
SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
MVT::ValueType VT = N->getValueType(0);
// fold (ctpop c1) -> c2
- if (N0C)
+ if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::CTPOP, VT, N0);
return SDOperand();
}
// FIXME: this should check for C type == X type, not i1?
if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
- WorkList.push_back(XORNode.Val);
+ AddToWorkList(XORNode.Val);
return DAG.getNode(ISD::AND, VT, XORNode, N2);
}
// fold select C, X, 1 -> ~C | X
if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
- WorkList.push_back(XORNode.Val);
+ AddToWorkList(XORNode.Val);
return DAG.getNode(ISD::OR, VT, XORNode, N1);
}
// fold select C, X, 0 -> C & X
// fold X ? Y : X --> X ? Y : 0 --> X & Y
if (MVT::i1 == VT && N0 == N2)
return DAG.getNode(ISD::AND, VT, N0, N1);
+
// If we can fold this based on the true/false value, do so.
if (SimplifySelectOps(N, N1, N2))
- return SDOperand();
+ return SDOperand(N, 0); // Don't revisit N.
+
// fold selects based on a setcc into other things, such as min/max/abs
if (N0.getOpcode() == ISD::SETCC)
// FIXME:
// Determine if the condition we're dealing with is constant
SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
- ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
+ //ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
// fold select_cc lhs, rhs, x, x, cc -> x
if (N2 == N3)
// If we can fold this based on the true/false value, do so.
if (SimplifySelectOps(N, N2, N3))
- return SDOperand();
+ return SDOperand(N, 0); // Don't revisit N.
// fold select_cc into other things, such as min/max/abs
return SimplifySelectCC(N0, N1, N2, N3, CC);
SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
MVT::ValueType VT = N->getValueType(0);
// fold (sext c1) -> c1
- if (N0C)
+ if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
+
// fold (sext (sext x)) -> (sext x)
- if (N0.getOpcode() == ISD::SIGN_EXTEND)
+ // fold (sext (aext x)) -> (sext x)
+ if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
+
// fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
(!AfterLegalize ||
TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
DAG.getValueType(N0.getValueType()));
+
// fold (sext (load x)) -> (sext (truncate (sextload x)))
if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
(!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
- return SDOperand();
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
// fold (sext (sextload x)) -> (sext (truncate (sextload x)))
// fold (sext ( extload x)) -> (sext (truncate (sextload x)))
if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
N0.hasOneUse()) {
- SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
- N0.getOperand(1), N0.getOperand(2),
- N0.getOperand(3));
+ MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2), EVT);
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
- return SDOperand();
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
return SDOperand();
SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
MVT::ValueType VT = N->getValueType(0);
// fold (zext c1) -> c1
- if (N0C)
+ if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
// fold (zext (zext x)) -> (zext x)
- if (N0.getOpcode() == ISD::ZERO_EXTEND)
+ // fold (zext (aext x)) -> (zext x)
+ if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
// fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
- return SDOperand();
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
// fold (zext (zextload x)) -> (zext (truncate (zextload x)))
// fold (zext ( extload x)) -> (zext (truncate (zextload x)))
if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
N0.hasOneUse()) {
- SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
- N0.getOperand(1), N0.getOperand(2),
- N0.getOperand(3));
+ MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2), EVT);
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
- return SDOperand();
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
return SDOperand();
}
+SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
+ SDOperand N0 = N->getOperand(0);
+ MVT::ValueType VT = N->getValueType(0);
+
+ // fold (aext c1) -> c1
+ if (isa<ConstantSDNode>(N0))
+ return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
+ // fold (aext (aext x)) -> (aext x)
+ // fold (aext (zext x)) -> (zext x)
+ // fold (aext (sext x)) -> (sext x)
+ if (N0.getOpcode() == ISD::ANY_EXTEND ||
+ N0.getOpcode() == ISD::ZERO_EXTEND ||
+ N0.getOpcode() == ISD::SIGN_EXTEND)
+ return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
+
+ // fold (aext (truncate x)) -> x iff x size == zext size.
+ if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT)
+ return N0.getOperand(0);
+ // fold (aext (load x)) -> (aext (truncate (extload x)))
+ if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
+ (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) {
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2),
+ N0.getValueType());
+ CombineTo(N, ExtLoad);
+ CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+ ExtLoad.getValue(1));
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ }
+
+ // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
+ // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
+ // fold (aext ( extload x)) -> (aext (truncate (extload x)))
+ if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD ||
+ N0.getOpcode() == ISD::SEXTLOAD) &&
+ N0.hasOneUse()) {
+ MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
+ SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2), EVT);
+ CombineTo(N, ExtLoad);
+ CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+ ExtLoad.getValue(1));
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ }
+ return SDOperand();
+}
+
+
SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
MVT::ValueType VT = N->getValueType(0);
MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
unsigned EVTBits = MVT::getSizeInBits(EVT);
// fold (sext_in_reg c1) -> c1
- if (N0C) {
- SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
- return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
- }
- // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
- cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
+ if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
+ return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
+
+ // If the input is already sign extended, just drop the extension.
+ if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
return N0;
- }
+
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
}
- // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
- if (N0.getOpcode() == ISD::AssertSext &&
- cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
- return N0;
- }
- // fold (sext_in_reg (sextload x)) -> (sextload x)
- if (N0.getOpcode() == ISD::SEXTLOAD &&
- cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
- return N0;
- }
- // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
- if (N0.getOpcode() == ISD::SETCC &&
- TLI.getSetCCResultContents() ==
- TargetLowering::ZeroOrNegativeOneSetCCResult)
- return N0;
+
// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
return DAG.getZeroExtendInReg(N0, EVT);
- // fold (sext_in_reg (srl x)) -> sra x
- if (N0.getOpcode() == ISD::SRL &&
- N0.getOperand(1).getOpcode() == ISD::Constant &&
- cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
- return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
- N0.getOperand(1));
+
+ // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
+ // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
+ // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
+ if (N0.getOpcode() == ISD::SRL) {
+ if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
+ if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
+ // We can turn this into an SRA iff the input to the SRL is already sign
+ // extended enough.
+ unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
+ if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
+ return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
+ }
}
+
// fold (sext_inreg (extload x)) -> (sextload x)
if (N0.getOpcode() == ISD::EXTLOAD &&
EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
EVT);
CombineTo(N, ExtLoad);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
- return SDOperand();
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
EVT);
CombineTo(N, ExtLoad);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
- return SDOperand();
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
return SDOperand();
}
SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
MVT::ValueType VT = N->getValueType(0);
// noop truncate
if (N0.getValueType() == N->getValueType(0))
return N0;
// fold (truncate c1) -> c1
- if (N0C)
+ if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::TRUNCATE, VT, N0);
// fold (truncate (truncate x)) -> (truncate x)
if (N0.getOpcode() == ISD::TRUNCATE)
return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
// fold (truncate (ext x)) -> (ext x) or (truncate x) or x
- if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
+ if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
+ N0.getOpcode() == ISD::ANY_EXTEND) {
if (N0.getValueType() < VT)
// if the source is smaller than the dest, we still need an extend
return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
DAG.getConstant(PtrOff, PtrType));
- WorkList.push_back(NewPtr.Val);
+ AddToWorkList(NewPtr.Val);
SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
- WorkList.push_back(N);
+ AddToWorkList(N);
CombineTo(N0.Val, Load, Load.getValue(1));
- return SDOperand();
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
return SDOperand();
}
if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
-
+
// fold (conv (load x)) -> (load (conv*)x)
// FIXME: These xforms need to know that the resultant load doesn't need a
// higher alignment than the original!
if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
N0.getOperand(2));
- WorkList.push_back(N);
+ AddToWorkList(N);
CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
Load.getValue(1));
return Load;
return SDOperand();
}
+SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
+ SDOperand N0 = N->getOperand(0);
+ MVT::ValueType VT = N->getValueType(0);
+
+ // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
+ // First check to see if this is all constant.
+ if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
+ VT == MVT::Vector) {
+ bool isSimple = true;
+ for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
+ if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
+ N0.getOperand(i).getOpcode() != ISD::Constant &&
+ N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
+ isSimple = false;
+ break;
+ }
+
+ MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
+ if (isSimple && !MVT::isVector(DestEltVT)) {
+ return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
+ }
+ }
+
+ return SDOperand();
+}
+
+/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
+/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
+/// destination element value type.
+SDOperand DAGCombiner::
+ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
+ MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
+
+ // If this is already the right type, we're done.
+ if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
+
+ unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
+ unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
+
+ // If this is a conversion of N elements of one type to N elements of another
+ // type, convert each element. This handles FP<->INT cases.
+ if (SrcBitSize == DstBitSize) {
+ std::vector<SDOperand> Ops;
+ for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
+ Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
+ AddToWorkList(Ops.back().Val);
+ }
+ Ops.push_back(*(BV->op_end()-2)); // Add num elements.
+ Ops.push_back(DAG.getValueType(DstEltVT));
+ return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ }
+
+ // Otherwise, we're growing or shrinking the elements. To avoid having to
+ // handle annoying details of growing/shrinking FP values, we convert them to
+ // int first.
+ if (MVT::isFloatingPoint(SrcEltVT)) {
+ // Convert the input float vector to a int vector where the elements are the
+ // same sizes.
+ assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
+ MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
+ BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
+ SrcEltVT = IntVT;
+ }
+
+ // Now we know the input is an integer vector. If the output is a FP type,
+ // convert to integer first, then to FP of the right size.
+ if (MVT::isFloatingPoint(DstEltVT)) {
+ assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
+ MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
+ SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
+
+ // Next, convert to FP elements of the same size.
+ return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
+ }
+
+ // Okay, we know the src/dst types are both integers of differing types.
+ // Handling growing first.
+ assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
+ if (SrcBitSize < DstBitSize) {
+ unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
+
+ std::vector<SDOperand> Ops;
+ for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
+ i += NumInputsPerOutput) {
+ bool isLE = TLI.isLittleEndian();
+ uint64_t NewBits = 0;
+ bool EltIsUndef = true;
+ for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
+ // Shift the previously computed bits over.
+ NewBits <<= SrcBitSize;
+ SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
+ if (Op.getOpcode() == ISD::UNDEF) continue;
+ EltIsUndef = false;
+
+ NewBits |= cast<ConstantSDNode>(Op)->getValue();
+ }
+
+ if (EltIsUndef)
+ Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
+ else
+ Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
+ }
+
+ Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
+ Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
+ return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ }
+
+ // Finally, this must be the case where we are shrinking elements: each input
+ // turns into multiple outputs.
+ unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
+ std::vector<SDOperand> Ops;
+ for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
+ if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
+ for (unsigned j = 0; j != NumOutputsPerInput; ++j)
+ Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
+ continue;
+ }
+ uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
+
+ for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
+ unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
+ OpVal >>= DstBitSize;
+ Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
+ }
+
+ // For big endian targets, swap the order of the pieces of each element.
+ if (!TLI.isLittleEndian())
+ std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
+ }
+ Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
+ Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
+ return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+}
+
+
+
SDOperand DAGCombiner::visitFADD(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
return SDOperand();
}
+SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
+ SDOperand N0 = N->getOperand(0);
+ SDOperand N1 = N->getOperand(1);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
+ MVT::ValueType VT = N->getValueType(0);
+
+ if (N0CFP && N1CFP) // Constant fold
+ return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
+
+ if (N1CFP) {
+ // copysign(x, c1) -> fabs(x) iff ispos(c1)
+ // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
+ union {
+ double d;
+ int64_t i;
+ } u;
+ u.d = N1CFP->getValue();
+ if (u.i >= 0)
+ return DAG.getNode(ISD::FABS, VT, N0);
+ else
+ return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
+ }
+
+ // copysign(fabs(x), y) -> copysign(x, y)
+ // copysign(fneg(x), y) -> copysign(x, y)
+ // copysign(copysign(x,z), y) -> copysign(x, y)
+ if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
+ N0.getOpcode() == ISD::FCOPYSIGN)
+ return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
+
+ // copysign(x, abs(y)) -> abs(x)
+ if (N1.getOpcode() == ISD::FABS)
+ return DAG.getNode(ISD::FABS, VT, N0);
+
+ // copysign(x, copysign(y,z)) -> copysign(x, z)
+ if (N1.getOpcode() == ISD::FCOPYSIGN)
+ return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
+
+ // copysign(x, fp_extend(y)) -> copysign(x, y)
+ // copysign(x, fp_round(y)) -> copysign(x, y)
+ if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
+ return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
+
+ return SDOperand();
+}
+
+
SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
SDOperand N0 = N->getOperand(0);
// fold (fp_round c1fp) -> c1fp
if (N0CFP)
return DAG.getNode(ISD::FP_ROUND, VT, N0);
+
+ // fold (fp_round (fp_extend x)) -> x
+ if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
+ return N0.getOperand(0);
+
+ // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
+ if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
+ SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
+ AddToWorkList(Tmp.Val);
+ return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
+ }
+
return SDOperand();
}
// fold (fp_extend c1fp) -> c1fp
if (N0CFP)
return DAG.getNode(ISD::FP_EXTEND, VT, N0);
+
+ // fold (fpext (load x)) -> (fpext (fpround (extload x)))
+ if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
+ (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) {
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2),
+ N0.getValueType());
+ CombineTo(N, ExtLoad);
+ CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
+ ExtLoad.getValue(1));
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ }
+
+
return SDOperand();
}
if (N0CFP)
return DAG.getNode(ISD::FNEG, VT, N0);
// fold (fneg (sub x, y)) -> (sub y, x)
- if (N->getOperand(0).getOpcode() == ISD::SUB)
- return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0));
+ if (N0.getOpcode() == ISD::SUB)
+ return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
// fold (fneg (fneg x)) -> x
- if (N->getOperand(0).getOpcode() == ISD::FNEG)
- return N->getOperand(0).getOperand(0);
+ if (N0.getOpcode() == ISD::FNEG)
+ return N0.getOperand(0);
return SDOperand();
}
if (N0CFP)
return DAG.getNode(ISD::FABS, VT, N0);
// fold (fabs (fabs x)) -> (fabs x)
- if (N->getOperand(0).getOpcode() == ISD::FABS)
+ if (N0.getOpcode() == ISD::FABS)
return N->getOperand(0);
// fold (fabs (fneg x)) -> (fabs x)
- if (N->getOperand(0).getOpcode() == ISD::FNEG)
- return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0));
+ // fold (fabs (fcopysign x, y)) -> (fabs x)
+ if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
+ return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
+
return SDOperand();
}
return SDOperand();
}
-SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
- SDOperand Chain = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
- SDOperand N2 = N->getOperand(2);
- SDOperand N3 = N->getOperand(3);
- ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-
- // unconditional branch to true mbb
- if (N1C && N1C->getValue() == 1)
- return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
- // unconditional branch to false mbb
- if (N1C && N1C->isNullValue())
- return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
- // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if
- // BRTWOWAY_CC is legal on the target.
- if (N1.getOpcode() == ISD::SETCC &&
- TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
- std::vector<SDOperand> Ops;
- Ops.push_back(Chain);
- Ops.push_back(N1.getOperand(2));
- Ops.push_back(N1.getOperand(0));
- Ops.push_back(N1.getOperand(1));
- Ops.push_back(N2);
- Ops.push_back(N3);
- return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
- }
- return SDOperand();
-}
-
// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
//
SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
return SDOperand();
}
-SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
- SDOperand Chain = N->getOperand(0);
- SDOperand CCN = N->getOperand(1);
- SDOperand LHS = N->getOperand(2);
- SDOperand RHS = N->getOperand(3);
- SDOperand N4 = N->getOperand(4);
- SDOperand N5 = N->getOperand(5);
-
- SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
- cast<CondCodeSDNode>(CCN)->get(), false);
- ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
-
- // fold select_cc lhs, rhs, x, x, cc -> x
- if (N4 == N5)
- return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
- // fold select_cc true, x, y -> x
- if (SCCC && SCCC->getValue())
- return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
- // fold select_cc false, x, y -> y
- if (SCCC && SCCC->isNullValue())
- return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
- // fold to a simpler setcc
- if (SCC.Val && SCC.getOpcode() == ISD::SETCC) {
- std::vector<SDOperand> Ops;
- Ops.push_back(Chain);
- Ops.push_back(SCC.getOperand(2));
- Ops.push_back(SCC.getOperand(0));
- Ops.push_back(SCC.getOperand(1));
- Ops.push_back(N4);
- Ops.push_back(N5);
- return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
- }
- return SDOperand();
-}
-
SDOperand DAGCombiner::visitLOAD(SDNode *N) {
SDOperand Chain = N->getOperand(0);
SDOperand Ptr = N->getOperand(1);
SDOperand SrcValue = N->getOperand(2);
+
+ // If there are no uses of the loaded value, change uses of the chain value
+ // into uses of the chain input (i.e. delete the dead load).
+ if (N->hasNUsesOfValue(0, 0))
+ return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
// If this load is directly stored, replace the load value with the stored
// value.
return SDOperand();
}
+/// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD.
+SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) {
+ SDOperand Chain = N->getOperand(0);
+ SDOperand Ptr = N->getOperand(1);
+ SDOperand SrcValue = N->getOperand(2);
+ SDOperand EVT = N->getOperand(3);
+
+ // If there are no uses of the loaded value, change uses of the chain value
+ // into uses of the chain input (i.e. delete the dead load).
+ if (N->hasNUsesOfValue(0, 0))
+ return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
+
+ return SDOperand();
+}
+
SDOperand DAGCombiner::visitSTORE(SDNode *N) {
SDOperand Chain = N->getOperand(0);
SDOperand Value = N->getOperand(1);
return SDOperand();
}
+SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
+ SDOperand InVec = N->getOperand(0);
+ SDOperand InVal = N->getOperand(1);
+ SDOperand EltNo = N->getOperand(2);
+
+ // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
+ // vector with the inserted element.
+ if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
+ unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
+ std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+ if (Elt < Ops.size())
+ Ops[Elt] = InVal;
+ return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops);
+ }
+
+ return SDOperand();
+}
+
+SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
+ SDOperand InVec = N->getOperand(0);
+ SDOperand InVal = N->getOperand(1);
+ SDOperand EltNo = N->getOperand(2);
+ SDOperand NumElts = N->getOperand(3);
+ SDOperand EltType = N->getOperand(4);
+
+ // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
+ // vector with the inserted element.
+ if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
+ unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
+ std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+ if (Elt < Ops.size()-2)
+ Ops[Elt] = InVal;
+ return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops);
+ }
+
+ return SDOperand();
+}
+
+SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
+ unsigned NumInScalars = N->getNumOperands()-2;
+ SDOperand NumElts = N->getOperand(NumInScalars);
+ SDOperand EltType = N->getOperand(NumInScalars+1);
+
+ // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
+ // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
+ // two distinct vectors, turn this into a shuffle node.
+ SDOperand VecIn1, VecIn2;
+ for (unsigned i = 0; i != NumInScalars; ++i) {
+ // Ignore undef inputs.
+ if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
+
+ // If this input is something other than a VEXTRACT_VECTOR_ELT with a
+ // constant index, bail out.
+ if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
+ !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
+ VecIn1 = VecIn2 = SDOperand(0, 0);
+ break;
+ }
+
+ // If the input vector type disagrees with the result of the vbuild_vector,
+ // we can't make a shuffle.
+ SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
+ if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
+ *(ExtractedFromVec.Val->op_end()-1) != EltType) {
+ VecIn1 = VecIn2 = SDOperand(0, 0);
+ break;
+ }
+
+ // Otherwise, remember this. We allow up to two distinct input vectors.
+ if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
+ continue;
+
+ if (VecIn1.Val == 0) {
+ VecIn1 = ExtractedFromVec;
+ } else if (VecIn2.Val == 0) {
+ VecIn2 = ExtractedFromVec;
+ } else {
+ // Too many inputs.
+ VecIn1 = VecIn2 = SDOperand(0, 0);
+ break;
+ }
+ }
+
+ // If everything is good, we can make a shuffle operation.
+ if (VecIn1.Val) {
+ std::vector<SDOperand> BuildVecIndices;
+ for (unsigned i = 0; i != NumInScalars; ++i) {
+ if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
+ BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
+ continue;
+ }
+
+ SDOperand Extract = N->getOperand(i);
+
+ // If extracting from the first vector, just use the index directly.
+ if (Extract.getOperand(0) == VecIn1) {
+ BuildVecIndices.push_back(Extract.getOperand(1));
+ continue;
+ }
+
+ // Otherwise, use InIdx + VecSize
+ unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
+ BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
+ }
+
+ // Add count and size info.
+ BuildVecIndices.push_back(NumElts);
+ BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
+
+ // Return the new VVECTOR_SHUFFLE node.
+ std::vector<SDOperand> Ops;
+ Ops.push_back(VecIn1);
+ if (VecIn2.Val) {
+ Ops.push_back(VecIn2);
+ } else {
+ // Use an undef vbuild_vector as input for the second operand.
+ std::vector<SDOperand> UnOps(NumInScalars,
+ DAG.getNode(ISD::UNDEF,
+ cast<VTSDNode>(EltType)->getVT()));
+ UnOps.push_back(NumElts);
+ UnOps.push_back(EltType);
+ Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
+ AddToWorkList(Ops.back().Val);
+ }
+ Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
+ Ops.push_back(NumElts);
+ Ops.push_back(EltType);
+ return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
+ }
+
+ return SDOperand();
+}
+
+SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
+ SDOperand ShufMask = N->getOperand(2);
+ unsigned NumElts = ShufMask.getNumOperands();
+
+ // If the shuffle mask is an identity operation on the LHS, return the LHS.
+ bool isIdentity = true;
+ for (unsigned i = 0; i != NumElts; ++i) {
+ if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+ cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
+ isIdentity = false;
+ break;
+ }
+ }
+ if (isIdentity) return N->getOperand(0);
+
+ // If the shuffle mask is an identity operation on the RHS, return the RHS.
+ isIdentity = true;
+ for (unsigned i = 0; i != NumElts; ++i) {
+ if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+ cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
+ isIdentity = false;
+ break;
+ }
+ }
+ if (isIdentity) return N->getOperand(1);
+
+ // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
+ // needed at all.
+ bool isUnary = true;
+ bool isSplat = true;
+ int VecNum = -1;
+ unsigned BaseIdx = 0;
+ for (unsigned i = 0; i != NumElts; ++i)
+ if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
+ unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
+ int V = (Idx < NumElts) ? 0 : 1;
+ if (VecNum == -1) {
+ VecNum = V;
+ BaseIdx = Idx;
+ } else {
+ if (BaseIdx != Idx)
+ isSplat = false;
+ if (VecNum != V) {
+ isUnary = false;
+ break;
+ }
+ }
+ }
+
+ SDOperand N0 = N->getOperand(0);
+ SDOperand N1 = N->getOperand(1);
+ // Normalize unary shuffle so the RHS is undef.
+ if (isUnary && VecNum == 1)
+ std::swap(N0, N1);
+
+ // If it is a splat, check if the argument vector is a build_vector with
+ // all scalar elements the same.
+ if (isSplat) {
+ SDNode *V = N0.Val;
+ if (V->getOpcode() == ISD::BIT_CONVERT)
+ V = V->getOperand(0).Val;
+ if (V->getOpcode() == ISD::BUILD_VECTOR) {
+ unsigned NumElems = V->getNumOperands()-2;
+ if (NumElems > BaseIdx) {
+ SDOperand Base;
+ bool AllSame = true;
+ for (unsigned i = 0; i != NumElems; ++i) {
+ if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
+ Base = V->getOperand(i);
+ break;
+ }
+ }
+ // Splat of <u, u, u, u>, return <u, u, u, u>
+ if (!Base.Val)
+ return N0;
+ for (unsigned i = 0; i != NumElems; ++i) {
+ if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
+ V->getOperand(i) != Base) {
+ AllSame = false;
+ break;
+ }
+ }
+ // Splat of <x, x, x, x>, return <x, x, x, x>
+ if (AllSame)
+ return N0;
+ }
+ }
+ }
+
+ // If it is a unary or the LHS and the RHS are the same node, turn the RHS
+ // into an undef.
+ if (isUnary || N0 == N1) {
+ if (N0.getOpcode() == ISD::UNDEF)
+ return DAG.getNode(ISD::UNDEF, N->getValueType(0));
+ // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
+ // first operand.
+ std::vector<SDOperand> MappedOps;
+ for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
+ if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
+ cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
+ MappedOps.push_back(ShufMask.getOperand(i));
+ } else {
+ unsigned NewIdx =
+ cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
+ MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
+ }
+ }
+ ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
+ MappedOps);
+ AddToWorkList(ShufMask.Val);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
+ N0,
+ DAG.getNode(ISD::UNDEF, N->getValueType(0)),
+ ShufMask);
+ }
+
+ return SDOperand();
+}
+
+SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
+ SDOperand ShufMask = N->getOperand(2);
+ unsigned NumElts = ShufMask.getNumOperands()-2;
+
+ // If the shuffle mask is an identity operation on the LHS, return the LHS.
+ bool isIdentity = true;
+ for (unsigned i = 0; i != NumElts; ++i) {
+ if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+ cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
+ isIdentity = false;
+ break;
+ }
+ }
+ if (isIdentity) return N->getOperand(0);
+
+ // If the shuffle mask is an identity operation on the RHS, return the RHS.
+ isIdentity = true;
+ for (unsigned i = 0; i != NumElts; ++i) {
+ if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
+ cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
+ isIdentity = false;
+ break;
+ }
+ }
+ if (isIdentity) return N->getOperand(1);
+
+ // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
+ // needed at all.
+ bool isUnary = true;
+ bool isSplat = true;
+ int VecNum = -1;
+ unsigned BaseIdx = 0;
+ for (unsigned i = 0; i != NumElts; ++i)
+ if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
+ unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
+ int V = (Idx < NumElts) ? 0 : 1;
+ if (VecNum == -1) {
+ VecNum = V;
+ BaseIdx = Idx;
+ } else {
+ if (BaseIdx != Idx)
+ isSplat = false;
+ if (VecNum != V) {
+ isUnary = false;
+ break;
+ }
+ }
+ }
+
+ SDOperand N0 = N->getOperand(0);
+ SDOperand N1 = N->getOperand(1);
+ // Normalize unary shuffle so the RHS is undef.
+ if (isUnary && VecNum == 1)
+ std::swap(N0, N1);
+
+ // If it is a splat, check if the argument vector is a build_vector with
+ // all scalar elements the same.
+ if (isSplat) {
+ SDNode *V = N0.Val;
+ if (V->getOpcode() == ISD::VBIT_CONVERT)
+ V = V->getOperand(0).Val;
+ if (V->getOpcode() == ISD::VBUILD_VECTOR) {
+ unsigned NumElems = V->getNumOperands()-2;
+ if (NumElems > BaseIdx) {
+ SDOperand Base;
+ bool AllSame = true;
+ for (unsigned i = 0; i != NumElems; ++i) {
+ if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
+ Base = V->getOperand(i);
+ break;
+ }
+ }
+ // Splat of <u, u, u, u>, return <u, u, u, u>
+ if (!Base.Val)
+ return N0;
+ for (unsigned i = 0; i != NumElems; ++i) {
+ if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
+ V->getOperand(i) != Base) {
+ AllSame = false;
+ break;
+ }
+ }
+ // Splat of <x, x, x, x>, return <x, x, x, x>
+ if (AllSame)
+ return N0;
+ }
+ }
+ }
+
+ // If it is a unary or the LHS and the RHS are the same node, turn the RHS
+ // into an undef.
+ if (isUnary || N0 == N1) {
+ // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
+ // first operand.
+ std::vector<SDOperand> MappedOps;
+ for (unsigned i = 0; i != NumElts; ++i) {
+ if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
+ cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
+ MappedOps.push_back(ShufMask.getOperand(i));
+ } else {
+ unsigned NewIdx =
+ cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
+ MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
+ }
+ }
+ // Add the type/#elts values.
+ MappedOps.push_back(ShufMask.getOperand(NumElts));
+ MappedOps.push_back(ShufMask.getOperand(NumElts+1));
+
+ ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
+ MappedOps);
+ AddToWorkList(ShufMask.Val);
+
+ // Build the undef vector.
+ SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
+ for (unsigned i = 0; i != NumElts; ++i)
+ MappedOps[i] = UDVal;
+ MappedOps[NumElts ] = *(N0.Val->op_end()-2);
+ MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
+ UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps);
+
+ return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
+ N0, UDVal, ShufMask,
+ MappedOps[NumElts], MappedOps[NumElts+1]);
+ }
+
+ return SDOperand();
+}
+
+/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
+/// a VAND to a vector_shuffle with the destination vector and a zero vector.
+/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
+/// vector_shuffle V, Zero, <0, 4, 2, 4>
+SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
+ SDOperand LHS = N->getOperand(0);
+ SDOperand RHS = N->getOperand(1);
+ if (N->getOpcode() == ISD::VAND) {
+ SDOperand DstVecSize = *(LHS.Val->op_end()-2);
+ SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
+ if (RHS.getOpcode() == ISD::VBIT_CONVERT)
+ RHS = RHS.getOperand(0);
+ if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
+ std::vector<SDOperand> IdxOps;
+ unsigned NumOps = RHS.getNumOperands();
+ unsigned NumElts = NumOps-2;
+ MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
+ for (unsigned i = 0; i != NumElts; ++i) {
+ SDOperand Elt = RHS.getOperand(i);
+ if (!isa<ConstantSDNode>(Elt))
+ return SDOperand();
+ else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
+ IdxOps.push_back(DAG.getConstant(i, EVT));
+ else if (cast<ConstantSDNode>(Elt)->isNullValue())
+ IdxOps.push_back(DAG.getConstant(NumElts, EVT));
+ else
+ return SDOperand();
+ }
+
+ // Let's see if the target supports this vector_shuffle.
+ if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
+ return SDOperand();
+
+ // Return the new VVECTOR_SHUFFLE node.
+ SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
+ SDOperand EVTNode = DAG.getValueType(EVT);
+ std::vector<SDOperand> Ops;
+ LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, EVTNode);
+ Ops.push_back(LHS);
+ AddToWorkList(LHS.Val);
+ std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
+ ZeroOps.push_back(NumEltsNode);
+ ZeroOps.push_back(EVTNode);
+ Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps));
+ IdxOps.push_back(NumEltsNode);
+ IdxOps.push_back(EVTNode);
+ Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps));
+ Ops.push_back(NumEltsNode);
+ Ops.push_back(EVTNode);
+ SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
+ if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
+ Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
+ DstVecSize, DstVecEVT);
+ }
+ return Result;
+ }
+ }
+ return SDOperand();
+}
+
+/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
+/// the scalar operation of the vop if it is operating on an integer vector
+/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
+SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
+ ISD::NodeType FPOp) {
+ MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
+ ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
+ SDOperand LHS = N->getOperand(0);
+ SDOperand RHS = N->getOperand(1);
+ SDOperand Shuffle = XformToShuffleWithZero(N);
+ if (Shuffle.Val) return Shuffle;
+
+ // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
+ // this operation.
+ if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
+ RHS.getOpcode() == ISD::VBUILD_VECTOR) {
+ std::vector<SDOperand> Ops;
+ for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
+ SDOperand LHSOp = LHS.getOperand(i);
+ SDOperand RHSOp = RHS.getOperand(i);
+ // If these two elements can't be folded, bail out.
+ if ((LHSOp.getOpcode() != ISD::UNDEF &&
+ LHSOp.getOpcode() != ISD::Constant &&
+ LHSOp.getOpcode() != ISD::ConstantFP) ||
+ (RHSOp.getOpcode() != ISD::UNDEF &&
+ RHSOp.getOpcode() != ISD::Constant &&
+ RHSOp.getOpcode() != ISD::ConstantFP))
+ break;
+ // Can't fold divide by zero.
+ if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
+ if ((RHSOp.getOpcode() == ISD::Constant &&
+ cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
+ (RHSOp.getOpcode() == ISD::ConstantFP &&
+ !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
+ break;
+ }
+ Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
+ AddToWorkList(Ops.back().Val);
+ assert((Ops.back().getOpcode() == ISD::UNDEF ||
+ Ops.back().getOpcode() == ISD::Constant ||
+ Ops.back().getOpcode() == ISD::ConstantFP) &&
+ "Scalar binop didn't fold!");
+ }
+
+ if (Ops.size() == LHS.getNumOperands()-2) {
+ Ops.push_back(*(LHS.Val->op_end()-2));
+ Ops.push_back(*(LHS.Val->op_end()-1));
+ return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ }
+ }
+
+ return SDOperand();
+}
+
SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
SCC.getOperand(0), SCC.getOperand(1),
SCC.getOperand(4));
- WorkList.push_back(SETCC.Val);
+ AddToWorkList(SETCC.Val);
return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
SCC.getOperand(3), SETCC);
}
/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
/// are the two values being selected between, see if we can simplify the
-/// select.
+/// select. Callers of this should assume that TheSelect is deleted if this
+/// returns true. As such, they should return the appropriate thing (e.g. the
+/// node) back to the top-level of the DAG combiner loop to avoid it being
+/// looked at.
///
bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
SDOperand RHS) {
ISD::CondCode CC) {
MVT::ValueType VT = N2.getValueType();
- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
+ //ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
- WorkList.push_back(Shift.Val);
+ AddToWorkList(Shift.Val);
if (XType > AType) {
Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
- WorkList.push_back(Shift.Val);
+ AddToWorkList(Shift.Val);
}
return DAG.getNode(ISD::AND, AType, Shift, N2);
}
SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
DAG.getConstant(MVT::getSizeInBits(XType)-1,
TLI.getShiftAmountTy()));
- WorkList.push_back(Shift.Val);
+ AddToWorkList(Shift.Val);
if (XType > AType) {
Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
- WorkList.push_back(Shift.Val);
+ AddToWorkList(Shift.Val);
}
return DAG.getNode(ISD::AND, AType, Shift, N2);
}
SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
}
- WorkList.push_back(SCC.Val);
- WorkList.push_back(Temp.Val);
+ AddToWorkList(SCC.Val);
+ AddToWorkList(Temp.Val);
// shl setcc result by log2 n2c
return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
DAG.getConstant(Log2_64(N2C->getValue()),
DAG.getConstant(MVT::getSizeInBits(XType)-1,
TLI.getShiftAmountTy()));
SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
- WorkList.push_back(Shift.Val);
- WorkList.push_back(Add.Val);
+ AddToWorkList(Shift.Val);
+ AddToWorkList(Add.Val);
return DAG.getNode(ISD::XOR, XType, Add, Shift);
}
}
ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
DAG.getConstant(Imm, Op0Ty));
}
- WorkList.push_back(ZextOp.Val);
+ AddToWorkList(ZextOp.Val);
// Otherwise, make this a use of a zext.
return DAG.getSetCC(VT, ZextOp,
DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
// Perform the xform if C1 is a single bit.
if ((C1 & (C1-1)) == 0) {
return DAG.getNode(ISD::SRL, VT, N0,
- DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
+ DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
}
}
}
SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
N1,
DAG.getConstant(1,TLI.getShiftAmountTy()));
- WorkList.push_back(SH.Val);
+ AddToWorkList(SH.Val);
return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
}
}
// X == (Z-X) --> X<<1 == Z
SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
DAG.getConstant(1,TLI.getShiftAmountTy()));
- WorkList.push_back(SH.Val);
+ AddToWorkList(SH.Val);
return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
}
}
case ISD::SETEQ: // X == Y -> (X^Y)^1
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
- WorkList.push_back(Temp.Val);
+ AddToWorkList(Temp.Val);
break;
case ISD::SETNE: // X != Y --> (X^Y)
N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
- WorkList.push_back(Temp.Val);
+ AddToWorkList(Temp.Val);
break;
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
- WorkList.push_back(Temp.Val);
+ AddToWorkList(Temp.Val);
break;
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
- WorkList.push_back(Temp.Val);
+ AddToWorkList(Temp.Val);
break;
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
break;
}
if (VT != MVT::i1) {
- WorkList.push_back(N0.Val);
+ AddToWorkList(N0.Val);
// FIXME: If running after legalize, we probably can't do this.
N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
}
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
- MVT::ValueType VT = N->getValueType(0);
-
- // Check to see if we can do this.
- if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
- return SDOperand(); // BuildSDIV only operates on i32 or i64
- if (!TLI.isOperationLegal(ISD::MULHS, VT))
- return SDOperand(); // Make sure the target supports MULHS.
-
- int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
- ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
-
- // Multiply the numerator (operand 0) by the magic value
- SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
- DAG.getConstant(magics.m, VT));
- // If d > 0 and m < 0, add the numerator
- if (d > 0 && magics.m < 0) {
- Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
- WorkList.push_back(Q.Val);
- }
- // If d < 0 and m > 0, subtract the numerator.
- if (d < 0 && magics.m > 0) {
- Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
- WorkList.push_back(Q.Val);
- }
- // Shift right algebraic if shift value is nonzero
- if (magics.s > 0) {
- Q = DAG.getNode(ISD::SRA, VT, Q,
- DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
- WorkList.push_back(Q.Val);
- }
- // Extract the sign bit and add it to the quotient
- SDOperand T =
- DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
- TLI.getShiftAmountTy()));
- WorkList.push_back(T.Val);
- return DAG.getNode(ISD::ADD, VT, Q, T);
+ std::vector<SDNode*> Built;
+ SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
+
+ for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
+ ii != ee; ++ii)
+ AddToWorkList(*ii);
+ return S;
}
/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
- MVT::ValueType VT = N->getValueType(0);
-
- // Check to see if we can do this.
- if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
- return SDOperand(); // BuildUDIV only operates on i32 or i64
- if (!TLI.isOperationLegal(ISD::MULHU, VT))
- return SDOperand(); // Make sure the target supports MULHU.
-
- uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
- mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
-
- // Multiply the numerator (operand 0) by the magic value
- SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
- DAG.getConstant(magics.m, VT));
- WorkList.push_back(Q.Val);
-
- if (magics.a == 0) {
- return DAG.getNode(ISD::SRL, VT, Q,
- DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
- } else {
- SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
- WorkList.push_back(NPQ.Val);
- NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
- DAG.getConstant(1, TLI.getShiftAmountTy()));
- WorkList.push_back(NPQ.Val);
- NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
- WorkList.push_back(NPQ.Val);
- return DAG.getNode(ISD::SRL, VT, NPQ,
- DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
- }
+ std::vector<SDNode*> Built;
+ SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
+
+ for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
+ ii != ee; ++ii)
+ AddToWorkList(*ii);
+ return S;
}
// SelectionDAG::Combine - This is the entry point for the file.
projects / oota-llvm.git / blobdiff