#include "llvm/ADT/STLExtras.h"
using namespace llvm;
-void RegScavenger::init(MachineBasicBlock *mbb) {
- if (mbb)
- MBB = mbb;
-
- const MachineFunction &MF = *MBB->getParent();
+void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
+ const MachineFunction &MF = *mbb->getParent();
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo *RegInfo = TM.getRegisterInfo();
+ TII = TM.getInstrInfo();
+ RegInfo = TM.getRegisterInfo();
+
+ assert((NumPhysRegs == 0 || NumPhysRegs == RegInfo->getNumRegs()) &&
+ "Target changed?");
+
+ if (!MBB) {
+ NumPhysRegs = RegInfo->getNumRegs();
+ RegsAvailable.resize(NumPhysRegs);
+
+ // Create reserved registers bitvector.
+ ReservedRegs = RegInfo->getReservedRegs(MF);
+
+ // Create callee-saved registers bitvector.
+ CalleeSavedRegs.resize(NumPhysRegs);
+ const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
+ if (CSRegs != NULL)
+ for (unsigned i = 0; CSRegs[i]; ++i)
+ CalleeSavedRegs.set(CSRegs[i]);
+ }
- MBBI = MBB->begin();
- NumPhysRegs = RegInfo->getNumRegs();
- RegStates.resize(NumPhysRegs, true);
+ MBB = mbb;
+ ScavengedReg = 0;
+ ScavengedRC = NULL;
- // Create reserved registers bitvector.
- ReservedRegs = RegInfo->getReservedRegs(MF);
- RegStates ^= ReservedRegs;
+ // All registers started out unused.
+ RegsAvailable.set();
- // Create callee-saved registers bitvector.
- CalleeSavedRegs.resize(NumPhysRegs);
- const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
- if (CSRegs != NULL)
- for (unsigned i = 0; CSRegs[i]; ++i)
- CalleeSavedRegs.set(CSRegs[i]);
+ // Reserved registers are always used.
+ RegsAvailable ^= ReservedRegs;
// Live-in registers are in use.
if (!MBB->livein_empty())
E = MBB->livein_end(); I != E; ++I)
setUsed(*I);
- Initialized = true;
+ Tracking = false;
+}
+
+void RegScavenger::restoreScavengedReg() {
+ if (!ScavengedReg)
+ return;
+
+ RegInfo->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
+ ScavengingFrameIndex, ScavengedRC);
+ MachineBasicBlock::iterator II = prior(MBBI);
+ RegInfo->eliminateFrameIndex(II, 0, this);
+ setUsed(ScavengedReg);
+ ScavengedReg = 0;
+ ScavengedRC = NULL;
}
void RegScavenger::forward() {
- assert(MBBI != MBB->end() && "Already at the end of the basic block!");
// Move ptr forward.
- if (!Initialized)
- init();
- else
+ if (!Tracking) {
+ MBBI = MBB->begin();
+ Tracking = true;
+ } else {
+ assert(MBBI != MBB->end() && "Already at the end of the basic block!");
MBBI = next(MBBI);
+ }
MachineInstr *MI = MBBI;
+
+ // Reaching a terminator instruction. Restore a scavenged register (which
+ // must be life out.
+ if (TII->isTerminatorInstr(MI->getOpcode()))
+ restoreScavengedReg();
+
// Process uses first.
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse())
+ if (!MO.isRegister() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
continue;
- assert(isUsed(Reg));
+ if (!isUsed(Reg)) {
+ // Register has been scavenged. Restore it!
+ if (Reg != ScavengedReg)
+ assert(false && "Using an undefined register!");
+ else
+ restoreScavengedReg();
+ }
if (MO.isKill() && !isReserved(Reg))
ChangedRegs.set(Reg);
}
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isDef())
+ if (!MO.isRegister() || !MO.isDef())
continue;
unsigned Reg = MO.getReg();
+ // If it's dead upon def, then it is now free.
+ if (MO.isDead()) {
+ setUnused(Reg);
+ continue;
+ }
// Skip two-address destination operand.
if (TID->findTiedToSrcOperand(i) != -1) {
- assert(isUsed(Reg));
+ assert(isUsed(Reg) && "Using an undefined register!");
continue;
}
- assert(isUnused(Reg) || isReserved(Reg));
- if (!MO.isDead())
- setUsed(Reg);
+ assert((isUnused(Reg) || isReserved(Reg)) &&
+ "Re-defining a live register!");
+ setUsed(Reg);
}
}
void RegScavenger::backward() {
+ assert(Tracking && "Not tracking states!");
assert(MBBI != MBB->begin() && "Already at start of basic block!");
// Move ptr backward.
MBBI = prior(MBBI);
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isDef())
+ if (!MO.isRegister() || !MO.isDef())
continue;
// Skip two-address destination operand.
if (TID->findTiedToSrcOperand(i) != -1)
BitVector ChangedRegs(NumPhysRegs);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse())
+ if (!MO.isRegister() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
setUsed(ChangedRegs);
}
+void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
+ if (includeReserved)
+ used = ~RegsAvailable;
+ else
+ used = ~RegsAvailable & ~ReservedRegs;
+}
+
/// CreateRegClassMask - Set the bits that represent the registers in the
/// TargetRegisterClass.
static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
Mask.set(*I);
}
+unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
+ const BitVector &Candidates) const {
+ // Mask off the registers which are not in the TargetRegisterClass.
+ BitVector RegsAvailableCopy(NumPhysRegs, false);
+ CreateRegClassMask(RegClass, RegsAvailableCopy);
+ RegsAvailableCopy &= RegsAvailable;
+
+ // Restrict the search to candidates.
+ RegsAvailableCopy &= Candidates;
+
+ // Returns the first unused (bit is set) register, or 0 is none is found.
+ int Reg = RegsAvailableCopy.find_first();
+ return (Reg == -1) ? 0 : Reg;
+}
+
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
bool ExCalleeSaved) const {
// Mask off the registers which are not in the TargetRegisterClass.
- BitVector RegStatesCopy(NumPhysRegs, false);
- CreateRegClassMask(RegClass, RegStatesCopy);
- RegStatesCopy &= RegStates;
+ BitVector RegsAvailableCopy(NumPhysRegs, false);
+ CreateRegClassMask(RegClass, RegsAvailableCopy);
+ RegsAvailableCopy &= RegsAvailable;
// If looking for a non-callee-saved register, mask off all the callee-saved
// registers.
if (ExCalleeSaved)
- RegStatesCopy &= ~CalleeSavedRegs;
+ RegsAvailableCopy &= ~CalleeSavedRegs;
// Returns the first unused (bit is set) register, or 0 is none is found.
- int Reg = RegStatesCopy.find_first();
+ int Reg = RegsAvailableCopy.find_first();
return (Reg == -1) ? 0 : Reg;
}
-void RegScavenger::clear() {
- if (MBB) {
- MBBI = MBB->end();
- MBB = NULL;
+/// calcDistanceToUse - Calculate the distance to the first use of the
+/// specified register.
+static unsigned calcDistanceToUse(MachineBasicBlock *MBB,
+ MachineBasicBlock::iterator I, unsigned Reg) {
+ unsigned Dist = 0;
+ I = next(I);
+ while (I != MBB->end()) {
+ Dist++;
+ if (I->findRegisterUseOperandIdx(Reg) != -1)
+ return Dist;
+ I = next(I);
}
+ return Dist + 1;
+}
+
+unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
+ MachineBasicBlock::iterator I,
+ int SPAdj) {
+ assert(ScavengingFrameIndex >= 0 &&
+ "Cannot scavenge a register without an emergency spill slot!");
+
+ // Mask off the registers which are not in the TargetRegisterClass.
+ BitVector Candidates(NumPhysRegs, false);
+ CreateRegClassMask(RC, Candidates);
+ Candidates ^= ReservedRegs; // Do not include reserved registers.
+
+ // Exclude all the registers being used by the instruction.
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = I->getOperand(i);
+ if (MO.isRegister())
+ Candidates.reset(MO.getReg());
+ }
+
+ // Find the register whose use is furtherest aaway.
+ unsigned SReg = 0;
+ unsigned MaxDist = 0;
+ int Reg = Candidates.find_first();
+ while (Reg != -1) {
+ unsigned Dist = calcDistanceToUse(MBB, I, Reg);
+ if (Dist >= MaxDist) {
+ MaxDist = Dist;
+ SReg = Reg;
+ }
+ Reg = Candidates.find_next(Reg);
+ }
+
+ if (ScavengedReg != 0) {
+ // First restore previously scavenged register.
+ RegInfo->loadRegFromStackSlot(*MBB, I, ScavengedReg,
+ ScavengingFrameIndex, ScavengedRC);
+ MachineBasicBlock::iterator II = prior(I);
+ RegInfo->eliminateFrameIndex(II, SPAdj, this);
+ }
+
+ RegInfo->storeRegToStackSlot(*MBB, I, SReg, ScavengingFrameIndex, RC);
+ MachineBasicBlock::iterator II = prior(I);
+ RegInfo->eliminateFrameIndex(II, SPAdj, this);
+ ScavengedReg = SReg;
+ ScavengedRC = RC;
- NumPhysRegs = 0;
- Initialized = false;
- RegStates.clear();
+ return SReg;
}
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