-//===-- RegAllocSimple.cpp - A simple generic register allocator --- ------===//
+//===-- RegAllocSimple.cpp - A simple generic register allocator ----------===//
//
-// This file implements a simple register allocator. *Very* simple.
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a simple register allocator. *Very* simple: It immediate
+// spills every value right after it is computed, and it reloads all used
+// operands from the spill area to temporary registers before each instruction.
+// It does not keep values in registers across instructions.
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/MachineFunction.h"
+#define DEBUG_TYPE "regalloc"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/RegAllocRegistry.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "Support/Statistic.h"
-#include <iostream>
-#include <set>
-
-#if 0
-/// PhysRegClassMap - Construct a mapping of physical register numbers to their
-/// register classes.
-///
-/// NOTE: This class will eventually be pulled out to somewhere shared.
-///
-class PhysRegClassMap {
- std::map<unsigned, const TargetRegisterClass*> PhysReg2RegClassMap;
-public:
- PhysRegClassMap(const MRegisterInfo *RI) {
- for (MRegisterInfo::const_iterator I = RI->regclass_begin(),
- E = RI->regclass_end(); I != E; ++I)
- for (unsigned i=0; i < (*I)->getNumRegs(); ++i)
- PhysReg2RegClassMap[(*I)->getRegister(i)] = *I;
- }
-
- const TargetRegisterClass *operator[](unsigned Reg) {
- assert(PhysReg2RegClassMap[Reg] && "Register is not a known physreg!");
- return PhysReg2RegClassMap[Reg];
- }
-
- const TargetRegisterClass *get(unsigned Reg) { return operator[](Reg); }
-};
-#endif
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/STLExtras.h"
+using namespace llvm;
+STATISTIC(NumStores, "Number of stores added");
+STATISTIC(NumLoads , "Number of loads added");
namespace {
- Statistic<> NumSpilled ("ra-simple", "Number of registers spilled");
- Statistic<> NumReloaded("ra-simple", "Number of registers reloaded");
+ static RegisterRegAlloc
+ simpleRegAlloc("simple", " simple register allocator",
+ createSimpleRegisterAllocator);
- class RegAllocSimple : public FunctionPass {
- TargetMachine &TM;
+ class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
+ public:
+ static char ID;
+ RegAllocSimple() : MachineFunctionPass((intptr_t)&ID) {}
+ private:
MachineFunction *MF;
+ const TargetMachine *TM;
const MRegisterInfo *RegInfo;
- unsigned NumBytesAllocated;
-
- // Maps SSA Regs => offsets on the stack where these values are stored
- std::map<unsigned, unsigned> VirtReg2OffsetMap;
- // RegsUsed - Keep track of what registers are currently in use.
- std::set<unsigned> RegsUsed;
+ // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
+ // these values are spilled
+ std::map<unsigned, int> StackSlotForVirtReg;
+
+ // RegsUsed - Keep track of what registers are currently in use. This is a
+ // bitset.
+ std::vector<bool> RegsUsed;
// RegClassIdx - Maps RegClass => which index we can take a register
// from. Since this is a simple register allocator, when we need a register
std::map<const TargetRegisterClass*, unsigned> RegClassIdx;
public:
-
- RegAllocSimple(TargetMachine &tm)
- : TM(tm), RegInfo(tm.getRegisterInfo()) {
- RegsUsed.insert(RegInfo->getFramePointer());
- RegsUsed.insert(RegInfo->getStackPointer());
-
- cleanupAfterFunction();
- }
-
- bool runOnFunction(Function &Fn) {
- return runOnMachineFunction(MachineFunction::get(&Fn));
- }
-
virtual const char *getPassName() const {
return "Simple Register Allocator";
}
- private:
/// runOnMachineFunction - Register allocate the whole function
bool runOnMachineFunction(MachineFunction &Fn);
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequiredID(PHIEliminationID); // Eliminate PHI nodes
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+ private:
/// AllocateBasicBlock - Register allocate the specified basic block.
void AllocateBasicBlock(MachineBasicBlock &MBB);
- /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
- /// in predecessor basic blocks.
- void EliminatePHINodes(MachineBasicBlock &MBB);
-
-
/// getStackSpaceFor - This returns the offset of the specified virtual
- /// register on the stack, allocating space if neccesary.
- unsigned getStackSpaceFor(unsigned VirtReg,
- const TargetRegisterClass *regClass);
+ /// register on the stack, allocating space if necessary.
+ int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
/// Given a virtual register, return a compatible physical register that is
/// currently unused.
///
unsigned getFreeReg(unsigned virtualReg);
- /// Returns all `borrowed' registers back to the free pool
- void clearAllRegs() {
- RegClassIdx.clear();
- }
-
- /// Invalidates any references, real or implicit, to physical registers
- ///
- void invalidatePhysRegs(const MachineInstr *MI) {
- unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = TM.getInstrInfo().get(Opcode);
- const unsigned *regs = Desc.ImplicitUses;
- while (*regs)
- RegsUsed.insert(*regs++);
-
- regs = Desc.ImplicitDefs;
- while (*regs)
- RegsUsed.insert(*regs++);
- }
-
- void cleanupAfterFunction() {
- VirtReg2OffsetMap.clear();
- NumBytesAllocated = 4; // FIXME: This is X86 specific
- }
-
/// Moves value from memory into that register
- MachineBasicBlock::iterator
- moveUseToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned VirtReg, unsigned &PhysReg);
+ unsigned reloadVirtReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I, unsigned VirtReg);
/// Saves reg value on the stack (maps virtual register to stack value)
- MachineBasicBlock::iterator
- saveVirtRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned VirtReg, unsigned PhysReg);
+ void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned VirtReg, unsigned PhysReg);
};
-
+ char RegAllocSimple::ID = 0;
}
/// getStackSpaceFor - This allocates space for the specified virtual
/// register to be held on the stack.
-unsigned RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
- const TargetRegisterClass *regClass) {
+int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
+ const TargetRegisterClass *RC) {
// Find the location VirtReg would belong...
- std::map<unsigned, unsigned>::iterator I =
- VirtReg2OffsetMap.lower_bound(VirtReg);
+ std::map<unsigned, int>::iterator I =
+ StackSlotForVirtReg.lower_bound(VirtReg);
- if (I != VirtReg2OffsetMap.end() && I->first == VirtReg)
+ if (I != StackSlotForVirtReg.end() && I->first == VirtReg)
return I->second; // Already has space allocated?
- unsigned RegSize = regClass->getDataSize();
+ // Allocate a new stack object for this spill location...
+ int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
+ RC->getAlignment());
- // Align NumBytesAllocated. We should be using TargetData alignment stuff
- // to determine this, but we don't know the LLVM type associated with the
- // virtual register. Instead, just align to a multiple of the size for now.
- NumBytesAllocated += RegSize-1;
- NumBytesAllocated = NumBytesAllocated/RegSize*RegSize;
-
// Assign the slot...
- VirtReg2OffsetMap.insert(I, std::make_pair(VirtReg, NumBytesAllocated));
-
- // Reserve the space!
- NumBytesAllocated += RegSize;
- return NumBytesAllocated-RegSize;
+ StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
+
+ return FrameIdx;
}
unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
- const TargetRegisterClass* regClass = MF->getRegClass(virtualReg);
-
- unsigned regIdx = RegClassIdx[regClass]++;
- assert(regIdx < regClass->getNumRegs() && "Not enough registers!");
- unsigned physReg = regClass->getRegister(regIdx);
-
- if (RegsUsed.find(physReg) == RegsUsed.end())
- return physReg;
- else
- return getFreeReg(virtualReg);
+ const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg);
+ TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
+ TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
+
+ while (1) {
+ unsigned regIdx = RegClassIdx[RC]++;
+ assert(RI+regIdx != RE && "Not enough registers!");
+ unsigned PhysReg = *(RI+regIdx);
+
+ if (!RegsUsed[PhysReg]) {
+ MF->setPhysRegUsed(PhysReg);
+ return PhysReg;
+ }
+ }
}
-MachineBasicBlock::iterator
-RegAllocSimple::moveUseToReg (MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- unsigned VirtReg, unsigned &PhysReg)
-{
- const TargetRegisterClass* regClass = MF->getRegClass(VirtReg);
- unsigned stackOffset = getStackSpaceFor(VirtReg, regClass);
- PhysReg = getFreeReg(VirtReg);
+unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ unsigned VirtReg) {
+ const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
+ int FrameIdx = getStackSpaceFor(VirtReg, RC);
+ unsigned PhysReg = getFreeReg(VirtReg);
// Add move instruction(s)
- ++NumReloaded;
- return RegInfo->loadRegOffset2Reg(MBB, I, PhysReg,
- RegInfo->getFramePointer(),
- -stackOffset, regClass->getDataSize());
+ ++NumLoads;
+ RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+ return PhysReg;
}
-MachineBasicBlock::iterator
-RegAllocSimple::saveVirtRegToStack (MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- unsigned VirtReg, unsigned PhysReg)
-{
- const TargetRegisterClass* regClass = MF->getRegClass(VirtReg);
- unsigned stackOffset = getStackSpaceFor(VirtReg, regClass);
+void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ unsigned VirtReg, unsigned PhysReg) {
+ const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
+ int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
- ++NumSpilled;
- return RegInfo->storeReg2RegOffset(MBB, I, PhysReg,
- RegInfo->getFramePointer(),
- -stackOffset, regClass->getDataSize());
-}
-
-
-/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
-/// predecessor basic blocks.
-///
-void RegAllocSimple::EliminatePHINodes(MachineBasicBlock &MBB) {
- const MachineInstrInfo &MII = TM.getInstrInfo();
-
- while (MBB.front()->getOpcode() == MachineInstrInfo::PHI) {
- MachineInstr *MI = MBB.front();
- // Unlink the PHI node from the basic block... but don't delete the PHI yet
- MBB.erase(MBB.begin());
-
- DEBUG(std::cerr << "num ops: " << MI->getNumOperands() << "\n");
- assert(MI->getOperand(0).isVirtualRegister() &&
- "PHI node doesn't write virt reg?");
-
- unsigned virtualReg = MI->getOperand(0).getAllocatedRegNum();
-
- for (int i = MI->getNumOperands() - 1; i >= 2; i-=2) {
- MachineOperand &opVal = MI->getOperand(i-1);
-
- // Get the MachineBasicBlock equivalent of the BasicBlock that is the
- // source path the phi
- MachineBasicBlock &opBlock = *MI->getOperand(i).getMachineBasicBlock();
-
- // Check to make sure we haven't already emitted the copy for this block.
- // This can happen because PHI nodes may have multiple entries for the
- // same basic block. It doesn't matter which entry we use though, because
- // all incoming values are guaranteed to be the same for a particular bb.
- //
- // Note that this is N^2 in the number of phi node entries, but since the
- // # of entries is tiny, this is not a problem.
- //
- bool HaveNotEmitted = true;
- for (int op = MI->getNumOperands() - 1; op != i; op -= 2)
- if (&opBlock == MI->getOperand(op).getMachineBasicBlock()) {
- HaveNotEmitted = false;
- break;
- }
-
- if (HaveNotEmitted) {
- MachineBasicBlock::iterator opI = opBlock.end();
- MachineInstr *opMI = *--opI;
-
- // must backtrack over ALL the branches in the previous block
- while (MII.isBranch(opMI->getOpcode()) && opI != opBlock.begin())
- opMI = *--opI;
-
- // move back to the first branch instruction so new instructions
- // are inserted right in front of it and not in front of a non-branch
- if (!MII.isBranch(opMI->getOpcode()))
- ++opI;
-
- unsigned dataSize = MF->getRegClass(virtualReg)->getDataSize();
-
- // Retrieve the constant value from this op, move it to target
- // register of the phi
- if (opVal.isImmediate()) {
- opI = RegInfo->moveImm2Reg(opBlock, opI, virtualReg,
- (unsigned) opVal.getImmedValue(),
- dataSize);
- } else {
- opI = RegInfo->moveReg2Reg(opBlock, opI, virtualReg,
- opVal.getAllocatedRegNum(), dataSize);
- }
- }
- }
-
- // really delete the PHI instruction now!
- delete MI;
- }
+ ++NumStores;
+ RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
}
void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction
- for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
+ for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
- MachineInstr *MI = *I;
-
- // a preliminary pass that will invalidate any registers that
- // are used by the instruction (including implicit uses)
- invalidatePhysRegs(MI);
-
- // Loop over uses, move from memory into registers
+ RegsUsed.resize(RegInfo->getNumRegs());
+
+ // This is a preliminary pass that will invalidate any registers that are
+ // used by the instruction (including implicit uses).
+ unsigned Opcode = MI->getOpcode();
+ const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
+ const unsigned *Regs;
+ if (Desc.ImplicitUses) {
+ for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
+ RegsUsed[*Regs] = true;
+ }
+
+ if (Desc.ImplicitDefs) {
+ for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
+ RegsUsed[*Regs] = true;
+ MF->setPhysRegUsed(*Regs);
+ }
+ }
+
+ // Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &op = MI->getOperand(i);
-
- if (op.isVirtualRegister()) {
- unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
- DEBUG(std::cerr << "op: " << op << "\n");
- DEBUG(std::cerr << "\t inst[" << i << "]: ";
- MI->print(std::cerr, TM));
-
+
+ if (op.isRegister() && op.getReg() &&
+ MRegisterInfo::isVirtualRegister(op.getReg())) {
+ unsigned virtualReg = (unsigned) op.getReg();
+ DOUT << "op: " << op << "\n";
+ DOUT << "\t inst[" << i << "]: ";
+ DEBUG(MI->print(*cerr.stream(), TM));
+
// make sure the same virtual register maps to the same physical
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
- if (op.opIsDef()) {
- if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
- // must be same register number as the first operand
- // This maps a = b + c into b += c, and saves b into a's spot
- assert(MI->getOperand(1).isRegister() &&
- MI->getOperand(1).getAllocatedRegNum() &&
- MI->getOperand(1).opIsUse() &&
+ if (op.isDef()) {
+ int TiedOp = MI->getInstrDescriptor()->findTiedToSrcOperand(i);
+ if (TiedOp == -1) {
+ physReg = getFreeReg(virtualReg);
+ } else {
+ // must be same register number as the source operand that is
+ // tied to. This maps a = b + c into b = b + c, and saves b into
+ // a's spot.
+ assert(MI->getOperand(TiedOp).isRegister() &&
+ MI->getOperand(TiedOp).getReg() &&
+ MI->getOperand(TiedOp).isUse() &&
"Two address instruction invalid!");
- physReg = MI->getOperand(1).getAllocatedRegNum();
- } else {
- physReg = getFreeReg(virtualReg);
+ physReg = MI->getOperand(TiedOp).getReg();
}
- I = --saveVirtRegToStack(MBB, ++I, virtualReg, physReg);
+ spillVirtReg(MBB, next(MI), virtualReg, physReg);
} else {
- I = moveUseToReg(MBB, I, virtualReg, physReg);
+ physReg = reloadVirtReg(MBB, MI, virtualReg);
+ Virt2PhysRegMap[virtualReg] = physReg;
}
- Virt2PhysRegMap[virtualReg] = physReg;
}
- MI->SetMachineOperandReg(i, physReg);
- DEBUG(std::cerr << "virt: " << virtualReg <<
- ", phys: " << op.getAllocatedRegNum() << "\n");
+ MI->getOperand(i).setReg(physReg);
+ DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
}
}
- clearAllRegs();
+ RegClassIdx.clear();
+ RegsUsed.clear();
}
}
+
/// runOnMachineFunction - Register allocate the whole function
///
bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
- DEBUG(std::cerr << "Machine Function " << "\n");
+ DOUT << "Machine Function\n";
MF = &Fn;
-
- // First pass: eliminate PHI instructions by inserting copies into predecessor
- // blocks.
- for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
- MBB != MBBe; ++MBB)
- EliminatePHINodes(*MBB);
+ TM = &MF->getTarget();
+ RegInfo = TM->getRegisterInfo();
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB)
AllocateBasicBlock(*MBB);
- // Add prologue to the function...
- RegInfo->emitPrologue(Fn, NumBytesAllocated);
-
- const MachineInstrInfo &MII = TM.getInstrInfo();
-
- // Add epilogue to restore the callee-save registers in each exiting block
- for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
- MBB != MBBe; ++MBB) {
- // If last instruction is a return instruction, add an epilogue
- if (MII.isReturn(MBB->back()->getOpcode()))
- RegInfo->emitEpilogue(*MBB, NumBytesAllocated);
- }
-
- cleanupAfterFunction();
+ StackSlotForVirtReg.clear();
return true;
}
-Pass *createSimpleX86RegisterAllocator(TargetMachine &TM) {
- return new RegAllocSimple(TM);
+FunctionPass *llvm::createSimpleRegisterAllocator() {
+ return new RegAllocSimple();
}
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