// pressure, it can caused fewer GPRs to be held in the queue.
static cl::opt<unsigned>
NumRecentlyUsedRegs("linearscan-skip-count",
- cl::desc("Number of registers for linearscan to remember to skip."),
+ cl::desc("Number of registers for linearscan to remember"
+ "to skip."),
cl::init(0),
cl::Hidden);
struct RALinScan : public MachineFunctionPass {
static char ID;
- RALinScan() : MachineFunctionPass(&ID) {
+ RALinScan() : MachineFunctionPass(ID) {
// Initialize the queue to record recently-used registers.
if (NumRecentlyUsedRegs > 0)
RecentRegs.resize(NumRecentlyUsedRegs, 0);
BitVector allocatableRegs_;
LiveIntervals* li_;
LiveStacks* ls_;
- const MachineLoopInfo *loopInfo;
+ MachineLoopInfo *loopInfo;
/// handled_ - Intervals are added to the handled_ set in the order of their
/// start value. This is uses for backtracking.
SmallVector<LiveInterval*, 8> &SpillIntervals);
/// attemptTrivialCoalescing - If a simple interval is defined by a copy,
- /// try allocate the definition the same register as the source register
- /// if the register is not defined during live time of the interval. This
- /// eliminate a copy. This is used to coalesce copies which were not
+ /// try to allocate the definition to the same register as the source,
+ /// if the register is not defined during the life time of the interval.
+ /// This eliminates a copy, and is used to coalesce copies which were not
/// coalesced away before allocation either due to dest and src being in
/// different register classes or because the coalescer was overly
/// conservative.
bool Error = false;
for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
if (regUse_[i] != 0) {
- errs() << tri_->getName(i) << " is still in use!\n";
+ dbgs() << tri_->getName(i) << " is still in use!\n";
Error = true;
}
}
SmallVector<unsigned, 256> &inactiveCounts,
bool SkipDGRegs);
- /// assignVirt2StackSlot - assigns this virtual register to a
- /// stack slot. returns the stack slot
- int assignVirt2StackSlot(unsigned virtReg);
-
void ComputeRelatedRegClasses();
template <typename ItTy>
void printIntervals(const char* const str, ItTy i, ItTy e) const {
DEBUG({
if (str)
- errs() << str << " intervals:\n";
+ dbgs() << str << " intervals:\n";
for (; i != e; ++i) {
- errs() << "\t" << *i->first << " -> ";
+ dbgs() << "\t" << *i->first << " -> ";
unsigned reg = i->first->reg;
if (TargetRegisterInfo::isVirtualRegister(reg))
reg = vrm_->getPhys(reg);
- errs() << tri_->getName(reg) << '\n';
+ dbgs() << tri_->getName(reg) << '\n';
}
});
}
char RALinScan::ID = 0;
}
-static RegisterPass<RALinScan>
-X("linearscan-regalloc", "Linear Scan Register Allocator");
+INITIALIZE_PASS(RALinScan, "linearscan-regalloc",
+ "Linear Scan Register Allocator", false, false);
void RALinScan::ComputeRelatedRegClasses() {
// First pass, add all reg classes to the union, and determine at least one
unsigned CandReg;
{
MachineInstr *CopyMI;
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (vni->def != SlotIndex() && vni->isDefAccurate() &&
- (CopyMI = li_->getInstructionFromIndex(vni->def)) &&
- tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
+ (CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
// Defined by a copy, try to extend SrcReg forward
- CandReg = SrcReg;
+ CandReg = CopyMI->getOperand(1).getReg();
else if (TrivCoalesceEnds &&
- (CopyMI =
- li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
- tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
- cur.reg == SrcReg)
+ (CopyMI = li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
+ CopyMI->isCopy() && cur.reg == CopyMI->getOperand(1).getReg())
// Only used by a copy, try to extend DstReg backwards
- CandReg = DstReg;
+ CandReg = CopyMI->getOperand(0).getReg();
else
return Reg;
}
return Reg;
// Try to coalesce.
- DEBUG(errs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
+ DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
<< '\n');
vrm_->clearVirt(cur.reg);
vrm_->assignVirt2Phys(cur.reg, CandReg);
vrm_ = &getAnalysis<VirtRegMap>();
if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
- spiller_.reset(createSpiller(mf_, li_, loopInfo, vrm_));
+ spiller_.reset(createSpiller(*this, *mf_, *vrm_));
initIntervalSets();
void RALinScan::linearScan() {
// linear scan algorithm
DEBUG({
- errs() << "********** LINEAR SCAN **********\n"
+ dbgs() << "********** LINEAR SCAN **********\n"
<< "********** Function: "
<< mf_->getFunction()->getName() << '\n';
printIntervals("fixed", fixed_.begin(), fixed_.end());
LiveInterval* cur = unhandled_.top();
unhandled_.pop();
++NumIters;
- DEBUG(errs() << "\n*** CURRENT ***: " << *cur << '\n');
+ DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
assert(!cur->empty() && "Empty interval in unhandled set.");
while (!active_.empty()) {
IntervalPtr &IP = active_.back();
unsigned reg = IP.first->reg;
- DEBUG(errs() << "\tinterval " << *IP.first << " expired\n");
+ DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
DEBUG({
for (IntervalPtrs::reverse_iterator
i = inactive_.rbegin(); i != inactive_.rend(); ++i)
- errs() << "\tinterval " << *i->first << " expired\n";
+ dbgs() << "\tinterval " << *i->first << " expired\n";
});
inactive_.clear();
}
}
- DEBUG(errs() << *vrm_);
+ DEBUG(dbgs() << *vrm_);
// Look for physical registers that end up not being allocated even though
// register allocator had to spill other registers in its register class.
/// to the inactive list.
void RALinScan::processActiveIntervals(SlotIndex CurPoint)
{
- DEBUG(errs() << "\tprocessing active intervals:\n");
+ DEBUG(dbgs() << "\tprocessing active intervals:\n");
for (unsigned i = 0, e = active_.size(); i != e; ++i) {
LiveInterval *Interval = active_[i].first;
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
if (IntervalPos == Interval->end()) { // Remove expired intervals.
- DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
+ DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
} else if (IntervalPos->start > CurPoint) {
// Move inactive intervals to inactive list.
- DEBUG(errs() << "\t\tinterval " << *Interval << " inactive\n");
+ DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
/// ones to the active list.
void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
{
- DEBUG(errs() << "\tprocessing inactive intervals:\n");
+ DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
LiveInterval *Interval = inactive_[i].first;
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
if (IntervalPos == Interval->end()) { // remove expired intervals.
- DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
+ DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
// Pop off the end of the list.
inactive_[i] = inactive_.back();
--i; --e;
} else if (IntervalPos->start <= CurPoint) {
// move re-activated intervals in active list
- DEBUG(errs() << "\t\tinterval " << *Interval << " active\n");
+ DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
static
float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
MachineRegisterInfo *mri_,
- const MachineLoopInfo *loopInfo) {
+ MachineLoopInfo *loopInfo) {
float Conflicts = 0;
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
E = mri_->reg_end(); I != E; ++I) {
MachineInstr *MI = &*I;
if (cur->liveAt(li_->getInstructionIndex(MI))) {
unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
- Conflicts += powf(10.0f, (float)loopDepth);
+ Conflicts += std::pow(10.0f, (float)loopDepth);
}
}
return Conflicts;
SmallVector<LiveInterval*, 8> SLIs[3];
DEBUG({
- errs() << "\tConsidering " << NumCands << " candidates: ";
+ dbgs() << "\tConsidering " << NumCands << " candidates: ";
for (unsigned i = 0; i != NumCands; ++i)
- errs() << tri_->getName(Candidates[i].first) << " ";
- errs() << "\n";
+ dbgs() << tri_->getName(Candidates[i].first) << " ";
+ dbgs() << "\n";
});
// Calculate the number of conflicts of each candidate.
/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
/// spill.
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
- DEBUG(errs() << "\tallocating current interval: ");
+ DEBUG(dbgs() << "\tallocating current interval: ");
// This is an implicitly defined live interval, just assign any register.
const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
unsigned physReg = vrm_->getRegAllocPref(cur->reg);
if (!physReg)
physReg = *RC->allocation_order_begin(*mf_);
- DEBUG(errs() << tri_->getName(physReg) << '\n');
+ DEBUG(dbgs() << tri_->getName(physReg) << '\n');
// Note the register is not really in use.
vrm_->assignVirt2Phys(cur->reg, physReg);
return;
if ((vni->def != SlotIndex()) && !vni->isUnused() &&
vni->isDefAccurate()) {
MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (CopyMI &&
- tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
+ if (CopyMI && CopyMI->isCopy()) {
+ unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();
+ unsigned SrcReg = CopyMI->getOperand(1).getReg();
+ unsigned SrcSubReg = CopyMI->getOperand(1).getSubReg();
unsigned Reg = 0;
if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
Reg = SrcReg;
// the free physical register and add this interval to the active
// list.
if (physReg) {
- DEBUG(errs() << tri_->getName(physReg) << '\n');
+ DEBUG(dbgs() << tri_->getName(physReg) << '\n');
vrm_->assignVirt2Phys(cur->reg, physReg);
addRegUse(physReg);
active_.push_back(std::make_pair(cur, cur->begin()));
}
return;
}
- DEBUG(errs() << "no free registers\n");
+ DEBUG(dbgs() << "no free registers\n");
// Compile the spill weights into an array that is better for scanning.
std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
}
- DEBUG(errs() << "\tassigning stack slot at interval "<< *cur << ":\n");
+ DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
// Find a register to spill.
float minWeight = HUGE_VALF;
assignRegOrStackSlotAtInterval(cur);
} else {
assert(false && "Ran out of registers during register allocation!");
- llvm_report_error("Ran out of registers during register allocation!");
+ report_fatal_error("Ran out of registers during register allocation!");
}
return;
}
}
DEBUG({
- errs() << "\t\tregister(s) with min weight(s): ";
+ dbgs() << "\t\tregister(s) with min weight(s): ";
for (unsigned i = 0; i != LastCandidate; ++i)
- errs() << tri_->getName(RegsWeights[i].first)
+ dbgs() << tri_->getName(RegsWeights[i].first)
<< " (" << RegsWeights[i].second << ")\n";
});
// add any added intervals back to unhandled, and restart
// linearscan.
if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
- DEBUG(errs() << "\t\t\tspilling(c): " << *cur << '\n');
+ DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
SmallVector<LiveInterval*, 8> spillIs;
std::vector<LiveInterval*> added;
-
- added = spiller_->spill(cur, spillIs);
+ spiller_->spill(cur, added, spillIs);
std::sort(added.begin(), added.end(), LISorter());
addStackInterval(cur, ls_, li_, mri_, *vrm_);
while (!spillIs.empty()) {
LiveInterval *sli = spillIs.back();
spillIs.pop_back();
- DEBUG(errs() << "\t\t\tspilling(a): " << *sli << '\n');
+ DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
if (sli->beginIndex() < earliestStart)
earliestStart = sli->beginIndex();
- std::vector<LiveInterval*> newIs;
- newIs = spiller_->spill(sli, spillIs, &earliestStart);
+ spiller_->spill(sli, added, spillIs, &earliestStart);
addStackInterval(sli, ls_, li_, mri_, *vrm_);
- std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
spilled.insert(sli->reg);
}
- DEBUG(errs() << "\t\trolling back to: " << earliestStart << '\n');
+ DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
// Scan handled in reverse order up to the earliest start of a
// spilled live interval and undo each one, restoring the state of
// If this interval starts before t we are done.
if (!i->empty() && i->beginIndex() < earliestStart)
break;
- DEBUG(errs() << "\t\t\tundo changes for: " << *i << '\n');
+ DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
handled_.pop_back();
// When undoing a live interval allocation we must know if it is active or
LiveInterval *HI = handled_[i];
if (!HI->expiredAt(earliestStart) &&
HI->expiredAt(cur->beginIndex())) {
- DEBUG(errs() << "\t\t\tundo changes for: " << *HI << '\n');
+ DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
active_.push_back(std::make_pair(HI, HI->begin()));
assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
addRegUse(vrm_->getPhys(HI->reg));
// available first.
unsigned Preference = vrm_->getRegAllocPref(cur->reg);
if (Preference) {
- DEBUG(errs() << "(preferred: " << tri_->getName(Preference) << ") ");
+ DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
if (isRegAvail(Preference) &&
RC->contains(Preference))
return Preference;
projects / oota-llvm.git / blobdiff