#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
+#include "llvm/CodeGen/RegisterCoalescer.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/EquivalenceClasses.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
#include <algorithm>
-#include <cmath>
-#include <iostream>
#include <set>
#include <queue>
#include <memory>
+#include <cmath>
using namespace llvm;
-namespace {
+STATISTIC(NumIters , "Number of iterations performed");
+STATISTIC(NumBacktracks, "Number of times we had to backtrack");
+STATISTIC(NumCoalesce, "Number of copies coalesced");
- static Statistic<double> efficiency
- ("regalloc", "Ratio of intervals processed over total intervals");
- static Statistic<> NumBacktracks
- ("regalloc", "Number of times we had to backtrack");
+static RegisterRegAlloc
+linearscanRegAlloc("linearscan", " linear scan register allocator",
+ createLinearScanRegisterAllocator);
- static RegisterRegAlloc
- linearscanRegAlloc("linearscan", " linear scan register allocator",
- createLinearScanRegisterAllocator);
-
- static unsigned numIterations = 0;
- static unsigned numIntervals = 0;
+namespace {
+ struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
+ static char ID;
+ RALinScan() : MachineFunctionPass((intptr_t)&ID) {}
- struct VISIBILITY_HIDDEN RA : public MachineFunctionPass {
typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
typedef std::vector<IntervalPtr> IntervalPtrs;
private:
MachineFunction* mf_;
const TargetMachine* tm_;
const MRegisterInfo* mri_;
+ const TargetInstrInfo* tii_;
+ SSARegMap *regmap_;
+ BitVector allocatableRegs_;
LiveIntervals* li_;
- bool *PhysRegsUsed;
/// handled_ - Intervals are added to the handled_ set in the order of their
/// start value. This is uses for backtracking.
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<LiveIntervals>();
+ // Make sure PassManager knows which analyses to make available
+ // to coalescing and which analyses coalescing invalidates.
+ AU.addRequiredTransitive<RegisterCoalescer>();
MachineFunctionPass::getAnalysisUsage(AU);
}
/// is available, or spill.
void assignRegOrStackSlotAtInterval(LiveInterval* cur);
+ /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
+ /// try allocate the definition the same register as the source register
+ /// if the register is not defined during live time of the interval. This
+ /// eliminate a copy. This is used to coalesce copies which were not
+ /// coalesced away before allocation either due to dest and src being in
+ /// different register classes or because the coalescer was overly
+ /// conservative.
+ unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
+
///
/// register handling helpers
///
template <typename ItTy>
void printIntervals(const char* const str, ItTy i, ItTy e) const {
- if (str) std::cerr << str << " intervals:\n";
+ if (str) DOUT << str << " intervals:\n";
for (; i != e; ++i) {
- std::cerr << "\t" << *i->first << " -> ";
+ DOUT << "\t" << *i->first << " -> ";
unsigned reg = i->first->reg;
if (MRegisterInfo::isVirtualRegister(reg)) {
reg = vrm_->getPhys(reg);
}
- std::cerr << mri_->getName(reg) << '\n';
+ DOUT << mri_->getName(reg) << '\n';
}
}
};
+ char RALinScan::ID = 0;
}
-void RA::ComputeRelatedRegClasses() {
+void RALinScan::ComputeRelatedRegClasses() {
const MRegisterInfo &MRI = *mri_;
// First pass, add all reg classes to the union, and determine at least one
RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
}
-bool RA::runOnMachineFunction(MachineFunction &fn) {
+/// attemptTrivialCoalescing - If a simple interval is defined by a copy,
+/// try allocate the definition the same register as the source register
+/// if the register is not defined during live time of the interval. This
+/// eliminate a copy. This is used to coalesce copies which were not
+/// coalesced away before allocation either due to dest and src being in
+/// different register classes or because the coalescer was overly
+/// conservative.
+unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
+ if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
+ return Reg;
+
+ VNInfo *vni = cur.getValNumInfo(0);
+ if (!vni->def || vni->def == ~1U || vni->def == ~0U)
+ return Reg;
+ MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
+ unsigned SrcReg, DstReg;
+ if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
+ return Reg;
+ if (MRegisterInfo::isVirtualRegister(SrcReg))
+ if (!vrm_->isAssignedReg(SrcReg))
+ return Reg;
+ else
+ SrcReg = vrm_->getPhys(SrcReg);
+ if (Reg == SrcReg)
+ return Reg;
+
+ const TargetRegisterClass *RC = regmap_->getRegClass(cur.reg);
+ if (!RC->contains(SrcReg))
+ return Reg;
+
+ // Try to coalesce.
+ if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
+ vrm_->clearVirt(cur.reg);
+ vrm_->assignVirt2Phys(cur.reg, SrcReg);
+ ++NumCoalesce;
+ return SrcReg;
+ }
+
+ return Reg;
+}
+
+bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn;
tm_ = &fn.getTarget();
mri_ = tm_->getRegisterInfo();
+ tii_ = tm_->getInstrInfo();
+ regmap_ = mf_->getSSARegMap();
+ allocatableRegs_ = mri_->getAllocatableSet(fn);
li_ = &getAnalysis<LiveIntervals>();
+ // We don't run the coalescer here because we have no reason to
+ // interact with it. If the coalescer requires interaction, it
+ // won't do anything. If it doesn't require interaction, we assume
+ // it was run as a separate pass.
+
// If this is the first function compiled, compute the related reg classes.
if (RelatedRegClasses.empty())
ComputeRelatedRegClasses();
- PhysRegsUsed = new bool[mri_->getNumRegs()];
- std::fill(PhysRegsUsed, PhysRegsUsed+mri_->getNumRegs(), false);
- fn.setUsedPhysRegs(PhysRegsUsed);
-
if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_));
vrm_.reset(new VirtRegMap(*mf_));
if (!spiller_.get()) spiller_.reset(createSpiller());
// Rewrite spill code and update the PhysRegsUsed set.
spiller_->runOnMachineFunction(*mf_, *vrm_);
-
vrm_.reset(); // Free the VirtRegMap
-
while (!unhandled_.empty()) unhandled_.pop();
fixed_.clear();
active_.clear();
/// initIntervalSets - initialize the interval sets.
///
-void RA::initIntervalSets()
+void RALinScan::initIntervalSets()
{
assert(unhandled_.empty() && fixed_.empty() &&
active_.empty() && inactive_.empty() &&
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
if (MRegisterInfo::isPhysicalRegister(i->second.reg)) {
- PhysRegsUsed[i->second.reg] = true;
+ mf_->setPhysRegUsed(i->second.reg);
fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
} else
unhandled_.push(&i->second);
}
}
-void RA::linearScan()
+void RALinScan::linearScan()
{
// linear scan algorithm
- DEBUG(std::cerr << "********** LINEAR SCAN **********\n");
- DEBUG(std::cerr << "********** Function: "
- << mf_->getFunction()->getName() << '\n');
+ DOUT << "********** LINEAR SCAN **********\n";
+ DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
- // DEBUG(printIntervals("unhandled", unhandled_.begin(), unhandled_.end()));
DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
- DEBUG(printIntervals("active", active_.begin(), active_.end()));
- DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
while (!unhandled_.empty()) {
// pick the interval with the earliest start point
LiveInterval* cur = unhandled_.top();
unhandled_.pop();
- ++numIterations;
- DEBUG(std::cerr << "\n*** CURRENT ***: " << *cur << '\n');
+ ++NumIters;
+ DOUT << "\n*** CURRENT ***: " << *cur << '\n';
processActiveIntervals(cur->beginNumber());
processInactiveIntervals(cur->beginNumber());
DEBUG(printIntervals("active", active_.begin(), active_.end()));
DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
}
- numIntervals += li_->getNumIntervals();
- efficiency = double(numIterations) / double(numIntervals);
// expire any remaining active intervals
- for (IntervalPtrs::reverse_iterator
- i = active_.rbegin(); i != active_.rend(); ) {
- unsigned reg = i->first->reg;
- DEBUG(std::cerr << "\tinterval " << *i->first << " expired\n");
+ while (!active_.empty()) {
+ IntervalPtr &IP = active_.back();
+ unsigned reg = IP.first->reg;
+ DOUT << "\tinterval " << *IP.first << " expired\n";
assert(MRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
prt_->delRegUse(reg);
- i = IntervalPtrs::reverse_iterator(active_.erase(i.base()-1));
+ active_.pop_back();
}
// expire any remaining inactive intervals
- for (IntervalPtrs::reverse_iterator
- i = inactive_.rbegin(); i != inactive_.rend(); ) {
- DEBUG(std::cerr << "\tinterval " << *i->first << " expired\n");
- i = IntervalPtrs::reverse_iterator(inactive_.erase(i.base()-1));
+ DEBUG(for (IntervalPtrs::reverse_iterator
+ i = inactive_.rbegin(); i != inactive_.rend(); ++i)
+ DOUT << "\tinterval " << *i->first << " expired\n");
+ inactive_.clear();
+
+ // Add live-ins to every BB except for entry.
+ MachineFunction::iterator EntryMBB = mf_->begin();
+ SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
+ for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
+ LiveInterval &cur = i->second;
+ unsigned Reg = 0;
+ if (MRegisterInfo::isPhysicalRegister(cur.reg))
+ Reg = i->second.reg;
+ else if (vrm_->isAssignedReg(cur.reg))
+ Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
+ if (!Reg)
+ continue;
+ for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
+ I != E; ++I) {
+ const LiveRange &LR = *I;
+ if (li_->findLiveInMBBs(LR, LiveInMBBs)) {
+ for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
+ if (LiveInMBBs[i] != EntryMBB)
+ LiveInMBBs[i]->addLiveIn(Reg);
+ LiveInMBBs.clear();
+ }
+ }
}
- DEBUG(std::cerr << *vrm_);
+ DOUT << *vrm_;
}
/// processActiveIntervals - expire old intervals and move non-overlapping ones
/// to the inactive list.
-void RA::processActiveIntervals(unsigned CurPoint)
+void RALinScan::processActiveIntervals(unsigned CurPoint)
{
- DEBUG(std::cerr << "\tprocessing active intervals:\n");
+ DOUT << "\tprocessing active intervals:\n";
for (unsigned i = 0, e = active_.size(); i != e; ++i) {
LiveInterval *Interval = active_[i].first;
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
if (IntervalPos == Interval->end()) { // Remove expired intervals.
- DEBUG(std::cerr << "\t\tinterval " << *Interval << " expired\n");
+ DOUT << "\t\tinterval " << *Interval << " expired\n";
assert(MRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
} else if (IntervalPos->start > CurPoint) {
// Move inactive intervals to inactive list.
- DEBUG(std::cerr << "\t\tinterval " << *Interval << " inactive\n");
+ DOUT << "\t\tinterval " << *Interval << " inactive\n";
assert(MRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
/// processInactiveIntervals - expire old intervals and move overlapping
/// ones to the active list.
-void RA::processInactiveIntervals(unsigned CurPoint)
+void RALinScan::processInactiveIntervals(unsigned CurPoint)
{
- DEBUG(std::cerr << "\tprocessing inactive intervals:\n");
+ DOUT << "\tprocessing inactive intervals:\n";
for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
LiveInterval *Interval = inactive_[i].first;
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
if (IntervalPos == Interval->end()) { // remove expired intervals.
- DEBUG(std::cerr << "\t\tinterval " << *Interval << " expired\n");
+ DOUT << "\t\tinterval " << *Interval << " expired\n";
// Pop off the end of the list.
inactive_[i] = inactive_.back();
--i; --e;
} else if (IntervalPos->start <= CurPoint) {
// move re-activated intervals in active list
- DEBUG(std::cerr << "\t\tinterval " << *Interval << " active\n");
+ DOUT << "\t\tinterval " << *Interval << " active\n";
assert(MRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!");
reg = vrm_->getPhys(reg);
Weights[*as] += weight;
}
-static RA::IntervalPtrs::iterator FindIntervalInVector(RA::IntervalPtrs &IP,
- LiveInterval *LI) {
- for (RA::IntervalPtrs::iterator I = IP.begin(), E = IP.end(); I != E; ++I)
+static
+RALinScan::IntervalPtrs::iterator
+FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
+ for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
+ I != E; ++I)
if (I->first == LI) return I;
return IP.end();
}
-static void RevertVectorIteratorsTo(RA::IntervalPtrs &V, unsigned Point) {
+static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
for (unsigned i = 0, e = V.size(); i != e; ++i) {
- RA::IntervalPtr &IP = V[i];
+ RALinScan::IntervalPtr &IP = V[i];
LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
IP.second, Point);
if (I != IP.first->begin()) --I;
/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
/// spill.
-void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
+void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
{
- DEBUG(std::cerr << "\tallocating current interval: ");
+ DOUT << "\tallocating current interval: ";
PhysRegTracker backupPrt = *prt_;
std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
unsigned StartPosition = cur->beginNumber();
- const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(cur->reg);
+ const TargetRegisterClass *RC = regmap_->getRegClass(cur->reg);
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
-
+
+ // If this live interval is defined by a move instruction and its source is
+ // assigned a physical register that is compatible with the target register
+ // class, then we should try to assign it the same register.
+ // This can happen when the move is from a larger register class to a smaller
+ // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
+ if (!cur->preference && cur->containsOneValue()) {
+ VNInfo *vni = cur->getValNumInfo(0);
+ if (vni->def && vni->def != ~1U && vni->def != ~0U) {
+ MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
+ unsigned SrcReg, DstReg;
+ if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
+ unsigned Reg = 0;
+ if (MRegisterInfo::isPhysicalRegister(SrcReg))
+ Reg = SrcReg;
+ else if (vrm_->isAssignedReg(SrcReg))
+ Reg = vrm_->getPhys(SrcReg);
+ if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
+ cur->preference = Reg;
+ }
+ }
+ }
+
// for every interval in inactive we overlap with, mark the
// register as not free and update spill weights.
for (IntervalPtrs::const_iterator i = inactive_.begin(),
unsigned Reg = i->first->reg;
assert(MRegisterInfo::isVirtualRegister(Reg) &&
"Can only allocate virtual registers!");
- const TargetRegisterClass *RegRC = mf_->getSSARegMap()->getRegClass(Reg);
+ const TargetRegisterClass *RegRC = regmap_->getRegClass(Reg);
// If this is not in a related reg class to the register we're allocating,
// don't check it.
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
// We got a register. However, if it's in the fixed_ list, we might
// conflict with it. Check to see if we conflict with it or any of its
// aliases.
- std::set<unsigned> RegAliases;
+ SmallSet<unsigned, 8> RegAliases;
for (const unsigned *AS = mri_->getAliasSet(physReg); *AS; ++AS)
RegAliases.insert(*AS);
// the free physical register and add this interval to the active
// list.
if (physReg) {
- DEBUG(std::cerr << mri_->getName(physReg) << '\n');
+ DOUT << mri_->getName(physReg) << '\n';
vrm_->assignVirt2Phys(cur->reg, physReg);
prt_->addRegUse(physReg);
active_.push_back(std::make_pair(cur, cur->begin()));
handled_.push_back(cur);
return;
}
- DEBUG(std::cerr << "no free registers\n");
+ DOUT << "no free registers\n";
// Compile the spill weights into an array that is better for scanning.
std::vector<float> SpillWeights(mri_->getNumRegs(), 0.0);
updateSpillWeights(SpillWeights, reg, i->first->weight, mri_);
}
- DEBUG(std::cerr << "\tassigning stack slot at interval "<< *cur << ":\n");
+ DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
// Find a register to spill.
float minWeight = HUGE_VALF;
- unsigned minReg = 0;
- for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
- e = RC->allocation_order_end(*mf_); i != e; ++i) {
- unsigned reg = *i;
- if (minWeight > SpillWeights[reg]) {
- minWeight = SpillWeights[reg];
- minReg = reg;
+ unsigned minReg = cur->preference; // Try the preferred register first.
+
+ if (!minReg || SpillWeights[minReg] == HUGE_VALF)
+ for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
+ e = RC->allocation_order_end(*mf_); i != e; ++i) {
+ unsigned reg = *i;
+ if (minWeight > SpillWeights[reg]) {
+ minWeight = SpillWeights[reg];
+ minReg = reg;
+ }
}
- }
// If we didn't find a register that is spillable, try aliases?
if (!minReg) {
minReg = *RC->allocation_order_begin(*mf_);
}
- DEBUG(std::cerr << "\t\tregister with min weight: "
- << mri_->getName(minReg) << " (" << minWeight << ")\n");
+ DOUT << "\t\tregister with min weight: "
+ << mri_->getName(minReg) << " (" << minWeight << ")\n";
// if the current has the minimum weight, we need to spill it and
// add any added intervals back to unhandled, and restart
// linearscan.
if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
- DEBUG(std::cerr << "\t\t\tspilling(c): " << *cur << '\n';);
- int slot = vrm_->assignVirt2StackSlot(cur->reg);
+ DOUT << "\t\t\tspilling(c): " << *cur << '\n';
std::vector<LiveInterval*> added =
- li_->addIntervalsForSpills(*cur, *vrm_, slot);
+ li_->addIntervalsForSpills(*cur, *vrm_);
if (added.empty())
return; // Early exit if all spills were folded.
std::vector<LiveInterval*> added;
assert(MRegisterInfo::isPhysicalRegister(minReg) &&
"did not choose a register to spill?");
- std::vector<bool> toSpill(mri_->getNumRegs(), false);
+ BitVector toSpill(mri_->getNumRegs());
// We are going to spill minReg and all its aliases.
toSpill[minReg] = true;
unsigned earliestStart = cur->beginNumber();
// set of spilled vregs (used later to rollback properly)
- std::set<unsigned> spilled;
+ SmallSet<unsigned, 32> spilled;
// spill live intervals of virtual regs mapped to the physical register we
// want to clear (and its aliases). We only spill those that overlap with the
if (//MRegisterInfo::isVirtualRegister(reg) &&
toSpill[vrm_->getPhys(reg)] &&
cur->overlapsFrom(*i->first, i->second)) {
- DEBUG(std::cerr << "\t\t\tspilling(a): " << *i->first << '\n');
+ DOUT << "\t\t\tspilling(a): " << *i->first << '\n';
earliestStart = std::min(earliestStart, i->first->beginNumber());
- int slot = vrm_->assignVirt2StackSlot(i->first->reg);
std::vector<LiveInterval*> newIs =
- li_->addIntervalsForSpills(*i->first, *vrm_, slot);
+ li_->addIntervalsForSpills(*i->first, *vrm_);
std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
spilled.insert(reg);
}
if (//MRegisterInfo::isVirtualRegister(reg) &&
toSpill[vrm_->getPhys(reg)] &&
cur->overlapsFrom(*i->first, i->second-1)) {
- DEBUG(std::cerr << "\t\t\tspilling(i): " << *i->first << '\n');
+ DOUT << "\t\t\tspilling(i): " << *i->first << '\n';
earliestStart = std::min(earliestStart, i->first->beginNumber());
- int slot = vrm_->assignVirt2StackSlot(reg);
std::vector<LiveInterval*> newIs =
- li_->addIntervalsForSpills(*i->first, *vrm_, slot);
+ li_->addIntervalsForSpills(*i->first, *vrm_);
std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
spilled.insert(reg);
}
}
- DEBUG(std::cerr << "\t\trolling back to: " << earliestStart << '\n');
+ DOUT << "\t\trolling back to: " << earliestStart << '\n';
// Scan handled in reverse order up to the earliest start of a
// spilled live interval and undo each one, restoring the state of
// If this interval starts before t we are done.
if (i->beginNumber() < earliestStart)
break;
- DEBUG(std::cerr << "\t\t\tundo changes for: " << *i << '\n');
+ DOUT << "\t\t\tundo changes for: " << *i << '\n';
handled_.pop_back();
// When undoing a live interval allocation we must know if it is active or
vrm_->clearVirt(i->reg);
unhandled_.push(i);
}
+
+ // It interval has a preference, it must be defined by a copy. Clear the
+ // preference now since the source interval allocation may have been undone
+ // as well.
+ i->preference = 0;
}
// Rewind the iterators in the active, inactive, and fixed lists back to the
LiveInterval *HI = handled_[i];
if (!HI->expiredAt(earliestStart) &&
HI->expiredAt(cur->beginNumber())) {
- DEBUG(std::cerr << "\t\t\tundo changes for: " << *HI << '\n');
+ DOUT << "\t\t\tundo changes for: " << *HI << '\n';
active_.push_back(std::make_pair(HI, HI->begin()));
assert(!MRegisterInfo::isPhysicalRegister(HI->reg));
prt_->addRegUse(vrm_->getPhys(HI->reg));
/// getFreePhysReg - return a free physical register for this virtual register
/// interval if we have one, otherwise return 0.
-unsigned RA::getFreePhysReg(LiveInterval *cur) {
+unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
std::vector<unsigned> inactiveCounts(mri_->getNumRegs(), 0);
unsigned MaxInactiveCount = 0;
- const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(cur->reg);
+ const TargetRegisterClass *RC = regmap_->getRegClass(cur->reg);
const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
// If this is not in a related reg class to the register we're allocating,
// don't check it.
- const TargetRegisterClass *RegRC = mf_->getSSARegMap()->getRegClass(reg);
+ const TargetRegisterClass *RegRC = regmap_->getRegClass(reg);
if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
reg = vrm_->getPhys(reg);
++inactiveCounts[reg];
}
}
- const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
-
unsigned FreeReg = 0;
unsigned FreeRegInactiveCount = 0;
-
+
+ // If copy coalescer has assigned a "preferred" register, check if it's
+ // available first.
+ if (cur->preference)
+ if (prt_->isRegAvail(cur->preference)) {
+ DOUT << "\t\tassigned the preferred register: "
+ << mri_->getName(cur->preference) << "\n";
+ return cur->preference;
+ } else
+ DOUT << "\t\tunable to assign the preferred register: "
+ << mri_->getName(cur->preference) << "\n";
+
// Scan for the first available register.
- TargetRegisterClass::iterator I = rc->allocation_order_begin(*mf_);
- TargetRegisterClass::iterator E = rc->allocation_order_end(*mf_);
+ TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
+ TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
for (; I != E; ++I)
if (prt_->isRegAvail(*I)) {
FreeReg = *I;
}
FunctionPass* llvm::createLinearScanRegisterAllocator() {
- return new RA();
+ return new RALinScan();
}
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