#include "Spiller.h"
#include "VirtRegMap.h"
#include "VirtRegRewriter.h"
+#include "llvm/ADT/OwningPtr.h"
+#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Function.h"
#include "llvm/PassAnalysisSupport.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#ifndef NDEBUG
+#include "llvm/ADT/SparseBitVector.h"
+#endif
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Timer.h"
-#include <vector>
-#include <queue>
+#include <cstdlib>
using namespace llvm;
static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
createBasicRegisterAllocator);
+// Temporary verification option until we can put verification inside
+// MachineVerifier.
+static cl::opt<bool>
+VerifyRegAlloc("verify-regalloc",
+ cl::desc("Verify live intervals before renaming"));
+
+const char *RegAllocBase::TimerGroupName = "Register Allocation";
+
namespace {
+class PhysicalRegisterDescription : public AbstractRegisterDescription {
+ const TargetRegisterInfo *TRI;
+public:
+ PhysicalRegisterDescription(const TargetRegisterInfo *T): TRI(T) {}
+ virtual const char *getName(unsigned Reg) const { return TRI->getName(Reg); }
+};
+
/// RABasic provides a minimal implementation of the basic register allocation
/// algorithm. It prioritizes live virtual registers by spill weight and spills
/// whenever a register is unavailable. This is not practical in production but
class RABasic : public MachineFunctionPass, public RegAllocBase
{
// context
- MachineFunction *mf_;
- const TargetMachine *tm_;
- MachineRegisterInfo *mri_;
+ MachineFunction *MF;
+ BitVector ReservedRegs;
// analyses
- LiveStacks *ls_;
- RenderMachineFunction *rmf_;
+ LiveStacks *LS;
+ RenderMachineFunction *RMF;
// state
- std::auto_ptr<Spiller> spiller_;
+ std::auto_ptr<Spiller> SpillerInstance;
public:
RABasic();
}
/// RABasic analysis usage.
- virtual void getAnalysisUsage(AnalysisUsage &au) const;
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const;
virtual void releaseMemory();
- virtual unsigned selectOrSplit(LiveInterval &lvr,
- SmallVectorImpl<LiveInterval*> &splitLVRs);
+ virtual Spiller &spiller() { return *SpillerInstance; }
+
+ virtual float getPriority(LiveInterval *LI) { return LI->weight; }
+
+ virtual unsigned selectOrSplit(LiveInterval &VirtReg,
+ SmallVectorImpl<LiveInterval*> &SplitVRegs);
- void spillInterferences(unsigned preg,
- SmallVectorImpl<LiveInterval*> &splitLVRs);
-
/// Perform register allocation.
virtual bool runOnMachineFunction(MachineFunction &mf);
} // end anonymous namespace
-// We should not need to publish the initializer as long as no other passes
-// require RABasic.
-#if 0 // disable INITIALIZE_PASS
-INITIALIZE_PASS_BEGIN(RABasic, "basic-regalloc",
- "Basic Register Allocator", false, false)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
-INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
-INITIALIZE_AG_DEPENDENCY(RegisterCoalescer)
-INITIALIZE_PASS_DEPENDENCY(CalculateSpillWeights)
-INITIALIZE_PASS_DEPENDENCY(LiveStacks)
-INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
-#ifndef NDEBUG
-INITIALIZE_PASS_DEPENDENCY(RenderMachineFunction)
-#endif
-INITIALIZE_PASS_END(RABasic, "basic-regalloc",
- "Basic Register Allocator", false, false)
-#endif // disable INITIALIZE_PASS
-
RABasic::RABasic(): MachineFunctionPass(ID) {
initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
}
-void RABasic::getAnalysisUsage(AnalysisUsage &au) const {
- au.setPreservesCFG();
- au.addRequired<LiveIntervals>();
- au.addPreserved<SlotIndexes>();
+void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesCFG();
+ AU.addRequired<AliasAnalysis>();
+ AU.addPreserved<AliasAnalysis>();
+ AU.addRequired<LiveIntervals>();
+ AU.addPreserved<SlotIndexes>();
if (StrongPHIElim)
- au.addRequiredID(StrongPHIEliminationID);
- au.addRequiredTransitive<RegisterCoalescer>();
- au.addRequired<CalculateSpillWeights>();
- au.addRequired<LiveStacks>();
- au.addPreserved<LiveStacks>();
- au.addRequiredID(MachineDominatorsID);
- au.addPreservedID(MachineDominatorsID);
- au.addRequired<MachineLoopInfo>();
- au.addPreserved<MachineLoopInfo>();
- au.addRequired<VirtRegMap>();
- au.addPreserved<VirtRegMap>();
- DEBUG(au.addRequired<RenderMachineFunction>());
- MachineFunctionPass::getAnalysisUsage(au);
+ AU.addRequiredID(StrongPHIEliminationID);
+ AU.addRequiredTransitive<RegisterCoalescer>();
+ AU.addRequired<CalculateSpillWeights>();
+ AU.addRequired<LiveStacks>();
+ AU.addPreserved<LiveStacks>();
+ AU.addRequiredID(MachineDominatorsID);
+ AU.addPreservedID(MachineDominatorsID);
+ AU.addRequired<MachineLoopInfo>();
+ AU.addPreserved<MachineLoopInfo>();
+ AU.addRequired<VirtRegMap>();
+ AU.addPreserved<VirtRegMap>();
+ DEBUG(AU.addRequired<RenderMachineFunction>());
+ MachineFunctionPass::getAnalysisUsage(AU);
}
void RABasic::releaseMemory() {
- spiller_.reset(0);
+ SpillerInstance.reset(0);
RegAllocBase::releaseMemory();
}
+#ifndef NDEBUG
+// Verify each LiveIntervalUnion.
+void RegAllocBase::verify() {
+ LiveVirtRegBitSet VisitedVRegs;
+ OwningArrayPtr<LiveVirtRegBitSet>
+ unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
+
+ // Verify disjoint unions.
+ for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
+ DEBUG(PhysicalRegisterDescription PRD(TRI);
+ PhysReg2LiveUnion[PhysReg].dump(&PRD));
+ LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
+ PhysReg2LiveUnion[PhysReg].verify(VRegs);
+ // Union + intersection test could be done efficiently in one pass, but
+ // don't add a method to SparseBitVector unless we really need it.
+ assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
+ VisitedVRegs |= VRegs;
+ }
+
+ // Verify vreg coverage.
+ for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
+ liItr != liEnd; ++liItr) {
+ unsigned reg = liItr->first;
+ if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
+ if (!VRM->hasPhys(reg)) continue; // spilled?
+ unsigned PhysReg = VRM->getPhys(reg);
+ if (!unionVRegs[PhysReg].test(reg)) {
+ dbgs() << "LiveVirtReg " << reg << " not in union " <<
+ TRI->getName(PhysReg) << "\n";
+ llvm_unreachable("unallocated live vreg");
+ }
+ }
+ // FIXME: I'm not sure how to verify spilled intervals.
+}
+#endif //!NDEBUG
+
//===----------------------------------------------------------------------===//
// RegAllocBase Implementation
//===----------------------------------------------------------------------===//
// Instantiate a LiveIntervalUnion for each physical register.
-void RegAllocBase::LIUArray::init(unsigned nRegs) {
- array_.reset(new LiveIntervalUnion[nRegs]);
- nRegs_ = nRegs;
- for (unsigned pr = 0; pr < nRegs; ++pr) {
- array_[pr].init(pr);
- }
+void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
+ unsigned NRegs) {
+ NumRegs = NRegs;
+ Array =
+ static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
+ for (unsigned r = 0; r != NRegs; ++r)
+ new(Array + r) LiveIntervalUnion(r, allocator);
}
-void RegAllocBase::init(const TargetRegisterInfo &tri, VirtRegMap &vrm,
- LiveIntervals &lis) {
- tri_ = &tri;
- vrm_ = &vrm;
- lis_ = &lis;
- physReg2liu_.init(tri_->getNumRegs());
+void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
+ NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
+ TRI = &vrm.getTargetRegInfo();
+ MRI = &vrm.getRegInfo();
+ VRM = &vrm;
+ LIS = &lis;
+ PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
// Cache an interferece query for each physical reg
- queries_.reset(new LiveIntervalUnion::Query[physReg2liu_.numRegs()]);
+ Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
}
-void RegAllocBase::LIUArray::clear() {
- nRegs_ = 0;
- array_.reset(0);
+void RegAllocBase::LiveUnionArray::clear() {
+ if (!Array)
+ return;
+ for (unsigned r = 0; r != NumRegs; ++r)
+ Array[r].~LiveIntervalUnion();
+ free(Array);
+ NumRegs = 0;
+ Array = 0;
}
void RegAllocBase::releaseMemory() {
- physReg2liu_.clear();
+ PhysReg2LiveUnion.clear();
}
-namespace llvm {
-/// This class defines a queue of live virtual registers prioritized by spill
-/// weight. The heaviest vreg is popped first.
-///
-/// Currently, this is trivial wrapper that gives us an opaque type in the
-/// header, but we may later give it a virtual interface for register allocators
-/// to override the priority queue comparator.
-class LiveVirtRegQueue {
- typedef std::priority_queue
- <LiveInterval*, std::vector<LiveInterval*>, LessSpillWeightPriority> PQ;
- PQ pq_;
-
-public:
- // Is the queue empty?
- bool empty() { return pq_.empty(); }
-
- // Get the highest priority lvr (top + pop)
- LiveInterval *get() {
- LiveInterval *lvr = pq_.top();
- pq_.pop();
- return lvr;
- }
- // Add this lvr to the queue
- void push(LiveInterval *lvr) {
- pq_.push(lvr);
- }
-};
-} // end namespace llvm
-
// Visit all the live virtual registers. If they are already assigned to a
// physical register, unify them with the corresponding LiveIntervalUnion,
// otherwise push them on the priority queue for later assignment.
-void RegAllocBase::seedLiveVirtRegs(LiveVirtRegQueue &lvrQ) {
- for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end();
- liItr != liEnd; ++liItr) {
- unsigned reg = liItr->first;
- LiveInterval &li = *liItr->second;
- if (TargetRegisterInfo::isPhysicalRegister(reg)) {
- physReg2liu_[reg].unify(li);
- }
- else {
- lvrQ.push(&li);
- }
+void RegAllocBase::
+seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> > &VirtRegQ) {
+ for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
+ unsigned RegNum = I->first;
+ LiveInterval &VirtReg = *I->second;
+ if (TargetRegisterInfo::isPhysicalRegister(RegNum))
+ PhysReg2LiveUnion[RegNum].unify(VirtReg);
+ else
+ VirtRegQ.push(std::make_pair(getPriority(&VirtReg), RegNum));
}
}
-// Top-level driver to manage the queue of unassigned LiveVirtRegs and call the
+// Top-level driver to manage the queue of unassigned VirtRegs and call the
// selectOrSplit implementation.
void RegAllocBase::allocatePhysRegs() {
- LiveVirtRegQueue lvrQ;
- seedLiveVirtRegs(lvrQ);
- while (!lvrQ.empty()) {
- LiveInterval *lvr = lvrQ.get();
- typedef SmallVector<LiveInterval*, 4> LVRVec;
- LVRVec splitLVRs;
- unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs);
- if (availablePhysReg) {
- DEBUG(dbgs() << "allocating: " << tri_->getName(availablePhysReg) <<
- " " << lvr << '\n');
- assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions");
- vrm_->assignVirt2Phys(lvr->reg, availablePhysReg);
- physReg2liu_[availablePhysReg].unify(*lvr);
+
+ // Push each vreg onto a queue or "precolor" by adding it to a physreg union.
+ std::priority_queue<std::pair<float, unsigned> > VirtRegQ;
+ seedLiveVirtRegs(VirtRegQ);
+
+ // Continue assigning vregs one at a time to available physical registers.
+ while (!VirtRegQ.empty()) {
+ // Pop the highest priority vreg.
+ LiveInterval &VirtReg = LIS->getInterval(VirtRegQ.top().second);
+ VirtRegQ.pop();
+
+ // selectOrSplit requests the allocator to return an available physical
+ // register if possible and populate a list of new live intervals that
+ // result from splitting.
+ DEBUG(dbgs() << "\nselectOrSplit " << MRI->getRegClass(VirtReg.reg)->getName()
+ << ':' << VirtReg << '\n');
+ typedef SmallVector<LiveInterval*, 4> VirtRegVec;
+ VirtRegVec SplitVRegs;
+ unsigned AvailablePhysReg = selectOrSplit(VirtReg, SplitVRegs);
+
+ if (AvailablePhysReg) {
+ DEBUG(dbgs() << "allocating: " << TRI->getName(AvailablePhysReg)
+ << " for " << VirtReg << '\n');
+ assert(!VRM->hasPhys(VirtReg.reg) && "duplicate vreg in union");
+ VRM->assignVirt2Phys(VirtReg.reg, AvailablePhysReg);
+ PhysReg2LiveUnion[AvailablePhysReg].unify(VirtReg);
}
- for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end();
- lvrI != lvrEnd; ++lvrI) {
- DEBUG(dbgs() << "queuing new interval: " << **lvrI << "\n");
- assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) &&
+ for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
+ I != E; ++I) {
+ LiveInterval* SplitVirtReg = *I;
+ if (SplitVirtReg->empty()) continue;
+ DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
+ assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
"expect split value in virtual register");
- lvrQ.push(*lvrI);
+ VirtRegQ.push(std::make_pair(getPriority(SplitVirtReg),
+ SplitVirtReg->reg));
}
}
}
-// Check if this live virtual reg interferes with a physical register. If not,
-// then check for interference on each register that aliases with the physical
-// register. Return the interfering register.
-unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &lvr,
- unsigned preg) {
- queries_[preg].init(&lvr, &physReg2liu_[preg]);
- if (queries_[preg].checkInterference())
- return preg;
- for (const unsigned *asI = tri_->getAliasSet(preg); *asI; ++asI) {
- queries_[*asI].init(&lvr, &physReg2liu_[*asI]);
- if (queries_[*asI].checkInterference())
- return *asI;
+// Check if this live virtual register interferes with a physical register. If
+// not, then check for interference on each register that aliases with the
+// physical register. Return the interfering register.
+unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
+ unsigned PhysReg) {
+ if (query(VirtReg, PhysReg).checkInterference())
+ return PhysReg;
+ for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
+ if (query(VirtReg, *AliasI).checkInterference())
+ return *AliasI;
}
return 0;
}
-// Spill all live virtual registers currently unified under preg that interfere
-// with lvr.
-void RABasic::spillInterferences(unsigned preg,
- SmallVectorImpl<LiveInterval*> &splitLVRs) {
- SmallPtrSet<LiveInterval*, 8> spilledLVRs;
- LiveIntervalUnion::Query &query = queries_[preg];
- LiveIntervalUnion::InterferenceResult ir = query.firstInterference();
- assert(query.isInterference(ir) && "expect interference");
- do {
- LiveInterval *lvr = ir.liuSegPos()->liveVirtReg;
- if (!spilledLVRs.insert(lvr)) continue;
- // Spill the previously allocated lvr.
- SmallVector<LiveInterval*, 1> spillIs; // ignored
- spiller_->spill(lvr, splitLVRs, spillIs);
- } while (query.nextInterference(ir));
- for (SmallPtrSetIterator<LiveInterval*> lvrI = spilledLVRs.begin(),
- lvrEnd = spilledLVRs.end();
- lvrI != lvrEnd; ++lvrI ) {
- // Deallocate the interfering lvr by removing it from the preg union.
- physReg2liu_[preg].extract(**lvrI);
+// Helper for spillInteferences() that spills all interfering vregs currently
+// assigned to this physical register.
+void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
+ SmallVectorImpl<LiveInterval*> &SplitVRegs) {
+ LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
+ assert(Q.seenAllInterferences() && "need collectInterferences()");
+ const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
+
+ for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
+ E = PendingSpills.end(); I != E; ++I) {
+ LiveInterval &SpilledVReg = **I;
+ DEBUG(dbgs() << "extracting from " <<
+ TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
+
+ // Deallocate the interfering vreg by removing it from the union.
+ // A LiveInterval instance may not be in a union during modification!
+ PhysReg2LiveUnion[PhysReg].extract(SpilledVReg);
+
+ // Clear the vreg assignment.
+ VRM->clearVirt(SpilledVReg.reg);
+
+ // Spill the extracted interval.
+ spiller().spill(&SpilledVReg, SplitVRegs, PendingSpills);
+ }
+ // After extracting segments, the query's results are invalid. But keep the
+ // contents valid until we're done accessing pendingSpills.
+ Q.clear();
+}
+
+// Spill or split all live virtual registers currently unified under PhysReg
+// that interfere with VirtReg. The newly spilled or split live intervals are
+// returned by appending them to SplitVRegs.
+bool
+RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
+ SmallVectorImpl<LiveInterval*> &SplitVRegs) {
+ // Record each interference and determine if all are spillable before mutating
+ // either the union or live intervals.
+
+ // Collect interferences assigned to the requested physical register.
+ LiveIntervalUnion::Query &QPreg = query(VirtReg, PhysReg);
+ unsigned NumInterferences = QPreg.collectInterferingVRegs();
+ if (QPreg.seenUnspillableVReg()) {
+ return false;
+ }
+ // Collect interferences assigned to any alias of the physical register.
+ for (const unsigned *asI = TRI->getAliasSet(PhysReg); *asI; ++asI) {
+ LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
+ NumInterferences += QAlias.collectInterferingVRegs();
+ if (QAlias.seenUnspillableVReg()) {
+ return false;
+ }
}
- // After extracting segments, the query's results are invalid.
- query.clear();
+ DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
+ " interferences with " << VirtReg << "\n");
+ assert(NumInterferences > 0 && "expect interference");
+
+ // Spill each interfering vreg allocated to PhysReg or an alias.
+ spillReg(VirtReg, PhysReg, SplitVRegs);
+ for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI)
+ spillReg(VirtReg, *AliasI, SplitVRegs);
+ return true;
}
+// Add newly allocated physical registers to the MBB live in sets.
+void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
+ NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
+ typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
+ MBBVec liveInMBBs;
+ MachineBasicBlock &entryMBB = *MF->begin();
+
+ for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
+ LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
+ if (LiveUnion.empty())
+ continue;
+ for (LiveIntervalUnion::SegmentIter SI = LiveUnion.begin(); SI.valid();
+ ++SI) {
+
+ // Find the set of basic blocks which this range is live into...
+ liveInMBBs.clear();
+ if (!LIS->findLiveInMBBs(SI.start(), SI.stop(), liveInMBBs)) continue;
+
+ // And add the physreg for this interval to their live-in sets.
+ for (MBBVec::iterator I = liveInMBBs.begin(), E = liveInMBBs.end();
+ I != E; ++I) {
+ MachineBasicBlock *MBB = *I;
+ if (MBB == &entryMBB) continue;
+ if (MBB->isLiveIn(PhysReg)) continue;
+ MBB->addLiveIn(PhysReg);
+ }
+ }
+ }
+}
+
+
//===----------------------------------------------------------------------===//
// RABasic Implementation
//===----------------------------------------------------------------------===//
// Driver for the register assignment and splitting heuristics.
// Manages iteration over the LiveIntervalUnions.
-//
-// Minimal implementation of register assignment and splitting--spills whenever
-// we run out of registers.
+//
+// This is a minimal implementation of register assignment and splitting that
+// spills whenever we run out of registers.
//
// selectOrSplit can only be called once per live virtual register. We then do a
// single interference test for each register the correct class until we find an
// available register. So, the number of interference tests in the worst case is
// |vregs| * |machineregs|. And since the number of interference tests is
-// minimal, there is no value in caching them.
-unsigned RABasic::selectOrSplit(LiveInterval &lvr,
- SmallVectorImpl<LiveInterval*> &splitLVRs) {
- // Accumulate the min spill cost among the interferences, in case we spill.
- unsigned minSpillReg = 0;
- unsigned minSpillAlias = 0;
- float minSpillWeight = lvr.weight;
-
- // Check for an available reg in this class.
- const TargetRegisterClass *trc = mri_->getRegClass(lvr.reg);
- for (TargetRegisterClass::iterator trcI = trc->allocation_order_begin(*mf_),
- trcEnd = trc->allocation_order_end(*mf_);
- trcI != trcEnd; ++trcI) {
- unsigned preg = *trcI;
- unsigned interfReg = checkPhysRegInterference(lvr, preg);
+// minimal, there is no value in caching them outside the scope of
+// selectOrSplit().
+unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
+ SmallVectorImpl<LiveInterval*> &SplitVRegs) {
+ // Populate a list of physical register spill candidates.
+ SmallVector<unsigned, 8> PhysRegSpillCands;
+
+ // Check for an available register in this class.
+ const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
+
+ for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
+ E = TRC->allocation_order_end(*MF);
+ I != E; ++I) {
+
+ unsigned PhysReg = *I;
+ if (ReservedRegs.test(PhysReg)) continue;
+
+ // Check interference and as a side effect, intialize queries for this
+ // VirtReg and its aliases.
+ unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
if (interfReg == 0) {
- return preg;
+ // Found an available register.
+ return PhysReg;
}
- LiveIntervalUnion::InterferenceResult interf =
- queries_[interfReg].firstInterference();
- float interfWeight = interf.liuSegPos()->liveVirtReg->weight;
- if (interfWeight < minSpillWeight ) {
- minSpillReg = interfReg;
- minSpillAlias = preg;
- minSpillWeight = interfWeight;
+ LiveInterval *interferingVirtReg =
+ Queries[interfReg].firstInterference().liveUnionPos().value();
+
+ // The current VirtReg must either be spillable, or one of its interferences
+ // must have less spill weight.
+ if (interferingVirtReg->weight < VirtReg.weight ) {
+ PhysRegSpillCands.push_back(PhysReg);
}
}
- if (minSpillReg == 0) {
- DEBUG(dbgs() << "spilling: " << lvr << '\n');
- SmallVector<LiveInterval*, 1> spillIs; // ignored
- spiller_->spill(&lvr, splitLVRs, spillIs);
- // The live virtual register requesting to be allocated was spilled. So tell
- // the caller not to allocate anything for this round.
- return 0;
- }
- // Free the cheapest physical register.
- spillInterferences(minSpillReg, splitLVRs);
- // Tell the caller to allocate to this newly freed physical register.
- assert(minSpillAlias != 0 && "need a free register after spilling");
- // We just spilled the first register that interferes with minSpillAlias. We
- // now assume minSpillAlias is free because only one register alias may
- // interfere at a time. e.g. we ignore predication.
- unsigned interfReg = checkPhysRegInterference(lvr, minSpillAlias);
- if (interfReg != 0) {
- dbgs() << "spilling cannot free " << tri_->getName(minSpillAlias) <<
- " for " << lvr.reg << " with interference " <<
- *queries_[interfReg].firstInterference().liuSegPos()->liveVirtReg << "\n";
- llvm_unreachable("Interference after spill.");
+ // Try to spill another interfering reg with less spill weight.
+ for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
+ PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
+
+ if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
+
+ assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
+ "Interference after spill.");
+ // Tell the caller to allocate to this newly freed physical register.
+ return *PhysRegI;
}
- return minSpillAlias;
-}
+ // No other spill candidates were found, so spill the current VirtReg.
+ DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
+ SmallVector<LiveInterval*, 1> pendingSpills;
-namespace llvm {
-Spiller *createInlineSpiller(MachineFunctionPass &pass,
- MachineFunction &mf,
- VirtRegMap &vrm);
+ spiller().spill(&VirtReg, SplitVRegs, pendingSpills);
+
+ // The live virtual register requesting allocation was spilled, so tell
+ // the caller not to allocate anything during this round.
+ return 0;
}
bool RABasic::runOnMachineFunction(MachineFunction &mf) {
<< "********** Function: "
<< ((Value*)mf.getFunction())->getName() << '\n');
- mf_ = &mf;
- tm_ = &mf.getTarget();
- mri_ = &mf.getRegInfo();
-
- DEBUG(rmf_ = &getAnalysis<RenderMachineFunction>());
-
- RegAllocBase::init(*tm_->getRegisterInfo(), getAnalysis<VirtRegMap>(),
- getAnalysis<LiveIntervals>());
-
- // We may want to force InlineSpiller for this register allocator. For
- // now we're also experimenting with the standard spiller.
- //
- //spiller_.reset(createInlineSpiller(*this, *mf_, *vrm_));
- spiller_.reset(createSpiller(*this, *mf_, *vrm_));
-
+ MF = &mf;
+ DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
+
+ RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
+
+ ReservedRegs = TRI->getReservedRegs(*MF);
+
+ SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
+
allocatePhysRegs();
+ addMBBLiveIns(MF);
+
// Diagnostic output before rewriting
- DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm_ << "\n");
+ DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
// optional HTML output
- DEBUG(rmf_->renderMachineFunction("After basic register allocation.", vrm_));
+ DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
+
+ // FIXME: Verification currently must run before VirtRegRewriter. We should
+ // make the rewriter a separate pass and override verifyAnalysis instead. When
+ // that happens, verification naturally falls under VerifyMachineCode.
+#ifndef NDEBUG
+ if (VerifyRegAlloc) {
+ // Verify accuracy of LiveIntervals. The standard machine code verifier
+ // ensures that each LiveIntervals covers all uses of the virtual reg.
+
+ // FIXME: MachineVerifier is badly broken when using the standard
+ // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
+ // inline spiller, some tests fail to verify because the coalescer does not
+ // always generate verifiable code.
+ MF->verify(this);
+
+ // Verify that LiveIntervals are partitioned into unions and disjoint within
+ // the unions.
+ verify();
+ }
+#endif // !NDEBUG
// Run rewriter
std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
- rewriter->runOnMachineFunction(*mf_, *vrm_, lis_);
+ rewriter->runOnMachineFunction(*MF, *VRM, LIS);
// The pass output is in VirtRegMap. Release all the transient data.
releaseMemory();
-
+
return true;
}
-FunctionPass* llvm::createBasicRegisterAllocator()
+FunctionPass* llvm::createBasicRegisterAllocator()
{
return new RABasic();
}
projects / oota-llvm.git / blobdiff