//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "regalloc"
#include "llvm/CodeGen/Passes.h"
#include "AllocationOrder.h"
#include "LiveDebugVariables.h"
#include "llvm/PassAnalysisSupport.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <cstdlib>
#include <queue>
using namespace llvm;
+#define DEBUG_TYPE "regalloc"
+
static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
createBasicRegisterAllocator);
Spiller &spiller() override { return *SpillerInstance; }
- virtual float getPriority(LiveInterval *LI) { return LI->weight; }
-
void enqueue(LiveInterval *LI) override {
Queue.push(LI);
}
LiveInterval *dequeue() override {
if (Queue.empty())
- return 0;
+ return nullptr;
LiveInterval *LI = Queue.top();
Queue.pop();
return LI;
}
void RABasic::releaseMemory() {
- SpillerInstance.reset(0);
+ SpillerInstance.reset();
}
SmallVector<unsigned, 8> PhysRegSpillCands;
// Check for an available register in this class.
- AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
+ AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
while (unsigned PhysReg = Order.next()) {
// Check for interference in PhysReg
switch (Matrix->checkInterference(VirtReg, PhysReg)) {
getAnalysis<LiveIntervals>(),
getAnalysis<LiveRegMatrix>());
- calculateSpillWeightsAndHints(*LIS, *MF,
+ calculateSpillWeightsAndHints(*LIS, *MF, VRM,
getAnalysis<MachineLoopInfo>(),
getAnalysis<MachineBlockFrequencyInfo>());