//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/ADT/STLExtras.h"
#include <climits>
using namespace llvm;
namespace {
struct VISIBILITY_HIDDEN PEI : public MachineFunctionPass {
+ static char ID;
+ PEI() : MachineFunctionPass((intptr_t)&ID) {}
+
const char *getPassName() const {
return "Prolog/Epilog Insertion & Frame Finalization";
}
// Get MachineModuleInfo so that we can track the construction of the
// frame.
- if (MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>()) {
+ if (MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>())
Fn.getFrameInfo()->setMachineModuleInfo(MMI);
- }
// Allow the target machine to make some adjustments to the function
// e.g. UsedPhysRegs before calculateCalleeSavedRegisters.
void replaceFrameIndices(MachineFunction &Fn);
void insertPrologEpilogCode(MachineFunction &Fn);
};
+ char PEI::ID = 0;
}
const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
// Get the callee saved register list...
- const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
+ const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(&Fn);
// Get the function call frame set-up and tear-down instruction opcode
int FrameSetupOpcode = RegInfo->getCallFrameSetupOpcode();
I->getOpcode() == FrameDestroyOpcode) {
assert(I->getNumOperands() >= 1 && "Call Frame Setup/Destroy Pseudo"
" instructions should have a single immediate argument!");
- unsigned Size = I->getOperand(0).getImmedValue();
+ unsigned Size = I->getOperand(0).getImm();
if (Size > MaxCallFrameSize) MaxCallFrameSize = Size;
HasCalls = true;
FrameSDOps.push_back(I);
MachineFrameInfo *FFI = Fn.getFrameInfo();
FFI->setHasCalls(HasCalls);
FFI->setMaxCallFrameSize(MaxCallFrameSize);
+
for (unsigned i = 0, e = FrameSDOps.size(); i != e; ++i) {
MachineBasicBlock::iterator I = FrameSDOps[i];
- RegInfo->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I);
+ // If call frames are not being included as part of the stack frame,
+ // and there is no dynamic allocation (therefore referencing frame slots
+ // off sp), leave the pseudo ops alone. We'll eliminate them later.
+ if (RegInfo->hasReservedCallFrame(Fn) || RegInfo->hasFP(Fn))
+ RegInfo->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I);
}
// Now figure out which *callee saved* registers are modified by the current
// function, thus needing to be saved and restored in the prolog/epilog.
//
const TargetRegisterClass* const *CSRegClasses =
- RegInfo->getCalleeSavedRegClasses();
+ RegInfo->getCalleeSavedRegClasses(&Fn);
std::vector<CalleeSavedInfo> CSI;
for (unsigned i = 0; CSRegs[i]; ++i) {
unsigned Reg = CSRegs[i];
- if (Fn.isPhysRegUsed(Reg)) {
+ if (Fn.getRegInfo().isPhysRegUsed(Reg)) {
// If the reg is modified, save it!
CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
} else {
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
*AliasSet; ++AliasSet) { // Check alias registers too.
- if (Fn.isPhysRegUsed(*AliasSet)) {
+ if (Fn.getRegInfo().isPhysRegUsed(*AliasSet)) {
CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
break;
}
if (CSI.empty())
return;
- const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
-
+ const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
+
// Now that we have a stack slot for each register to be saved, insert spill
// code into the entry block.
MachineBasicBlock *MBB = Fn.begin();
MachineBasicBlock::iterator I = MBB->begin();
- if (!RegInfo->spillCalleeSavedRegisters(*MBB, I, CSI)) {
+ if (!TII.spillCalleeSavedRegisters(*MBB, I, CSI)) {
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
// Add the callee-saved register as live-in. It's killed at the spill.
MBB->addLiveIn(CSI[i].getReg());
// Insert the spill to the stack frame.
- RegInfo->storeRegToStackSlot(*MBB, I, CSI[i].getReg(),
+ TII.storeRegToStackSlot(*MBB, I, CSI[i].getReg(), true,
CSI[i].getFrameIdx(), CSI[i].getRegClass());
}
}
// Add code to restore the callee-save registers in each exiting block.
- const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
// If last instruction is a return instruction, add an epilogue.
if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
// Skip over all terminator instructions, which are part of the return
// sequence.
MachineBasicBlock::iterator I2 = I;
- while (I2 != MBB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
+ while (I2 != MBB->begin() && (--I2)->getDesc()->isTerminator())
I = I2;
bool AtStart = I == MBB->begin();
// Restore all registers immediately before the return and any terminators
// that preceed it.
- if (!RegInfo->restoreCalleeSavedRegisters(*MBB, I, CSI)) {
+ if (!TII.restoreCalleeSavedRegisters(*MBB, I, CSI)) {
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
- RegInfo->loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
+ TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
CSI[i].getFrameIdx(),
CSI[i].getRegClass());
assert(I != MBB->begin() &&
// Make sure the special register scavenging spill slot is closest to the
// stack pointer.
- if (RS) {
+ if (RS && !RegInfo->hasFP(Fn)) {
int SFI = RS->getScavengingFrameIndex();
if (SFI >= 0) {
// If stack grows down, we need to add size of find the lowest
const TargetMachine &TM = Fn.getTarget();
assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
const MRegisterInfo &MRI = *TM.getRegisterInfo();
+ const TargetFrameInfo *TFI = TM.getFrameInfo();
+ bool StackGrowsDown =
+ TFI->getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
+ int FrameSetupOpcode = MRI.getCallFrameSetupOpcode();
+ int FrameDestroyOpcode = MRI.getCallFrameDestroyOpcode();
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
+ int SPAdj = 0; // SP offset due to call frame setup / destroy.
if (RS) RS->enterBasicBlock(BB);
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) {
- MachineInstr *MI = I++;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).isFrameIndex()) {
- // If this instruction has a FrameIndex operand, we need to use that
- // target machine register info object to eliminate it.
- MRI.eliminateFrameIndex(MI, RS);
-
- // Revisit the instruction in full. Some instructions (e.g. inline
- // asm instructions) can have multiple frame indices.
- --I;
- MI = 0;
- break;
- }
+ MachineInstr *MI = I;
+
+ // Remember how much SP has been adjustment to create the call frame.
+ if (I->getOpcode() == FrameSetupOpcode ||
+ I->getOpcode() == FrameDestroyOpcode) {
+ int Size = I->getOperand(0).getImm();
+ if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) ||
+ (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode))
+ Size = -Size;
+ SPAdj += Size;
+ MachineBasicBlock::iterator PrevI = prior(I);
+ MRI.eliminateCallFramePseudoInstr(Fn, *BB, I);
+ // Visit the instructions created by eliminateCallFramePseudoInstr().
+ I = next(PrevI);
+ MI = NULL;
+ } else {
+ I++;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
+ if (MI->getOperand(i).isFrameIndex()) {
+ // If this instruction has a FrameIndex operand, we need to use that
+ // target machine register info object to eliminate it.
+ MRI.eliminateFrameIndex(MI, SPAdj, RS);
+
+ // Revisit the instruction in full. Some instructions (e.g. inline
+ // asm instructions) can have multiple frame indices.
+ --I;
+ MI = 0;
+ break;
+ }
+ }
// Update register states.
if (RS && MI) RS->forward(MI);
}
+ assert(SPAdj == 0 && "Unbalanced call frame setup / destroy pairs?");
}
}
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