#include "llvm/CodeGen/Passes.h"
#include "llvm/Analysis/BasicAliasAnalysis.h"
+#include "llvm/Analysis/CFLAliasAnalysis.h"
#include "llvm/Analysis/Passes.h"
+#include "llvm/Analysis/ScopedNoAliasAA.h"
+#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/IR/IRPrintingPasses.h"
cl::desc("Disable Machine LICM"));
static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
cl::desc("Disable Machine Common Subexpression Elimination"));
-static cl::opt<cl::boolOrDefault>
- EnableShrinkWrapOpt("enable-shrink-wrap", cl::Hidden,
- cl::desc("enable the shrink-wrapping pass"));
static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
"optimize-regalloc", cl::Hidden,
cl::desc("Enable optimized register allocation compilation path."));
// Temporary option to allow experimenting with MachineScheduler as a post-RA
// scheduler. Targets can "properly" enable this with
-// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); Ideally it
-// wouldn't be part of the standard pass pipeline, and the target would just add
-// a PostRA scheduling pass wherever it wants.
-static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
+// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
+// Targets can return true in targetSchedulesPostRAScheduling() and
+// insert a PostRA scheduling pass wherever it wants.
+cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
// Experimental option to run live interval analysis early.
char TargetPassConfig::EarlyTailDuplicateID = 0;
char TargetPassConfig::PostRAMachineLICMID = 0;
+namespace {
+struct InsertedPass {
+ AnalysisID TargetPassID;
+ IdentifyingPassPtr InsertedPassID;
+ bool VerifyAfter;
+ bool PrintAfter;
+
+ InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
+ bool VerifyAfter, bool PrintAfter)
+ : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
+ VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
+
+ Pass *getInsertedPass() const {
+ assert(InsertedPassID.isValid() && "Illegal Pass ID!");
+ if (InsertedPassID.isInstance())
+ return InsertedPassID.getInstance();
+ Pass *NP = Pass::createPass(InsertedPassID.getID());
+ assert(NP && "Pass ID not registered");
+ return NP;
+ }
+};
+}
+
namespace llvm {
class PassConfigImpl {
public:
/// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
/// is inserted after each instance of the first one.
- SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses;
+ SmallVector<InsertedPass, 4> InsertedPasses;
};
} // namespace llvm
: ImmutablePass(ID), PM(&pm), StartBefore(nullptr), StartAfter(nullptr),
StopAfter(nullptr), Started(true), Stopped(false),
AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false),
- DisableVerify(false), EnableTailMerge(true), EnableShrinkWrap(false) {
+ DisableVerify(false), EnableTailMerge(true) {
Impl = new PassConfigImpl();
// including this pass itself.
initializeCodeGen(*PassRegistry::getPassRegistry());
+ // Also register alias analysis passes required by codegen passes.
+ initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
+ initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
+
// Substitute Pseudo Pass IDs for real ones.
substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
substitutePass(&PostRAMachineLICMID, &MachineLICMID);
/// Insert InsertedPassID pass after TargetPassID.
void TargetPassConfig::insertPass(AnalysisID TargetPassID,
- IdentifyingPassPtr InsertedPassID) {
+ IdentifyingPassPtr InsertedPassID,
+ bool VerifyAfter, bool PrintAfter) {
assert(((!InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getID()) ||
(InsertedPassID.isInstance() &&
TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
"Insert a pass after itself!");
- std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
- Impl->InsertedPasses.push_back(P);
+ Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
+ PrintAfter);
}
/// createPassConfig - Create a pass configuration object to be used by
}
// Add the passes after the pass P if there is any.
- for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
- I = Impl->InsertedPasses.begin(),
- E = Impl->InsertedPasses.end();
- I != E; ++I) {
- if ((*I).first == PassID) {
- assert((*I).second.isValid() && "Illegal Pass ID!");
- Pass *NP;
- if ((*I).second.isInstance())
- NP = (*I).second.getInstance();
- else {
- NP = Pass::createPass((*I).second.getID());
- assert(NP && "Pass ID not registered");
- }
- addPass(NP, false, false);
- }
+ for (auto IP : Impl->InsertedPasses) {
+ if (IP.TargetPassID == PassID)
+ addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
}
} else {
delete P;
// BasicAliasAnalysis wins if they disagree. This is intended to help
// support "obvious" type-punning idioms.
if (UseCFLAA)
- addPass(createCFLAliasAnalysisPass());
- addPass(createTypeBasedAliasAnalysisPass());
- addPass(createScopedNoAliasAAPass());
- addPass(createBasicAliasAnalysisPass());
+ addPass(createCFLAAWrapperPass());
+ addPass(createTypeBasedAAWrapperPass());
+ addPass(createScopedNoAliasAAWrapperPass());
+ addPass(createBasicAAWrapperPass());
// Before running any passes, run the verifier to determine if the input
// coming from the front-end and/or optimizer is valid.
// Add both the safe stack and the stack protection passes: each of them will
// only protect functions that have corresponding attributes.
- addPass(createSafeStackPass());
+ addPass(createSafeStackPass(TM));
addPass(createStackProtectorPass(TM));
if (PrintISelInput)
addPostRegAlloc();
// Insert prolog/epilog code. Eliminate abstract frame index references...
- if (getEnableShrinkWrap())
+ if (getOptLevel() != CodeGenOpt::None)
addPass(&ShrinkWrapID);
+
addPass(&PrologEpilogCodeInserterID);
/// Add passes that optimize machine instructions after register allocation.
addPass(&ImplicitNullChecksID);
// Second pass scheduler.
- if (getOptLevel() != CodeGenOpt::None) {
+ // Let Target optionally insert this pass by itself at some other
+ // point.
+ if (getOptLevel() != CodeGenOpt::None &&
+ !TM->targetSchedulesPostRAScheduling()) {
if (MISchedPostRA)
addPass(&PostMachineSchedulerID);
else
addPreEmitPass();
+ addPass(&FuncletLayoutID, false);
+
addPass(&StackMapLivenessID, false);
+ addPass(&LiveDebugValuesID, false);
AddingMachinePasses = false;
}
addPass(&MachineCSEID, false);
addPass(&MachineSinkingID);
- addPass(&PeepholeOptimizerID, false);
+ addPass(&PeepholeOptimizerID);
// Clean-up the dead code that may have been generated by peephole
// rewriting.
addPass(&DeadMachineInstructionElimID);
}
-bool TargetPassConfig::getEnableShrinkWrap() const {
- switch (EnableShrinkWrapOpt) {
- case cl::BOU_UNSET:
- return EnableShrinkWrap && getOptLevel() != CodeGenOpt::None;
- // If EnableShrinkWrap is set, it takes precedence on whatever the
- // target sets. The rational is that we assume we want to test
- // something related to shrink-wrapping.
- case cl::BOU_TRUE:
- return true;
- case cl::BOU_FALSE:
- return false;
- }
- llvm_unreachable("Invalid shrink-wrapping state");
-}
-
//===---------------------------------------------------------------------===//
/// Register Allocation Pass Configuration
//===---------------------------------------------------------------------===//
addPass(&PHIEliminationID, false);
addPass(&TwoAddressInstructionPassID, false);
- addPass(RegAllocPass);
+ if (RegAllocPass)
+ addPass(RegAllocPass);
}
/// Add standard target-independent passes that are tightly coupled with
// PreRA instruction scheduling.
addPass(&MachineSchedulerID);
- // Add the selected register allocation pass.
- addPass(RegAllocPass);
+ if (RegAllocPass) {
+ // Add the selected register allocation pass.
+ addPass(RegAllocPass);
- // Allow targets to change the register assignments before rewriting.
- addPreRewrite();
+ // Allow targets to change the register assignments before rewriting.
+ addPreRewrite();
- // Finally rewrite virtual registers.
- addPass(&VirtRegRewriterID);
+ // Finally rewrite virtual registers.
+ addPass(&VirtRegRewriterID);
- // Perform stack slot coloring and post-ra machine LICM.
- //
- // FIXME: Re-enable coloring with register when it's capable of adding
- // kill markers.
- addPass(&StackSlotColoringID);
+ // Perform stack slot coloring and post-ra machine LICM.
+ //
+ // FIXME: Re-enable coloring with register when it's capable of adding
+ // kill markers.
+ addPass(&StackSlotColoringID);
- // Run post-ra machine LICM to hoist reloads / remats.
- //
- // FIXME: can this move into MachineLateOptimization?
- addPass(&PostRAMachineLICMID);
+ // Run post-ra machine LICM to hoist reloads / remats.
+ //
+ // FIXME: can this move into MachineLateOptimization?
+ addPass(&PostRAMachineLICMID);
+ }
}
//===---------------------------------------------------------------------===//
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