Correctly extract the ValueType from a VTSDNode.

[oota-llvm.git] / lib / CodeGen / PHIElimination.cpp

diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index ea26bef65aeb3d697d6b8f5d9241cb00240a960a..ffec6ca6d78ce8d70dff0cc3a57f83f6e93f995f 100644 (file)
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -13,6 +13,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#define DEBUG_TYPE "phielim"
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
@@ -20,7 +21,6 @@
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Support/Compiler.h"
@@ -28,11 +28,14 @@
 #include <algorithm>
 using namespace llvm;
 
+STATISTIC(NumAtomic, "Number of atomic phis lowered");
+//STATISTIC(NumSimple, "Number of simple phis lowered");
+
 namespace {
-  static Statistic<> NumAtomic("phielim", "Number of atomic phis lowered");
-  static Statistic<> NumSimple("phielim", "Number of simple phis lowered");
-  
   struct VISIBILITY_HIDDEN PNE : public MachineFunctionPass {
+    static char ID; // Pass identification, replacement for typeid
+    PNE() : MachineFunctionPass((intptr_t)&ID) {}
+
     bool runOnMachineFunction(MachineFunction &Fn) {
       analyzePHINodes(Fn);
 
@@ -64,7 +67,7 @@ namespace {
     /// register which is used in a PHI node. We map that to the BB the
     /// vreg is coming from. This is used later to determine when the vreg
     /// is killed in the BB.
-    /// 
+    ///
     void analyzePHINodes(const MachineFunction& Fn);
 
     typedef std::pair<const MachineBasicBlock*, unsigned> BBVRegPair;
@@ -73,6 +76,7 @@ namespace {
     VRegPHIUse VRegPHIUseCount;
   };
 
+  char PNE::ID = 0;
   RegisterPass<PNE> X("phi-node-elimination",
                       "Eliminate PHI nodes for register allocation");
 }
@@ -121,7 +125,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
 
   unsigned DestReg = MPhi->getOperand(0).getReg();
 
-  // Create a new register for the incoming PHI arguments/
+  // Create a new register for the incoming PHI arguments.
   MachineFunction &MF = *MBB.getParent();
   const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
   unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC);
@@ -131,13 +135,16 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
   // into the phi node destination.
   //
   const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
-  RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
+  RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
 
   // Update live variable information if there is any...
   LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
   if (LV) {
     MachineInstr *PHICopy = prior(AfterPHIsIt);
 
+    // Increment use count of the newly created virtual register.
+    LV->getVarInfo(IncomingReg).NumUses++;
+
     // Add information to LiveVariables to know that the incoming value is
     // killed.  Note that because the value is defined in several places (once
     // each for each incoming block), the "def" block and instruction fields
@@ -164,11 +171,10 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
 
   // Adjust the VRegPHIUseCount map to account for the removal of this PHI
   // node.
-  unsigned NumPreds = (MPhi->getNumOperands()-1)/2;
   for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
-    VRegPHIUseCount[BBVRegPair(
-                      MPhi->getOperand(i + 1).getMachineBasicBlock(),
-                      MPhi->getOperand(i).getReg())] -= NumPreds;
+    --VRegPHIUseCount[BBVRegPair(
+                        MPhi->getOperand(i + 1).getMachineBasicBlock(),
+                        MPhi->getOperand(i).getReg())];
 
   // Now loop over all of the incoming arguments, changing them to copy into
   // the IncomingReg register in the corresponding predecessor basic block.
@@ -194,7 +200,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
     MachineBasicBlock::iterator I = opBlock.getFirstTerminator();
     
     // Insert the copy.
-    RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC);
+    RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC);
 
     // Now update live variable information if we have it.  Otherwise we're done
     if (!LV) continue;
@@ -220,10 +226,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
     //
 
     // Is it used by any PHI instructions in this block?
-    bool ValueIsLive = 
-      VRegPHIUseCount[BBVRegPair(
-                        MPhi->getOperand(i).getMachineBasicBlock(),
-                        SrcReg)] != 0;
+    bool ValueIsLive = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0;
 
     std::vector<MachineBasicBlock*> OpSuccBlocks;
     
@@ -326,14 +329,14 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
 /// particular, we want to map the number of uses of a virtual register which is
 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
 /// used later to determine when the vreg is killed in the BB.
-/// 
+///
 void PNE::analyzePHINodes(const MachineFunction& Fn) {
   for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
        I != E; ++I)
     for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
          BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
       for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
-        VRegPHIUseCount[BBVRegPair(
-                          BBI->getOperand(i + 1).getMachineBasicBlock(),
-                          BBI->getOperand(i).getReg())]++;
+        ++VRegPHIUseCount[BBVRegPair(
+                            BBI->getOperand(i + 1).getMachineBasicBlock(),
+                            BBI->getOperand(i).getReg())];
 }