}
#endif
VRegInfo.clear();
+ for (auto &I : LiveIns)
+ I.second = 0;
}
void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
}
}
-unsigned MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const
-{
+LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const {
// Lane masks are only defined for vregs.
assert(TargetRegisterInfo::isVirtualRegister(Reg));
const TargetRegisterClass &TRC = *getRegClass(Reg);
if (MF.getFunction()->hasFnAttribute(Attribute::UWTable))
return false;
const Function *Called = getCalledFunction(MI);
- if (Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn)
- || !Called->hasFnAttribute(Attribute::NoUnwind))
- return false;
-
- return true;
+ return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
+ !Called->hasFnAttribute(Attribute::NoUnwind));
}
bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg) const {
}
return false;
}
+
+bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
+ if (UsedPhysRegMask.test(PhysReg))
+ return true;
+ const TargetRegisterInfo *TRI = getTargetRegisterInfo();
+ for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
+ ++AliasReg) {
+ if (!reg_nodbg_empty(*AliasReg))
+ return true;
+ }
+ return false;
+}