#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Config/alloca.h"
#include <algorithm>
using namespace llvm;
+char LiveVariables::ID = 0;
static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
void LiveVariables::VarInfo::dump() const {
cerr << " Alive in blocks: ";
for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
if (AliveBlocks[i]) cerr << i << ", ";
+ cerr << " Used in blocks: ";
+ for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i)
+ if (UsedBlocks[i]) cerr << i << ", ";
cerr << "\n Killed by:";
if (Kills.empty())
cerr << " No instructions.\n";
else
VirtRegInfo.resize(2*VirtRegInfo.size());
}
- return VirtRegInfo[RegIdx];
-}
-
-/// registerOverlap - Returns true if register 1 is equal to register 2
-/// or if register 1 is equal to any of alias of register 2.
-static bool registerOverlap(unsigned Reg1, unsigned Reg2,
- const MRegisterInfo *RegInfo) {
- bool isVirt1 = MRegisterInfo::isVirtualRegister(Reg1);
- bool isVirt2 = MRegisterInfo::isVirtualRegister(Reg2);
- if (isVirt1 != isVirt2)
- return false;
- if (Reg1 == Reg2)
- return true;
- else if (isVirt1)
- return false;
- for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg2);
- unsigned Alias = *AliasSet; ++AliasSet) {
- if (Reg1 == Alias)
- return true;
- }
- return false;
+ VarInfo &VI = VirtRegInfo[RegIdx];
+ VI.AliveBlocks.resize(MF->getNumBlockIDs());
+ VI.UsedBlocks.resize(MF->getNumBlockIDs());
+ return VI;
}
bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isKill()) {
- if (registerOverlap(Reg, MO.getReg(), RegInfo))
+ if (MO.isRegister() && MO.isKill()) {
+ if ((MO.getReg() == Reg) ||
+ (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ MRegisterInfo::isPhysicalRegister(Reg) &&
+ RegInfo->isSubRegister(MO.getReg(), Reg)))
return true;
}
}
bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead())
- if (registerOverlap(Reg, MO.getReg(), RegInfo))
+ if (MO.isRegister() && MO.isDead()) {
+ if ((MO.getReg() == Reg) ||
+ (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ MRegisterInfo::isPhysicalRegister(Reg) &&
+ RegInfo->isSubRegister(MO.getReg(), Reg)))
return true;
+ }
}
return false;
}
bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef()) {
- if (registerOverlap(Reg, MO.getReg(), RegInfo))
- return true;
- }
+ if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
+ return true;
}
return false;
}
void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
- MachineBasicBlock *MBB) {
+ MachineBasicBlock *MBB,
+ std::vector<MachineBasicBlock*> &WorkList) {
unsigned BBNum = MBB->getNumber();
// Check to see if this basic block is one of the killing blocks. If so,
if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
- if (VRInfo.AliveBlocks.size() <= BBNum)
- VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
-
if (VRInfo.AliveBlocks[BBNum])
return; // We already know the block is live
// Mark the variable known alive in this bb
VRInfo.AliveBlocks[BBNum] = true;
- for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
- E = MBB->pred_end(); PI != E; ++PI)
- MarkVirtRegAliveInBlock(VRInfo, *PI);
+ for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
+ E = MBB->pred_rend(); PI != E; ++PI)
+ WorkList.push_back(*PI);
}
+void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
+ MachineBasicBlock *MBB) {
+ std::vector<MachineBasicBlock*> WorkList;
+ MarkVirtRegAliveInBlock(VRInfo, MBB, WorkList);
+ while (!WorkList.empty()) {
+ MachineBasicBlock *Pred = WorkList.back();
+ WorkList.pop_back();
+ MarkVirtRegAliveInBlock(VRInfo, Pred, WorkList);
+ }
+}
+
+
void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
MachineInstr *MI) {
assert(VRInfo.DefInst && "Register use before def!");
+ unsigned BBNum = MBB->getNumber();
+
+ VRInfo.UsedBlocks[BBNum] = true;
+ VRInfo.NumUses++;
+
// Check to see if this basic block is already a kill block...
if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
// Yes, this register is killed in this basic block already. Increase the
"Should have kill for defblock!");
// Add a new kill entry for this basic block.
- VRInfo.Kills.push_back(MI);
+ // If this virtual register is already marked as alive in this basic block,
+ // that means it is alive in at least one of the successor block, it's not
+ // a kill.
+ if (!VRInfo.AliveBlocks[BBNum])
+ VRInfo.Kills.push_back(MI);
// Update all dominating blocks to mark them known live.
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
MarkVirtRegAliveInBlock(VRInfo, *PI);
}
-void LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
+bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
+ bool AddIfNotFound) {
+ bool Found = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isUse() && MO.getReg() == IncomingReg) {
- MO.setIsKill();
- break;
+ if (MO.isRegister() && MO.isUse()) {
+ unsigned Reg = MO.getReg();
+ if (!Reg)
+ continue;
+ if (Reg == IncomingReg) {
+ MO.setIsKill();
+ Found = true;
+ break;
+ } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
+ MRegisterInfo::isPhysicalRegister(IncomingReg) &&
+ RegInfo->isSuperRegister(IncomingReg, Reg) &&
+ MO.isKill())
+ // A super-register kill already exists.
+ Found = true;
}
}
+
+ // If not found, this means an alias of one of the operand is killed. Add a
+ // new implicit operand if required.
+ if (!Found && AddIfNotFound) {
+ MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
+ return true;
+ }
+ return Found;
}
-void LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
+bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI,
+ bool AddIfNotFound) {
+ bool Found = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef() && MO.getReg() == IncomingReg) {
- MO.setIsDead();
- break;
+ if (MO.isRegister() && MO.isDef()) {
+ unsigned Reg = MO.getReg();
+ if (!Reg)
+ continue;
+ if (Reg == IncomingReg) {
+ MO.setIsDead();
+ Found = true;
+ break;
+ } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
+ MRegisterInfo::isPhysicalRegister(IncomingReg) &&
+ RegInfo->isSuperRegister(IncomingReg, Reg) &&
+ MO.isDead())
+ // There exists a super-register that's marked dead.
+ return true;
}
}
+
+ // If not found, this means an alias of one of the operand is dead. Add a
+ // new implicit operand.
+ if (!Found && AddIfNotFound) {
+ MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/,
+ true/*IsDead*/);
+ return true;
+ }
+ return Found;
}
void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
+ // Turn previous partial def's into read/mod/write.
+ for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
+ MachineInstr *Def = PhysRegPartDef[Reg][i];
+ // First one is just a def. This means the use is reading some undef bits.
+ if (i != 0)
+ Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
+ Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
+ }
+ PhysRegPartDef[Reg].clear();
+
+ // There was an earlier def of a super-register. Add implicit def to that MI.
+ // A: EAX = ...
+ // B: = AX
+ // Add implicit def to A.
+ if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
+ !PhysRegUsed[Reg]) {
+ MachineInstr *Def = PhysRegInfo[Reg];
+ if (!Def->findRegisterDefOperand(Reg))
+ Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
+ }
+
+ // There is a now a proper use, forget about the last partial use.
+ PhysRegPartUse[Reg] = NULL;
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = true;
- for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
- unsigned Alias = *AliasSet; ++AliasSet) {
- PhysRegInfo[Alias] = MI;
- PhysRegUsed[Alias] = true;
+ for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs) {
+ PhysRegInfo[SubReg] = MI;
+ PhysRegUsed[SubReg] = true;
+ }
+
+ for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
+ unsigned SuperReg = *SuperRegs; ++SuperRegs) {
+ // Remember the partial use of this superreg if it was previously defined.
+ bool HasPrevDef = PhysRegInfo[SuperReg] != NULL;
+ if (!HasPrevDef) {
+ for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg);
+ unsigned SSReg = *SSRegs; ++SSRegs) {
+ if (PhysRegInfo[SSReg] != NULL) {
+ HasPrevDef = true;
+ break;
+ }
+ }
+ }
+ if (HasPrevDef) {
+ PhysRegInfo[SuperReg] = MI;
+ PhysRegPartUse[SuperReg] = MI;
+ }
+ }
+}
+
+bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI,
+ SmallSet<unsigned, 4> &SubKills) {
+ for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs) {
+ MachineInstr *LastRef = PhysRegInfo[SubReg];
+ if (LastRef != RefMI ||
+ !HandlePhysRegKill(SubReg, RefMI, SubKills))
+ SubKills.insert(SubReg);
+ }
+
+ if (*RegInfo->getImmediateSubRegisters(Reg) == 0) {
+ // No sub-registers, just check if reg is killed by RefMI.
+ if (PhysRegInfo[Reg] == RefMI)
+ return true;
+ } else if (SubKills.empty())
+ // None of the sub-registers are killed elsewhere...
+ return true;
+ return false;
+}
+
+void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
+ SmallSet<unsigned, 4> &SubKills) {
+ if (SubKills.count(Reg) == 0)
+ addRegisterKilled(Reg, MI, true);
+ else {
+ for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs)
+ addRegisterKills(SubReg, MI, SubKills);
+ }
+}
+
+bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
+ SmallSet<unsigned, 4> SubKills;
+ if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
+ addRegisterKilled(Reg, RefMI, true);
+ return true;
+ } else {
+ // Some sub-registers are killed by another MI.
+ for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs)
+ addRegisterKills(SubReg, RefMI, SubKills);
+ return false;
}
}
void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
// Does this kill a previous version of this register?
- if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
- if (PhysRegUsed[Reg])
- addRegisterKilled(Reg, LastUse);
- else
- addRegisterDead(Reg, LastUse);
+ if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
+ if (PhysRegUsed[Reg]) {
+ if (!HandlePhysRegKill(Reg, LastRef)) {
+ if (PhysRegPartUse[Reg])
+ addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
+ }
+ } else if (PhysRegPartUse[Reg])
+ // Add implicit use / kill to last partial use.
+ addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
+ else if (LastRef != MI)
+ // Defined, but not used. However, watch out for cases where a super-reg
+ // is also defined on the same MI.
+ addRegisterDead(Reg, LastRef);
}
- PhysRegInfo[Reg] = MI;
- PhysRegUsed[Reg] = false;
- for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
- unsigned Alias = *AliasSet; ++AliasSet) {
- if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
- if (PhysRegUsed[Alias])
- addRegisterKilled(Alias, LastUse);
- else
- addRegisterDead(Alias, LastUse);
+ for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs) {
+ if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
+ if (PhysRegUsed[SubReg]) {
+ if (!HandlePhysRegKill(SubReg, LastRef)) {
+ if (PhysRegPartUse[SubReg])
+ addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
+ }
+ } else if (PhysRegPartUse[SubReg])
+ // Add implicit use / kill to last use of a sub-register.
+ addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
+ else if (LastRef != MI)
+ // This must be a def of the subreg on the same MI.
+ addRegisterDead(SubReg, LastRef);
+ }
+ }
+
+ if (MI) {
+ for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
+ unsigned SuperReg = *SuperRegs; ++SuperRegs) {
+ if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
+ // The larger register is previously defined. Now a smaller part is
+ // being re-defined. Treat it as read/mod/write.
+ // EAX =
+ // AX = EAX<imp-use,kill>, EAX<imp-def>
+ MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
+ MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/);
+ PhysRegInfo[SuperReg] = MI;
+ PhysRegUsed[SuperReg] = false;
+ PhysRegPartUse[SuperReg] = NULL;
+ } else {
+ // Remember this partial def.
+ PhysRegPartDef[SuperReg].push_back(MI);
+ }
+ }
+
+ PhysRegInfo[Reg] = MI;
+ PhysRegUsed[Reg] = false;
+ PhysRegPartDef[Reg].clear();
+ PhysRegPartUse[Reg] = NULL;
+ for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs) {
+ PhysRegInfo[SubReg] = MI;
+ PhysRegUsed[SubReg] = false;
+ PhysRegPartDef[SubReg].clear();
+ PhysRegPartUse[SubReg] = NULL;
}
- PhysRegInfo[Alias] = MI;
- PhysRegUsed[Alias] = false;
}
}
-bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
- const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
- RegInfo = MF.getTarget().getRegisterInfo();
+bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
+ MF = &mf;
+ const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
+ RegInfo = MF->getTarget().getRegisterInfo();
assert(RegInfo && "Target doesn't have register information?");
- AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF);
+ ReservedRegisters = RegInfo->getReservedRegs(mf);
- // PhysRegInfo - Keep track of which instruction was the last use of a
- // physical register. This is a purely local property, because all physical
- // register references as presumed dead across basic blocks.
- //
- PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
- RegInfo->getNumRegs());
- PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
- std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
+ unsigned NumRegs = RegInfo->getNumRegs();
+ PhysRegInfo = new MachineInstr*[NumRegs];
+ PhysRegUsed = new bool[NumRegs];
+ PhysRegPartUse = new MachineInstr*[NumRegs];
+ PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs];
+ PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
+ std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
+ std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
+ std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
/// Get some space for a respectable number of registers...
VirtRegInfo.resize(64);
- analyzePHINodes(MF);
+ analyzePHINodes(mf);
// Calculate live variable information in depth first order on the CFG of the
// function. This guarantees that we will see the definition of a virtual
// register before its uses due to dominance properties of SSA (except for PHI
// nodes, which are treated as a special case).
//
- MachineBasicBlock *Entry = MF.begin();
- std::set<MachineBasicBlock*> Visited;
- for (df_ext_iterator<MachineBasicBlock*> DFI = df_ext_begin(Entry, Visited),
- E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
+ MachineBasicBlock *Entry = MF->begin();
+ SmallPtrSet<MachineBasicBlock*,16> Visited;
+ for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
+ DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
+ DFI != E; ++DFI) {
MachineBasicBlock *MBB = *DFI;
- // Mark live-in registers as live-in.
- for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
+ // Mark live-in registers as live-in.
+ for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
EE = MBB->livein_end(); II != EE; ++II) {
assert(MRegisterInfo::isPhysicalRegister(*II) &&
"Cannot have a live-in virtual register!");
if (MRegisterInfo::isVirtualRegister(MO.getReg())){
HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- AllocatablePhysicalRegisters[MO.getReg()]) {
+ !ReservedRegisters[MO.getReg()]) {
HandlePhysRegUse(MO.getReg(), MI);
}
}
// Defaults to dead
VRInfo.Kills.push_back(MI);
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- AllocatablePhysicalRegisters[MO.getReg()]) {
+ !ReservedRegisters[MO.getReg()]) {
HandlePhysRegDef(MO.getReg(), MI);
}
}
// bottom of this basic block. We check all of our successor blocks to see
// if they have PHI nodes, and if so, we simulate an assignment at the end
// of the current block.
- if (!PHIVarInfo[MBB].empty()) {
- std::vector<unsigned>& VarInfoVec = PHIVarInfo[MBB];
+ if (!PHIVarInfo[MBB->getNumber()].empty()) {
+ SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
- for (std::vector<unsigned>::iterator I = VarInfoVec.begin(),
+ for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
E = VarInfoVec.end(); I != E; ++I) {
VarInfo& VRInfo = getVarInfo(*I);
assert(VRInfo.DefInst && "Register use before def (or no def)!");
// it as using all of the live-out values in the function.
if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
MachineInstr *Ret = &MBB->back();
- for (MachineFunction::liveout_iterator I = MF.liveout_begin(),
- E = MF.liveout_end(); I != E; ++I) {
+ for (MachineFunction::liveout_iterator I = MF->liveout_begin(),
+ E = MF->liveout_end(); I != E; ++I) {
assert(MRegisterInfo::isPhysicalRegister(*I) &&
"Cannot have a live-in virtual register!");
HandlePhysRegUse(*I, Ret);
// Add live-out registers as implicit uses.
- Ret->addRegOperand(*I, false, true);
+ if (Ret->findRegisterUseOperandIdx(*I) == -1)
+ Ret->addRegOperand(*I, false, true);
}
}
// Loop over PhysRegInfo, killing any registers that are available at the
// end of the basic block. This also resets the PhysRegInfo map.
- for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
+ for (unsigned i = 0; i != NumRegs; ++i)
if (PhysRegInfo[i])
HandlePhysRegDef(i, 0);
+
+ // Clear some states between BB's. These are purely local information.
+ for (unsigned i = 0; i != NumRegs; ++i)
+ PhysRegPartDef[i].clear();
+ std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
+ std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
+ std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
}
// Convert and transfer the dead / killed information we have gathered into
// VirtRegInfo onto MI's.
//
- for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
- for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
+ for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
+ for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
addRegisterDead(i + MRegisterInfo::FirstVirtualRegister,
VirtRegInfo[i].Kills[j]);
// function. If so, it is due to a bug in the instruction selector or some
// other part of the code generator if this happens.
#ifndef NDEBUG
- for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
+ for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
assert(Visited.count(&*i) != 0 && "unreachable basic block found");
#endif
- PHIVarInfo.clear();
+ delete[] PhysRegInfo;
+ delete[] PhysRegUsed;
+ delete[] PhysRegPartUse;
+ delete[] PhysRegPartDef;
+ delete[] PHIVarInfo;
+
return false;
}
if (VI.DefInst == OldMI)
VI.DefInst = NewMI;
}
- if (MO.isUse()) {
- if (MO.isKill()) {
- MO.unsetIsKill();
- addVirtualRegisterKilled(Reg, NewMI);
- }
- // If this is a kill of the value, update the VI kills list.
- if (VI.removeKill(OldMI))
- VI.Kills.push_back(NewMI); // Yes, there was a kill of it
+ if (MO.isKill()) {
+ MO.unsetIsKill();
+ addVirtualRegisterKilled(Reg, NewMI);
}
+ // If this is a kill of the value, update the VI kills list.
+ if (VI.removeKill(OldMI))
+ VI.Kills.push_back(NewMI); // Yes, there was a kill of it
}
}
}
void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isKill()) {
+ if (MO.isRegister() && MO.isKill()) {
MO.unsetIsKill();
unsigned Reg = MO.getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead()) {
+ if (MO.isRegister() && MO.isDead()) {
MO.unsetIsDead();
unsigned Reg = MO.getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
- PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()].
+ PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()].
push_back(BBI->getOperand(i).getReg());
}
projects / oota-llvm.git / blobdiff