#define DEBUG_TYPE "regalloc"
+void LiveRangeCalc::resetLiveOutMap() {
+ unsigned NumBlocks = MF->getNumBlockIDs();
+ Seen.clear();
+ Seen.resize(NumBlocks);
+ Map.resize(NumBlocks);
+}
+
void LiveRangeCalc::reset(const MachineFunction *mf,
SlotIndexes *SI,
MachineDominatorTree *MDT,
Indexes = SI;
DomTree = MDT;
Alloc = VNIA;
-
- unsigned NumBlocks = MF->getNumBlockIDs();
- Seen.clear();
- Seen.resize(NumBlocks);
- Map.resize(NumBlocks);
+ resetLiveOutMap();
+ LiveIn.clear();
}
static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc,
LiveRange &LR, const MachineOperand &MO) {
const MachineInstr *MI = MO.getParent();
- SlotIndex DefIdx;
- if (MI->isPHI()) {
- DefIdx = Indexes.getMBBStartIdx(MI->getParent());
- } else {
- DefIdx = Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
- }
+ SlotIndex DefIdx =
+ Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
+
// Create the def in LR. This may find an existing def.
LR.createDeadDef(DefIdx, Alloc);
}
-void LiveRangeCalc::calculate(LiveInterval &LI) {
+void LiveRangeCalc::calculate(LiveInterval &LI, bool TrackSubRegs) {
assert(MRI && Indexes && "call reset() first");
// Step 1: Create minimal live segments for every definition of Reg.
// Visit all def operands. If the same instruction has multiple defs of Reg,
- // LR.createDeadDef() will deduplicate.
+ // createDeadDef() will deduplicate.
const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
unsigned Reg = LI.reg;
for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
+ if (!MO.isDef() && !MO.readsReg())
+ continue;
+
unsigned SubReg = MO.getSubReg();
- if (LI.hasSubRanges() || (SubReg != 0 && MRI->tracksSubRegLiveness())) {
- unsigned Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
- : MRI->getMaxLaneMaskForVReg(Reg);
+ if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
+ LaneBitmask Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
+ : MRI->getMaxLaneMaskForVReg(Reg);
// If this is the first time we see a subregister def, initialize
// subranges by creating a copy of the main range.
if (!LI.hasSubRanges() && !LI.empty()) {
- unsigned ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
+ LaneBitmask ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
LI.createSubRangeFrom(*Alloc, ClassMask, LI);
}
for (LiveInterval::SubRange &S : LI.subranges()) {
// A Mask for subregs common to the existing subrange and current def.
- unsigned Common = S.LaneMask & Mask;
+ LaneBitmask Common = S.LaneMask & Mask;
if (Common == 0)
continue;
// A Mask for subregs covered by the subrange but not the current def.
- unsigned LRest = S.LaneMask & ~Mask;
+ LaneBitmask LRest = S.LaneMask & ~Mask;
LiveInterval::SubRange *CommonRange;
if (LRest != 0) {
// Split current subrange into Common and LRest ranges.
}
}
- // Create the def in the main liverange.
- if (MO.isDef())
+ // Create the def in the main liverange. We do not have to do this if
+ // subranges are tracked as we recreate the main range later in this case.
+ if (MO.isDef() && !LI.hasSubRanges())
createDeadDef(*Indexes, *Alloc, LI, MO);
}
+ // We may have created empty live ranges for partially undefined uses, we
+ // can't keep them because we won't find defs in them later.
+ LI.removeEmptySubRanges();
+
// Step 2: Extend live segments to all uses, constructing SSA form as
// necessary.
- for (LiveInterval::SubRange &S : LI.subranges()) {
- extendToUses(S, Reg, S.LaneMask);
+ if (LI.hasSubRanges()) {
+ for (LiveInterval::SubRange &S : LI.subranges()) {
+ resetLiveOutMap();
+ extendToUses(S, Reg, S.LaneMask);
+ }
+ LI.clear();
+ LI.constructMainRangeFromSubranges(*Indexes, *Alloc);
+ } else {
+ resetLiveOutMap();
+ extendToUses(LI, Reg, ~0u);
}
- extendToUses(LI, Reg, ~0u);
}
-void LiveRangeCalc::calculate(LiveRange &LR, unsigned Reg, bool IgnoreUses) {
+void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) {
assert(MRI && Indexes && "call reset() first");
- // Step 1: Create minimal live segments for every definition of Reg.
// Visit all def operands. If the same instruction has multiple defs of Reg,
// LR.createDeadDef() will deduplicate.
- for (MachineOperand &MO : MRI->def_operands(Reg)) {
+ for (MachineOperand &MO : MRI->def_operands(Reg))
createDeadDef(*Indexes, *Alloc, LR, MO);
- }
-
- // Step 2: Extend live segments to all uses, constructing SSA form as
- // necessary.
- if (!IgnoreUses)
- extendToUses(LR, Reg, ~0u);
}
-void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg, unsigned Mask) {
- unsigned NumBlocks = MF->getNumBlockIDs();
- Seen.clear();
- Seen.resize(NumBlocks);
- Map.resize(NumBlocks);
-
+void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg,
+ LaneBitmask Mask) {
// Visit all operands that read Reg. This may include partial defs.
const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
// by LiveIntervalAnalysis::addKillFlags().
if (MO.isUse())
MO.setIsKill(false);
- // We are only interested in uses. For the main range this also includes
- // the reads happening on partial register defs.
- if (!MO.isUse() && (!MO.readsReg() || Mask != ~0u))
+ else {
+ // We only care about uses, but on the main range (mask ~0u) this includes
+ // the "virtual" reads happening for subregister defs.
+ if (Mask != ~0u)
+ continue;
+ }
+
+ if (!MO.readsReg())
continue;
unsigned SubReg = MO.getSubReg();
if (SubReg != 0) {
- unsigned SubRegMask = TRI.getSubRegIndexLaneMask(SubReg);
+ LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg);
// Ignore uses not covering the current subrange.
if ((SubRegMask & Mask) == 0)
continue;
- // The create dead-defs logic in calculate() splits subranges as fine as
- // necessary for all uses, so SubRegMask shouldn't be smaller than Mask.
- assert((SubRegMask & ~Mask) == 0);
}
// Determine the actual place of the use.
// Check for early-clobber redefs.
bool isEarlyClobber = false;
unsigned DefIdx;
- if (MO.isDef()) {
+ if (MO.isDef())
isEarlyClobber = MO.isEarlyClobber();
- } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
+ else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
// FIXME: This would be a lot easier if tied early-clobber uses also
// had an early-clobber flag.
isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
}
-void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Kill, unsigned PhysReg) {
- assert(Kill.isValid() && "Invalid SlotIndex");
+void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg) {
+ assert(Use.isValid() && "Invalid SlotIndex");
assert(Indexes && "Missing SlotIndexes");
assert(DomTree && "Missing dominator tree");
- MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill.getPrevSlot());
- assert(KillMBB && "No MBB at Kill");
+ MachineBasicBlock *UseMBB = Indexes->getMBBFromIndex(Use.getPrevSlot());
+ assert(UseMBB && "No MBB at Use");
// Is there a def in the same MBB we can extend?
- if (LR.extendInBlock(Indexes->getMBBStartIdx(KillMBB), Kill))
+ if (LR.extendInBlock(Indexes->getMBBStartIdx(UseMBB), Use))
return;
- // Find the single reaching def, or determine if Kill is jointly dominated by
+ // Find the single reaching def, or determine if Use is jointly dominated by
// multiple values, and we may need to create even more phi-defs to preserve
// VNInfo SSA form. Perform a search for all predecessor blocks where we
// know the dominating VNInfo.
- if (findReachingDefs(LR, *KillMBB, Kill, PhysReg))
+ if (findReachingDefs(LR, *UseMBB, Use, PhysReg))
return;
// When there were multiple different values, we may need new PHIs.
}
-bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &KillMBB,
- SlotIndex Kill, unsigned PhysReg) {
- unsigned KillMBBNum = KillMBB.getNumber();
+bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
+ SlotIndex Use, unsigned PhysReg) {
+ unsigned UseMBBNum = UseMBB.getNumber();
// Block numbers where LR should be live-in.
- SmallVector<unsigned, 16> WorkList(1, KillMBBNum);
+ SmallVector<unsigned, 16> WorkList(1, UseMBBNum);
// Remember if we have seen more than one value.
bool UniqueVNI = true;
#ifndef NDEBUG
if (MBB->pred_empty()) {
MBB->getParent()->verify();
+ errs() << "Use of " << PrintReg(PhysReg)
+ << " does not have a corresponding definition on every path:\n";
+ const MachineInstr *MI = Indexes->getInstructionFromIndex(Use);
+ if (MI != nullptr)
+ errs() << Use << " " << *MI;
llvm_unreachable("Use not jointly dominated by defs.");
}
if (TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
!MBB->isLiveIn(PhysReg)) {
MBB->getParent()->verify();
- errs() << "The register needs to be live in to BB#" << MBB->getNumber()
+ errs() << "The register " << PrintReg(PhysReg)
+ << " needs to be live in to BB#" << MBB->getNumber()
<< ", but is missing from the live-in list.\n";
llvm_unreachable("Invalid global physical register");
}
}
// No, we need a live-in value for Pred as well
- if (Pred != &KillMBB)
+ if (Pred != &UseMBB)
WorkList.push_back(Pred->getNumber());
else
- // Loopback to KillMBB, so value is really live through.
- Kill = SlotIndex();
+ // Loopback to UseMBB, so value is really live through.
+ Use = SlotIndex();
}
}
E = WorkList.end(); I != E; ++I) {
SlotIndex Start, End;
std::tie(Start, End) = Indexes->getMBBRange(*I);
- // Trim the live range in KillMBB.
- if (*I == KillMBBNum && Kill.isValid())
- End = Kill;
+ // Trim the live range in UseMBB.
+ if (*I == UseMBBNum && Use.isValid())
+ End = Use;
else
Map[MF->getBlockNumbered(*I)] = LiveOutPair(TheVNI, nullptr);
Updater.add(Start, End, TheVNI);
I = WorkList.begin(), E = WorkList.end(); I != E; ++I) {
MachineBasicBlock *MBB = MF->getBlockNumbered(*I);
addLiveInBlock(LR, DomTree->getNode(MBB));
- if (MBB == &KillMBB)
- LiveIn.back().Kill = Kill;
+ if (MBB == &UseMBB)
+ LiveIn.back().Kill = Use;
}
return false;
projects / oota-llvm.git / blobdiff