#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/FormattedStream.h"
using namespace llvm;
+namespace llvm {
+ bool EnableFastISel;
+}
+
static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
cl::desc("Print LLVM IR produced by the loop-reduce pass"));
static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
cl::desc("Dump emitter generated instructions as assembly"));
static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
cl::desc("Dump garbage collector data"));
-
-// Hidden options to help debugging
-static cl::opt<bool>
-EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
- cl::desc("Perform sinking on machine code"));
-static cl::opt<bool>
-EnableLICM("machine-licm",
- cl::init(false), cl::Hidden,
- cl::desc("Perform loop-invariant code motion on machine code"));
+static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
+ cl::desc("Verify generated machine code"),
+ cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
// When this works it will be on by default.
static cl::opt<bool>
cl::desc("Disable scheduling after register allocation"),
cl::init(true));
+// Enable or disable FastISel. Both options are needed, because
+// FastISel is enabled by default with -fast, and we wish to be
+// able to enable or disable fast-isel independently from -fast.
+static cl::opt<cl::boolOrDefault>
+EnableFastISelOption("fast-isel", cl::Hidden,
+ cl::desc("Enable the experimental \"fast\" instruction selector"));
+
FileModel::Model
LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
- raw_ostream &Out,
+ formatted_raw_ostream &Out,
CodeGenFileType FileType,
- bool Fast) {
- // Standard LLVM-Level Passes.
-
- // Run loop strength reduction before anything else.
- if (!Fast) {
- PM.add(createLoopStrengthReducePass(getTargetLowering()));
- if (PrintLSR)
- PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
- }
-
- PM.add(createGCLoweringPass());
-
- if (!getTargetAsmInfo()->doesSupportExceptionHandling())
- PM.add(createLowerInvokePass(getTargetLowering()));
-
- // Make sure that no unreachable blocks are instruction selected.
- PM.add(createUnreachableBlockEliminationPass());
-
- if (!Fast)
- PM.add(createCodeGenPreparePass(getTargetLowering()));
-
- if (PrintISelInput)
- PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
- &cerr));
-
- // Ask the target for an isel.
- if (addInstSelector(PM, Fast))
+ CodeGenOpt::Level OptLevel) {
+ // Add common CodeGen passes.
+ if (addCommonCodeGenPasses(PM, OptLevel))
return FileModel::Error;
- // Print the instruction selected machine code...
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- if (EnableLICM)
- PM.add(createMachineLICMPass());
-
- if (EnableSinking)
- PM.add(createMachineSinkingPass());
-
- // Run pre-ra passes.
- if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- // Perform register allocation to convert to a concrete x86 representation
- PM.add(createRegisterAllocator());
-
- // Perform stack slot coloring.
- if (!Fast)
- PM.add(createStackSlotColoringPass());
-
- if (PrintMachineCode) // Print the register-allocated code
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- // Run post-ra passes.
- if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- PM.add(createLowerSubregsPass());
-
- if (PrintMachineCode) // Print the subreg lowered code
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- // Insert prolog/epilog code. Eliminate abstract frame index references...
- PM.add(createPrologEpilogCodeInserter());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- // Second pass scheduler.
- if (!Fast && !DisablePostRAScheduler)
- PM.add(createPostRAScheduler());
-
- // Branch folding must be run after regalloc and prolog/epilog insertion.
- if (!Fast)
- PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
-
- PM.add(createGCMachineCodeAnalysisPass());
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- if (PrintGCInfo)
- PM.add(createGCInfoPrinter(*cerr));
-
// Fold redundant debug labels.
PM.add(createDebugLabelFoldingPass());
-
- if (PrintMachineCode) // Print the register-allocated code
+
+ if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
- if (addPreEmitPass(PM, Fast) && PrintMachineCode)
+ if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
- if (!Fast && !OptimizeForSize)
- PM.add(createLoopAlignerPass());
+ if (OptLevel != CodeGenOpt::None)
+ PM.add(createCodePlacementOptPass());
switch (FileType) {
default:
break;
case TargetMachine::AssemblyFile:
- if (addAssemblyEmitter(PM, Fast, Out))
+ if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
return FileModel::Error;
return FileModel::AsmFile;
case TargetMachine::ObjectFile:
return FileModel::Error;
}
-
+
/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
/// be split up (e.g., to add an object writer pass), this method can be used to
/// finish up adding passes to emit the file, if necessary.
bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
MachineCodeEmitter *MCE,
- bool Fast) {
+ CodeGenOpt::Level OptLevel) {
if (MCE)
- addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
-
+ addSimpleCodeEmitter(PM, OptLevel, *MCE);
+ if (PrintEmittedAsm)
+ addAssemblyEmitter(PM, OptLevel, true, ferrs());
+
+ PM.add(createGCInfoDeleter());
+
+ // Delete machine code for this function
+ PM.add(createMachineCodeDeleter());
+
+ return false; // success!
+}
+
+/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
+/// be split up (e.g., to add an object writer pass), this method can be used to
+/// finish up adding passes to emit the file, if necessary.
+bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
+ JITCodeEmitter *JCE,
+ CodeGenOpt::Level OptLevel) {
+ if (JCE)
+ addSimpleCodeEmitter(PM, OptLevel, *JCE);
+ if (PrintEmittedAsm)
+ addAssemblyEmitter(PM, OptLevel, true, ferrs());
+
+ PM.add(createGCInfoDeleter());
+
+ // Delete machine code for this function
+ PM.add(createMachineCodeDeleter());
+
+ return false; // success!
+}
+
+/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
+/// be split up (e.g., to add an object writer pass), this method can be used to
+/// finish up adding passes to emit the file, if necessary.
+bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
+ ObjectCodeEmitter *OCE,
+ CodeGenOpt::Level OptLevel) {
+ if (OCE)
+ addSimpleCodeEmitter(PM, OptLevel, *OCE);
+ if (PrintEmittedAsm)
+ addAssemblyEmitter(PM, OptLevel, true, ferrs());
+
PM.add(createGCInfoDeleter());
// Delete machine code for this function
///
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
MachineCodeEmitter &MCE,
- bool Fast) {
+ CodeGenOpt::Level OptLevel) {
+ // Add common CodeGen passes.
+ if (addCommonCodeGenPasses(PM, OptLevel))
+ return true;
+
+ if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
+ PM.add(createMachineFunctionPrinterPass(cerr));
+
+ addCodeEmitter(PM, OptLevel, MCE);
+ if (PrintEmittedAsm)
+ addAssemblyEmitter(PM, OptLevel, true, ferrs());
+
+ PM.add(createGCInfoDeleter());
+
+ // Delete machine code for this function
+ PM.add(createMachineCodeDeleter());
+
+ return false; // success!
+}
+
+/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
+/// get machine code emitted. This uses a MachineCodeEmitter object to handle
+/// actually outputting the machine code and resolving things like the address
+/// of functions. This method should returns true if machine code emission is
+/// not supported.
+///
+bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
+ JITCodeEmitter &JCE,
+ CodeGenOpt::Level OptLevel) {
+ // Add common CodeGen passes.
+ if (addCommonCodeGenPasses(PM, OptLevel))
+ return true;
+
+ if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
+ PM.add(createMachineFunctionPrinterPass(cerr));
+
+ addCodeEmitter(PM, OptLevel, JCE);
+ if (PrintEmittedAsm)
+ addAssemblyEmitter(PM, OptLevel, true, ferrs());
+
+ PM.add(createGCInfoDeleter());
+
+ // Delete machine code for this function
+ PM.add(createMachineCodeDeleter());
+
+ return false; // success!
+}
+
+static void printAndVerify(PassManagerBase &PM,
+ bool allowDoubleDefs = false) {
+ if (PrintMachineCode)
+ PM.add(createMachineFunctionPrinterPass(cerr));
+
+ if (VerifyMachineCode)
+ PM.add(createMachineVerifierPass(allowDoubleDefs));
+}
+
+/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
+/// emitting to assembly files or machine code output.
+///
+bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Standard LLVM-Level Passes.
-
+
// Run loop strength reduction before anything else.
- if (!Fast) {
+ if (OptLevel != CodeGenOpt::None) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
- PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
+ PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
}
-
- PM.add(createGCLoweringPass());
-
+
+ // Turn exception handling constructs into something the code generators can
+ // handle.
if (!getTargetAsmInfo()->doesSupportExceptionHandling())
PM.add(createLowerInvokePass(getTargetLowering()));
-
+ else
+ PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
+
+ PM.add(createGCLoweringPass());
+
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
- if (!Fast)
+ if (OptLevel != CodeGenOpt::None)
PM.add(createCodeGenPreparePass(getTargetLowering()));
+ PM.add(createStackProtectorPass(getTargetLowering()));
+
if (PrintISelInput)
- PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
- &cerr));
+ PM.add(createPrintFunctionPass("\n\n"
+ "*** Final LLVM Code input to ISel ***\n",
+ &errs()));
+
+ // Standard Lower-Level Passes.
+
+ // Enable FastISel with -fast, but allow that to be overridden.
+ if (EnableFastISelOption == cl::BOU_TRUE ||
+ (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
+ EnableFastISel = true;
// Ask the target for an isel.
- if (addInstSelector(PM, Fast))
+ if (addInstSelector(PM, OptLevel))
return true;
// Print the instruction selected machine code...
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
+ printAndVerify(PM, /* allowDoubleDefs= */ true);
- if (EnableLICM)
+ if (OptLevel != CodeGenOpt::None) {
PM.add(createMachineLICMPass());
-
- if (EnableSinking)
PM.add(createMachineSinkingPass());
+ printAndVerify(PM, /* allowDoubleDefs= */ true);
+ }
// Run pre-ra passes.
- if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
+ if (addPreRegAlloc(PM, OptLevel))
+ printAndVerify(PM);
// Perform register allocation.
PM.add(createRegisterAllocator());
// Perform stack slot coloring.
- if (!Fast)
- PM.add(createStackSlotColoringPass());
+ if (OptLevel != CodeGenOpt::None)
+ PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
+
+ printAndVerify(PM); // Print the register-allocated code
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
// Run post-ra passes.
- if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
+ if (addPostRegAlloc(PM, OptLevel))
+ printAndVerify(PM);
- if (PrintMachineCode) // Print the register-allocated code
- PM.add(createMachineFunctionPrinterPass(cerr));
-
PM.add(createLowerSubregsPass());
-
- if (PrintMachineCode) // Print the subreg lowered code
- PM.add(createMachineFunctionPrinterPass(cerr));
+ printAndVerify(PM);
// Insert prolog/epilog code. Eliminate abstract frame index references...
PM.add(createPrologEpilogCodeInserter());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
+ printAndVerify(PM);
+
// Second pass scheduler.
- if (!Fast)
+ if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
PM.add(createPostRAScheduler());
+ printAndVerify(PM);
+ }
// Branch folding must be run after regalloc and prolog/epilog insertion.
- if (!Fast)
+ if (OptLevel != CodeGenOpt::None) {
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
+ printAndVerify(PM);
+ }
PM.add(createGCMachineCodeAnalysisPass());
+ printAndVerify(PM);
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
if (PrintGCInfo)
PM.add(createGCInfoPrinter(*cerr));
-
- if (addPreEmitPass(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
- addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
-
- PM.add(createGCInfoDeleter());
-
- // Delete machine code for this function
- PM.add(createMachineCodeDeleter());
-
- return false; // success!
+ return false;
}
projects / oota-llvm.git / blobdiff