Untabify.

[oota-llvm.git] / include / llvm / Target / Target.td

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 1ff8db8c2e68aaf994e0d0018bbe15717719801e..4d6958e92a05219c87d6f6e33af56cb542343098 100644 (file)
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -381,6 +381,7 @@ class Instruction {
   bit hasPostISelHook = 0;  // To be *adjusted* after isel by target hook.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?
   bit hasPostISelHook = 0;  // To be *adjusted* after isel by target hook.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?

+  bit isConvergent = 0;     // Is this instruction convergent?

   bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
   bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
   bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
   bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
   bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
   bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?


@@ -506,7 +507,7 @@ class Requires<list<Predicate> preds> {
 
 /// ops definition - This is just a simple marker used to identify the operand
 /// list for an instruction. outs and ins are identical both syntactically and
 
 /// ops definition - This is just a simple marker used to identify the operand
 /// list for an instruction. outs and ins are identical both syntactically and

-/// semanticallyr; they are used to define def operands and use operands to
+/// semantically; they are used to define def operands and use operands to

 /// improve readibility. This should be used like this:
 ///     (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
 def ops;
 /// improve readibility. This should be used like this:
 ///     (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
 def ops;


@@ -880,6 +881,12 @@ def FRAME_ALLOC : Instruction {
   let hasSideEffects = 0;
   let hasCtrlDep = 1;
 }
   let hasSideEffects = 0;
   let hasCtrlDep = 1;
 }

+def FAULTING_LOAD_OP : Instruction {
+  let OutOperandList = (outs unknown:$dst);
+  let InOperandList = (ins variable_ops);
+  let usesCustomInserter = 1;
+  let mayLoad = 1;
+}

 }
 
 //===----------------------------------------------------------------------===//
 }
 
 //===----------------------------------------------------------------------===//


@@ -1006,6 +1013,15 @@ class InstAlias<string Asm, dag Result, int Emit = 1> {
 
   // Predicates - Predicates that must be true for this to match.
   list<Predicate> Predicates = [];
 
   // Predicates - Predicates that must be true for this to match.
   list<Predicate> Predicates = [];

+
+  // If the instruction specified in Result has defined an AsmMatchConverter
+  // then setting this to 1 will cause the alias to use the AsmMatchConverter
+  // function when converting the OperandVector into an MCInst instead of the
+  // function that is generated by the dag Result.
+  // Setting this to 0 will cause the alias to ignore the Result instruction's
+  // defined AsmMatchConverter and instead use the function generated by the
+  // dag Result.
+  bit UseInstAsmMatchConverter = 1;

 }
 
 //===----------------------------------------------------------------------===//
 }
 
 //===----------------------------------------------------------------------===//