[TrailingObjects] Dynamically realign under-aligned trailing objects.

[oota-llvm.git] / include / llvm / Support / ELF.h

diff --git a/include/llvm/Support/ELF.h b/include/llvm/Support/ELF.h
index 3804d2626fc3a401d378ffc1e45b4a93de8b563c..97708a7cdd635de87726102f36158a9d48e2a5df 100644 (file)
--- a/include/llvm/Support/ELF.h
+++ b/include/llvm/Support/ELF.h
@@ -347,6 +347,7 @@ enum {
   ELFOSABI_FENIXOS = 16,      // FenixOS
   ELFOSABI_CLOUDABI = 17,     // Nuxi CloudABI
   ELFOSABI_C6000_ELFABI = 64, // Bare-metal TMS320C6000
+  ELFOSABI_AMDGPU_HSA = 64,   // AMD HSA runtime
   ELFOSABI_C6000_LINUX = 65,  // Linux TMS320C6000
   ELFOSABI_ARM = 97,          // ARM
   ELFOSABI_STANDALONE = 255   // Standalone (embedded) application
@@ -428,6 +429,33 @@ enum {
 #include "ELFRelocs/ARM.def"
 };
 
+// AVR specific e_flags
+enum : unsigned {
+  EF_AVR_ARCH_AVR1    = 1,
+  EF_AVR_ARCH_AVR2    = 2,
+  EF_AVR_ARCH_AVR25   = 25,
+  EF_AVR_ARCH_AVR3    = 3,
+  EF_AVR_ARCH_AVR31   = 31,
+  EF_AVR_ARCH_AVR35   = 35,
+  EF_AVR_ARCH_AVR4    = 4,
+  EF_AVR_ARCH_AVR5    = 5,
+  EF_AVR_ARCH_AVR51   = 51,
+  EF_AVR_ARCH_AVR6    = 6,
+  EF_AVR_ARCH_AVRTINY = 100,
+  EF_AVR_ARCH_XMEGA1  = 101,
+  EF_AVR_ARCH_XMEGA2  = 102,
+  EF_AVR_ARCH_XMEGA3  = 103,
+  EF_AVR_ARCH_XMEGA4  = 104,
+  EF_AVR_ARCH_XMEGA5  = 105,
+  EF_AVR_ARCH_XMEGA6  = 106,
+  EF_AVR_ARCH_XMEGA7  = 107
+};
+
+// ELF Relocation types for AVR
+enum {
+#include "ELFRelocs/AVR.def"
+};
+
 // Mips Specific e_flags
 enum : unsigned {
   EF_MIPS_NOREORDER = 0x00000001, // Don't reorder instructions
@@ -521,26 +549,28 @@ enum {
   ODK_PAGESIZE   = 11   // Page size information
 };
 
-// Hexagon Specific e_flags
-// Release 5 ABI
+// Hexagon-specific e_flags
 enum {
-  // Object processor version flags, bits[3:0]
+  // Object processor version flags, bits[11:0]
   EF_HEXAGON_MACH_V2      = 0x00000001,   // Hexagon V2
   EF_HEXAGON_MACH_V3      = 0x00000002,   // Hexagon V3
   EF_HEXAGON_MACH_V4      = 0x00000003,   // Hexagon V4
   EF_HEXAGON_MACH_V5      = 0x00000004,   // Hexagon V5
+  EF_HEXAGON_MACH_V55     = 0x00000005,   // Hexagon V55
+  EF_HEXAGON_MACH_V60     = 0x00000060,   // Hexagon V60
 
   // Highest ISA version flags
-  EF_HEXAGON_ISA_MACH     = 0x00000000,   // Same as specified in bits[3:0]
+  EF_HEXAGON_ISA_MACH     = 0x00000000,   // Same as specified in bits[11:0]
                                           // of e_flags
   EF_HEXAGON_ISA_V2       = 0x00000010,   // Hexagon V2 ISA
   EF_HEXAGON_ISA_V3       = 0x00000020,   // Hexagon V3 ISA
   EF_HEXAGON_ISA_V4       = 0x00000030,   // Hexagon V4 ISA
-  EF_HEXAGON_ISA_V5       = 0x00000040    // Hexagon V5 ISA
+  EF_HEXAGON_ISA_V5       = 0x00000040,   // Hexagon V5 ISA
+  EF_HEXAGON_ISA_V55      = 0x00000050,   // Hexagon V55 ISA
+  EF_HEXAGON_ISA_V60      = 0x00000060,   // Hexagon V60 ISA
 };
 
-// Hexagon specific Section indexes for common small data
-// Release 5 ABI
+// Hexagon-specific section indexes for common small data
 enum {
   SHN_HEXAGON_SCOMMON     = 0xff00,       // Other access sizes
   SHN_HEXAGON_SCOMMON_1   = 0xff01,       // Byte-sized access
@@ -746,7 +776,12 @@ enum : unsigned {
   SHF_MIPS_ADDR    = 0x40000000,
 
   // Section data is string data by default.
-  SHF_MIPS_STRING  = 0x80000000
+  SHF_MIPS_STRING  = 0x80000000,
+
+  SHF_AMDGPU_HSA_GLOBAL   = 0x00100000,
+  SHF_AMDGPU_HSA_READONLY = 0x00200000,
+  SHF_AMDGPU_HSA_CODE     = 0x00400000,
+  SHF_AMDGPU_HSA_AGENT    = 0x00800000
 };
 
 // Section Group Flags
@@ -827,7 +862,12 @@ enum {
   STT_LOOS    = 10,  // Lowest operating system-specific symbol type
   STT_HIOS    = 12,  // Highest operating system-specific symbol type
   STT_LOPROC  = 13,  // Lowest processor-specific symbol type
-  STT_HIPROC  = 15   // Highest processor-specific symbol type
+  STT_HIPROC  = 15,  // Highest processor-specific symbol type
+
+  // AMDGPU symbol types
+  STT_AMDGPU_HSA_KERNEL            = 10,
+  STT_AMDGPU_HSA_INDIRECT_FUNCTION = 11,
+  STT_AMDGPU_HSA_METADATA          = 12
 };
 
 enum {
@@ -978,7 +1018,13 @@ enum {
   PT_MIPS_REGINFO  = 0x70000000,  // Register usage information.
   PT_MIPS_RTPROC   = 0x70000001,  // Runtime procedure table.
   PT_MIPS_OPTIONS  = 0x70000002,  // Options segment.
-  PT_MIPS_ABIFLAGS = 0x70000003   // Abiflags segment.
+  PT_MIPS_ABIFLAGS = 0x70000003,  // Abiflags segment.
+
+  // AMDGPU program header types.
+  PT_AMDGPU_HSA_LOAD_GLOBAL_PROGRAM = 0x60000000,
+  PT_AMDGPU_HSA_LOAD_GLOBAL_AGENT   = 0x60000001,
+  PT_AMDGPU_HSA_LOAD_READONLY_AGENT = 0x60000002,
+  PT_AMDGPU_HSA_LOAD_CODE_AGENT     = 0x60000003
 };
 
 // Segment flag bits.
@@ -1138,8 +1184,10 @@ enum {
   DT_MIPS_GP_VALUE          = 0x70000030, // GP value for auxiliary GOTs.
   DT_MIPS_AUX_DYNAMIC       = 0x70000031, // Address of auxiliary .dynamic.
   DT_MIPS_PLTGOT            = 0x70000032, // Address of the base of the PLTGOT.
-  DT_MIPS_RWPLT             = 0x70000034  // Points to the base
+  DT_MIPS_RWPLT             = 0x70000034, // Points to the base
                                           // of a writable PLT.
+  DT_MIPS_RLD_MAP_REL       = 0x70000035  // Relative offset of run time loader
+                                          // map, used for debugging.
 };
 
 // DT_FLAGS values.