/// MCSubtargetInfo - Generic base class for all target subtargets.
///
class MCSubtargetInfo {
- std::string TargetTriple; // Target triple
+ Triple TargetTriple; // Target triple
std::string CPU; // CPU being targeted.
ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
FeatureBitset FeatureBits; // Feature bits for current CPU + FS
public:
- void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
+ void InitMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetFeatureKV> PD,
const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
- const MCReadAdvanceEntry *RA,
- const InstrStage *IS,
+ const MCReadAdvanceEntry *RA, const InstrStage *IS,
const unsigned *OC, const unsigned *FP);
/// getTargetTriple - Return the target triple string.
- StringRef getTargetTriple() const {
- return TargetTriple;
- }
+ const Triple &getTargetTriple() const { return TargetTriple; }
/// getCPU - Return the CPU string.
StringRef getCPU() const {
/// feature bits. This version will also change all implied bits.
FeatureBitset ToggleFeature(StringRef FS);
+ /// Apply a feature flag and return the re-computed feature bits, including
+ /// all feature bits implied by the flag.
+ FeatureBitset ApplyFeatureFlag(StringRef FS);
+
/// getSchedModelForCPU - Get the machine model of a CPU.
///
MCSchedModel getSchedModelForCPU(StringRef CPU) const;
}
};
-} // End llvm namespace
+} // namespace llvm
#endif