Fixed/added namespace ending comments using clang-tidy. NFC

[oota-llvm.git] / include / llvm / MC / MCSubtargetInfo.h

diff --git a/include/llvm/MC/MCSubtargetInfo.h b/include/llvm/MC/MCSubtargetInfo.h
index 9d09bd8ed403258cd75df84c1cc495c37ae2cedc..0a23306fa694d6fb48d71fabcc73199d19440417 100644 (file)
--- a/include/llvm/MC/MCSubtargetInfo.h
+++ b/include/llvm/MC/MCSubtargetInfo.h
@@ -27,7 +27,8 @@ class StringRef;
 /// MCSubtargetInfo - Generic base class for all target subtargets.
 ///
 class MCSubtargetInfo {
-  std::string TargetTriple;            // Target triple
+  Triple TargetTriple;                        // Target triple
+  std::string CPU; // CPU being targeted.
   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
   ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
 
@@ -41,33 +42,37 @@ class MCSubtargetInfo {
   const InstrStage *Stages;            // Instruction itinerary stages
   const unsigned *OperandCycles;       // Itinerary operand cycles
   const unsigned *ForwardingPaths;     // Forwarding paths
-  uint64_t FeatureBits;                // Feature bits for current CPU + FS
+  FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
 
 public:
-  void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
+  void InitMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
                            ArrayRef<SubtargetFeatureKV> PF,
                            ArrayRef<SubtargetFeatureKV> PD,
                            const SubtargetInfoKV *ProcSched,
                            const MCWriteProcResEntry *WPR,
                            const MCWriteLatencyEntry *WL,
-                           const MCReadAdvanceEntry *RA,
-                           const InstrStage *IS,
+                           const MCReadAdvanceEntry *RA, const InstrStage *IS,
                            const unsigned *OC, const unsigned *FP);
 
   /// getTargetTriple - Return the target triple string.
-  StringRef getTargetTriple() const {
-    return TargetTriple;
+  const Triple &getTargetTriple() const { return TargetTriple; }
+
+  /// getCPU - Return the CPU string.
+  StringRef getCPU() const {
+    return CPU;
   }
 
   /// getFeatureBits - Return the feature bits.
   ///
-  uint64_t getFeatureBits() const {
+  const FeatureBitset& getFeatureBits() const {
     return FeatureBits;
   }
 
   /// setFeatureBits - Set the feature bits.
   ///
-  void setFeatureBits(uint64_t FeatureBits_) { FeatureBits = FeatureBits_; }
+  void setFeatureBits(const FeatureBitset &FeatureBits_) {
+    FeatureBits = FeatureBits_;
+  }
 
   /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
   /// feature string). Recompute feature bits and scheduling model.
@@ -78,11 +83,19 @@ public:
 
   /// ToggleFeature - Toggle a feature and returns the re-computed feature
   /// bits. This version does not change the implied bits.
-  uint64_t ToggleFeature(uint64_t FB);
+  FeatureBitset ToggleFeature(uint64_t FB);
 
   /// ToggleFeature - Toggle a feature and returns the re-computed feature
-  /// bits. This version will also change all implied bits.
-  uint64_t ToggleFeature(StringRef FS);
+  /// bits. This version does not change the implied bits.
+  FeatureBitset ToggleFeature(const FeatureBitset& FB);
+
+  /// ToggleFeature - Toggle a set of features and returns the re-computed
+  /// feature bits. This version will also change all implied bits.
+  FeatureBitset ToggleFeature(StringRef FS);
+
+  /// Apply a feature flag and return the re-computed feature bits, including
+  /// all feature bits implied by the flag.
+  FeatureBitset ApplyFeatureFlag(StringRef FS);
 
   /// getSchedModelForCPU - Get the machine model of a CPU.
   ///
@@ -136,8 +149,17 @@ public:
 
   /// Initialize an InstrItineraryData instance.
   void initInstrItins(InstrItineraryData &InstrItins) const;
+
+  /// Check whether the CPU string is valid.
+  bool isCPUStringValid(StringRef CPU) {
+    auto Found = std::find_if(ProcDesc.begin(), ProcDesc.end(),
+                              [=](const SubtargetFeatureKV &KV) {
+                                return CPU == KV.Key; 
+                              });
+    return Found != ProcDesc.end();
+  }
 };
 
-} // End llvm namespace
+} // namespace llvm
 
 #endif