#define LLVM_MC_MCREGISTERINFO_H
#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/DenseSet.h"
+#include "llvm/Support/ErrorHandling.h"
#include <cassert>
namespace llvm {
/// MCRegisterClass - Base class of TargetRegisterClass.
class MCRegisterClass {
public:
- typedef const unsigned* iterator;
- typedef const unsigned* const_iterator;
-private:
- unsigned ID;
+ typedef const uint16_t* iterator;
+ typedef const uint16_t* const_iterator;
+
+ const unsigned ID;
const char *Name;
const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
const int CopyCost;
const bool Allocatable;
- const iterator RegsBegin, RegsEnd;
- DenseSet<unsigned> RegSet;
-public:
- MCRegisterClass(unsigned id, const char *name,
- unsigned RS, unsigned Al, int CC, bool Allocable,
- iterator RB, iterator RE)
- : ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
- Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE) {}
-
- /// initMCRegisterClass - Initialize initMCRegisterClass. *DO NOT USE*.
- // FIXME: This could go away if RegSet would use a constant bit field.
- void initMCRegisterClass() {
- RegSet.resize(getNumRegs());
- for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
- RegSet.insert(*I);
- }
+ const iterator RegsBegin;
+ const uint8_t *const RegSet;
+ const unsigned RegsSize;
+ const unsigned RegSetSize;
/// getID() - Return the register class ID number.
///
/// begin/end - Return all of the registers in this class.
///
iterator begin() const { return RegsBegin; }
- iterator end() const { return RegsEnd; }
+ iterator end() const { return RegsBegin + RegsSize; }
/// getNumRegs - Return the number of registers in this class.
///
- unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
+ unsigned getNumRegs() const { return RegsSize; }
/// getRegister - Return the specified register in the class.
///
/// contains - Return true if the specified register is included in this
/// register class. This does not include virtual registers.
bool contains(unsigned Reg) const {
- return RegSet.count(Reg);
+ unsigned InByte = Reg % 8;
+ unsigned Byte = Reg / 8;
+ if (Byte >= RegSetSize)
+ return false;
+ return (RegSet[Byte] & (1 << InByte)) != 0;
}
/// contains - Return true if both registers are in this class.
/// of AX.
///
struct MCRegisterDesc {
- const char *Name; // Printable name for the reg (for debugging)
- const unsigned *Overlaps; // Overlapping registers, described above
- const unsigned *SubRegs; // Sub-register set, described above
- const unsigned *SuperRegs; // Super-register set, described above
+ const char *Name; // Printable name for the reg (for debugging)
+ unsigned Overlaps; // Overlapping registers, described above
+ unsigned SubRegs; // Sub-register set, described above
+ unsigned SuperRegs; // Super-register set, described above
};
/// MCRegisterInfo base class - We assume that the target defines a static
unsigned RAReg; // Return address register
const MCRegisterClass *Classes; // Pointer to the regclass array
unsigned NumClasses; // Number of entries in the array
+ const unsigned *Overlaps; // Pointer to the overlaps array
+ const unsigned *SubRegs; // Pointer to the subregs array
+ const unsigned *SuperRegs; // Pointer to the superregs array
+ const uint16_t *SubRegIndices; // Pointer to the subreg lookup
+ // array.
+ unsigned NumSubRegIndices; // Number of subreg indices.
DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
/// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
/// auto-generated routines. *DO NOT USE*.
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
- MCRegisterClass *C, unsigned NC) {
+ const MCRegisterClass *C, unsigned NC,
+ const unsigned *O, const unsigned *Sub,
+ const unsigned *Super,
+ const uint16_t *SubIndices,
+ unsigned NumIndices) {
Desc = D;
NumRegs = NR;
RAReg = RA;
Classes = C;
+ Overlaps = O;
+ SubRegs = Sub;
+ SuperRegs = Super;
NumClasses = NC;
- // FIXME: This should go away.
- for (unsigned i = 0; i != NC; ++i)
- C[i].initMCRegisterClass();
+ SubRegIndices = SubIndices;
+ NumSubRegIndices = NumIndices;
}
/// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
else
L2DwarfRegs[LLVMReg] = DwarfReg;
}
-
+
/// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
/// register number mapping. Called by TableGen auto-generated routines.
/// *DO NOT USE*.
else
Dwarf2LRegs[DwarfReg] = LLVMReg;
}
-
+
/// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
/// number mapping. By default the SEH register number is just the same
/// as the LLVM register number.
///
const unsigned *getAliasSet(unsigned RegNo) const {
// The Overlaps set always begins with Reg itself.
- return get(RegNo).Overlaps + 1;
+ return Overlaps + get(RegNo).Overlaps + 1;
}
/// getOverlaps - Return a list of registers that overlap Reg, including
/// These are exactly the registers in { x | regsOverlap(x, Reg) }.
///
const unsigned *getOverlaps(unsigned RegNo) const {
- return get(RegNo).Overlaps;
+ return Overlaps + get(RegNo).Overlaps;
}
/// getSubRegisters - Return the list of registers that are sub-registers of
/// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
///
const unsigned *getSubRegisters(unsigned RegNo) const {
- return get(RegNo).SubRegs;
+ return SubRegs + get(RegNo).SubRegs;
+ }
+
+ /// getSubReg - Returns the physical register number of sub-register "Index"
+ /// for physical register RegNo. Return zero if the sub-register does not
+ /// exist.
+ unsigned getSubReg(unsigned Reg, unsigned Idx) const {
+ return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1);
+ }
+
+ /// getSubRegIndex - For a given register pair, return the sub-register index
+ /// if the second register is a sub-register of the first. Return zero
+ /// otherwise.
+ unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {
+ for (unsigned I = 1; I <= NumSubRegIndices; ++I)
+ if (getSubReg(RegNo, I) == SubRegNo)
+ return I;
+ return 0;
}
/// getSuperRegisters - Return the list of registers that are super-registers
/// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
///
const unsigned *getSuperRegisters(unsigned RegNo) const {
- return get(RegNo).SuperRegs;
+ return SuperRegs + get(RegNo).SuperRegs;
}
/// getName - Return the human-readable symbolic target-specific name for the
const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
if (I == M.end()) {
- assert(0 && "Invalid RegNum");
- return -1;
+ llvm_unreachable("Invalid RegNum");
}
return I->second;
}
return Classes[i];
}
};
-
+
} // End llvm namespace
#endif
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