Rename SDOperand to SDValue.

[oota-llvm.git] / include / llvm / CodeGen / SelectionDAGISel.h

diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index e9b3f52ed48d0cda5130decf82bc13b92a2be3b9..c384fa512d140afd6c8f4793355029c8c0b93db9 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -21,7 +21,7 @@
 
 namespace llvm {
   class SelectionDAGLowering;
-  class SDOperand;
+  class SDValue;
   class MachineRegisterInfo;
   class MachineBasicBlock;
   class MachineFunction;
@@ -70,9 +70,9 @@ public:
   /// not match or is not implemented, return true.  The resultant operands
   /// (which will appear in the machine instruction) should be added to the
   /// OutOps vector.
-  virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
                                             char ConstraintCode,
-                                            std::vector<SDOperand> &OutOps,
+                                            std::vector<SDValue> &OutOps,
                                             SelectionDAG &DAG) {
     return true;
   }
@@ -168,13 +168,13 @@ protected:
 
   /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
   /// by tblgen.  Others should not call it.
-  void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
+  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
                                      SelectionDAG &DAG);
 
   // Calls to these predicates are generated by tblgen.
-  bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
+  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
                     int64_t DesiredMaskS) const;
-  bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
+  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
                     int64_t DesiredMaskS) const;
   
 private: