Rename some GC classes so that their roll will hopefully be clearer.

[oota-llvm.git] / include / llvm / CodeGen / SelectionDAGISel.h

diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 3ebe515b38be8d6f36a7fd279245e1e0fe1a48c7..77e75c0d86da3749ea87f0921107af046d774c86 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -18,11 +18,10 @@
 #include "llvm/Pass.h"
 #include "llvm/Constant.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SelectionDAGNodes.h"
 
 namespace llvm {
   class SelectionDAGLowering;
-  class SDOperand;
+  class SDValue;
   class MachineRegisterInfo;
   class MachineBasicBlock;
   class MachineFunction;
@@ -30,7 +29,8 @@ namespace llvm {
   class TargetLowering;
   class FunctionLoweringInfo;
   class HazardRecognizer;
-  class CollectorMetadata;
+  class GCFunctionInfo;
+  class ScheduleDAG;
  
 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
 /// pattern-matching instruction selectors.
@@ -41,14 +41,13 @@ public:
   SelectionDAG *CurDAG;
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
+  GCFunctionInfo *GFI;
+  bool Fast;
   std::vector<SDNode*> TopOrder;
-  unsigned DAGSize;
-  CollectorMetadata *GCI;
-  bool FastISel;
   static char ID;
 
   explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) : 
-    FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0), GCI(0), FastISel(fast) {}
+    FunctionPass((intptr_t)&ID), TLI(tli), GFI(), Fast(fast), DAGSize(0) {}
   
   TargetLowering &getTargetLowering() { return TLI; }
 
@@ -60,7 +59,7 @@ public:
 
   virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
   virtual void InstructionSelect(SelectionDAG &SD) = 0;
-  virtual void InstructionSelectPostProcessing(SelectionDAG &DAG) {}
+  virtual void InstructionSelectPostProcessing() {}
   
   virtual void SelectRootInit() {
     DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
@@ -71,9 +70,9 @@ public:
   /// not match or is not implemented, return true.  The resultant operands
   /// (which will appear in the machine instruction) should be added to the
   /// OutOps vector.
-  virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
                                             char ConstraintCode,
-                                            std::vector<SDOperand> &OutOps,
+                                            std::vector<SDValue> &OutOps,
                                             SelectionDAG &DAG) {
     return true;
   }
@@ -163,32 +162,44 @@ public:
   };
   
 protected:
+  /// DAGSize - Size of DAG being instruction selected.
+  ///
+  unsigned DAGSize;
+
   /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
   /// by tblgen.  Others should not call it.
-  void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
+  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
                                      SelectionDAG &DAG);
 
   // Calls to these predicates are generated by tblgen.
-  bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
+  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
                     int64_t DesiredMaskS) const;
-  bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
+  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
                     int64_t DesiredMaskS) const;
   
 private:
+  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
+                            FunctionLoweringInfo &FuncInfo);
   void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
-                        FunctionLoweringInfo &FuncInfo);
+                        FunctionLoweringInfo &FuncInfo,
+             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
+                        NodeAllocatorType &NodeAllocator);
+  void FinishBasicBlock(BasicBlock *BB, MachineFunction &MF,
+                        FunctionLoweringInfo &FuncInfo,
+             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
+                        NodeAllocatorType &NodeAllocator);
 
   void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
-           std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
+             std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
                          FunctionLoweringInfo &FuncInfo);
   void CodeGenAndEmitDAG(SelectionDAG &DAG);
   void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL);
   
   void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
 
-  /// Pick a safe ordering and emit instructions for each target node in the
+  /// Pick a safe ordering for instructions for each target node in the
   /// graph.
-  void ScheduleAndEmitDAG(SelectionDAG &DAG);
+  ScheduleDAG *Schedule(SelectionDAG &DAG);
 
   /// SwitchCases - Vector of CaseBlock structures used to communicate
   /// SwitchInst code generation information.