//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#ifndef LLVM_CODEGEN_MACHINEINSTR_H
#define LLVM_CODEGEN_MACHINEINSTR_H
-#include "llvm/ADT/iterator"
-#include "llvm/Support/DataTypes.h"
-#include "llvm/Support/Streams.h"
+#include "llvm/ADT/ilist.h"
+#include "llvm/ADT/ilist_node.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/Target/TargetInstrDesc.h"
+#include "llvm/Target/TargetOpcodes.h"
+#include "llvm/Support/DebugLoc.h"
#include <vector>
-#include <cassert>
-#include <iosfwd>
namespace llvm {
-class Value;
-class Function;
-class MachineBasicBlock;
-class TargetInstrDescriptor;
-class TargetMachine;
-class GlobalValue;
-
-template <typename T> struct ilist_traits;
-template <typename T> struct ilist;
-
-//===----------------------------------------------------------------------===//
-// class MachineOperand
-//
-// Representation of each machine instruction operand.
-//
-struct MachineOperand {
- enum MachineOperandType {
- MO_Register, // Register operand.
- MO_Immediate, // Immediate Operand
- MO_MachineBasicBlock, // MachineBasicBlock reference
- MO_FrameIndex, // Abstract Stack Frame Index
- MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
- MO_JumpTableIndex, // Address of indexed Jump Table for switch
- MO_ExternalSymbol, // Name of external global symbol
- MO_GlobalAddress // Address of a global value
- };
-
-private:
- union {
- GlobalValue *GV; // For MO_GlobalAddress.
- MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
- const char *SymbolName; // For MO_ExternalSymbol.
- unsigned RegNo; // For MO_Register.
- int64_t immedVal; // For MO_Immediate and MO_*Index.
- } contents;
-
- MachineOperandType opType:8; // Discriminate the union.
- bool IsDef : 1; // True if this is a def, false if this is a use.
- bool IsImp : 1; // True if this is an implicit def or use.
-
- bool IsKill : 1; // True if this is a reg use and the reg is dead
- // immediately after the read.
- bool IsDead : 1; // True if this is a reg def and the reg is dead
- // immediately after the write. i.e. A register
- // that is defined but never used.
-
- /// offset - Offset to address of global or external, only valid for
- /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
- int offset;
-
- MachineOperand() {}
-
- void print(std::ostream &os) const;
- void print(std::ostream *os) const { if (os) print(*os); }
-
-public:
- MachineOperand(const MachineOperand &M) {
- *this = M;
- }
-
- ~MachineOperand() {}
-
- static MachineOperand CreateImm(int64_t Val) {
- MachineOperand Op;
- Op.opType = MachineOperand::MO_Immediate;
- Op.contents.immedVal = Val;
- Op.IsDef = false;
- Op.IsImp = false;
- Op.IsKill = false;
- Op.IsDead = false;
- Op.offset = 0;
- return Op;
- }
-
- const MachineOperand &operator=(const MachineOperand &MO) {
- contents = MO.contents;
- IsDef = MO.IsDef;
- IsImp = MO.IsImp;
- IsKill = MO.IsKill;
- IsDead = MO.IsDead;
- opType = MO.opType;
- offset = MO.offset;
- return *this;
- }
-
- /// getType - Returns the MachineOperandType for this operand.
- ///
- MachineOperandType getType() const { return opType; }
-
- /// Accessors that tell you what kind of MachineOperand you're looking at.
- ///
- bool isReg() const { return opType == MO_Register; }
- bool isImm() const { return opType == MO_Immediate; }
- bool isMBB() const { return opType == MO_MachineBasicBlock; }
-
- bool isRegister() const { return opType == MO_Register; }
- bool isImmediate() const { return opType == MO_Immediate; }
- bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
- bool isFrameIndex() const { return opType == MO_FrameIndex; }
- bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
- bool isJumpTableIndex() const { return opType == MO_JumpTableIndex; }
- bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
- bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
-
- int64_t getImm() const {
- assert(isImm() && "Wrong MachineOperand accessor");
- return contents.immedVal;
- }
-
- int64_t getImmedValue() const {
- assert(isImm() && "Wrong MachineOperand accessor");
- return contents.immedVal;
- }
- MachineBasicBlock *getMBB() const {
- assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
- return contents.MBB;
- }
- MachineBasicBlock *getMachineBasicBlock() const {
- assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
- return contents.MBB;
- }
- void setMachineBasicBlock(MachineBasicBlock *MBB) {
- assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
- contents.MBB = MBB;
- }
- int getFrameIndex() const {
- assert(isFrameIndex() && "Wrong MachineOperand accessor");
- return (int)contents.immedVal;
- }
- unsigned getConstantPoolIndex() const {
- assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
- return (unsigned)contents.immedVal;
- }
- unsigned getJumpTableIndex() const {
- assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
- return (unsigned)contents.immedVal;
- }
- GlobalValue *getGlobal() const {
- assert(isGlobalAddress() && "Wrong MachineOperand accessor");
- return contents.GV;
- }
- int getOffset() const {
- assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
- "Wrong MachineOperand accessor");
- return offset;
- }
- const char *getSymbolName() const {
- assert(isExternalSymbol() && "Wrong MachineOperand accessor");
- return contents.SymbolName;
- }
-
- bool isUse() const {
- assert(isRegister() && "Wrong MachineOperand accessor");
- return !IsDef;
- }
- bool isDef() const {
- assert(isRegister() && "Wrong MachineOperand accessor");
- return IsDef;
- }
- void setIsUse() {
- assert(isRegister() && "Wrong MachineOperand accessor");
- IsDef = false;
- }
- void setIsDef() {
- assert(isRegister() && "Wrong MachineOperand accessor");
- IsDef = true;
- }
-
- bool isImplicit() const {
- assert(isRegister() && "Wrong MachineOperand accessor");
- return IsImp;
- }
- void setImplicit() {
- assert(isRegister() && "Wrong MachineOperand accessor");
- IsImp = true;
- }
-
- bool isKill() const {
- assert(isRegister() && "Wrong MachineOperand accessor");
- return IsKill;
- }
- bool isDead() const {
- assert(isRegister() && "Wrong MachineOperand accessor");
- return IsDead;
- }
- void setIsKill() {
- assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
- IsKill = true;
- }
- void setIsDead() {
- assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
- IsDead = true;
- }
- void unsetIsKill() {
- assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
- IsKill = false;
- }
- void unsetIsDead() {
- assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
- IsDead = false;
- }
-
- /// getReg - Returns the register number.
- ///
- unsigned getReg() const {
- assert(isRegister() && "This is not a register operand!");
- return contents.RegNo;
- }
-
- /// MachineOperand mutators.
- ///
- void setReg(unsigned Reg) {
- assert(isRegister() && "This is not a register operand!");
- contents.RegNo = Reg;
- }
-
- void setImmedValue(int64_t immVal) {
- assert(isImm() && "Wrong MachineOperand mutator");
- contents.immedVal = immVal;
- }
- void setImm(int64_t immVal) {
- assert(isImm() && "Wrong MachineOperand mutator");
- contents.immedVal = immVal;
- }
-
- void setOffset(int Offset) {
- assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex() ||
- isJumpTableIndex()) &&
- "Wrong MachineOperand accessor");
- offset = Offset;
- }
- void setConstantPoolIndex(unsigned Idx) {
- assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
- contents.immedVal = Idx;
- }
- void setJumpTableIndex(unsigned Idx) {
- assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
- contents.immedVal = Idx;
- }
-
- /// isIdenticalTo - Return true if this operand is identical to the specified
- /// operand. Note: This method ignores isKill and isDead properties.
- bool isIdenticalTo(const MachineOperand &Other) const;
-
- /// ChangeToImmediate - Replace this operand with a new immediate operand of
- /// the specified value. If an operand is known to be an immediate already,
- /// the setImmedValue method should be used.
- void ChangeToImmediate(int64_t ImmVal) {
- opType = MO_Immediate;
- contents.immedVal = ImmVal;
- }
-
- /// ChangeToRegister - Replace this operand with a new register operand of
- /// the specified value. If an operand is known to be an register already,
- /// the setReg method should be used.
- void ChangeToRegister(unsigned Reg, bool isDef) {
- opType = MO_Register;
- contents.RegNo = Reg;
- IsDef = isDef;
- IsImp = false;
- IsKill = false;
- IsDead = false;
- }
-
- friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop) {
- mop.print(os);
- return os;
- }
-
- friend class MachineInstr;
-};
-
+class AliasAnalysis;
+class TargetInstrDesc;
+class TargetInstrInfo;
+class TargetRegisterInfo;
+class MachineFunction;
+class MachineMemOperand;
//===----------------------------------------------------------------------===//
/// MachineInstr - Representation of each machine instruction.
///
-class MachineInstr {
- const TargetInstrDescriptor *TID; // Instruction descriptor.
+class MachineInstr : public ilist_node<MachineInstr> {
+public:
+ typedef MachineMemOperand **mmo_iterator;
+
+private:
+ const TargetInstrDesc *TID; // Instruction descriptor.
unsigned short NumImplicitOps; // Number of implicit operands (which
// are determined at construction time).
+ unsigned short AsmPrinterFlags; // Various bits of information used by
+ // the AsmPrinter to emit helpful
+ // comments. This is *not* semantic
+ // information. Do not use this for
+ // anything other than to convey comment
+ // information to AsmPrinter.
+
std::vector<MachineOperand> Operands; // the operands
- MachineInstr* prev, *next; // links for our intrusive list
- MachineBasicBlock* parent; // pointer to the owning basic block
+ mmo_iterator MemRefs; // information on memory references
+ mmo_iterator MemRefsEnd;
+ MachineBasicBlock *Parent; // Pointer to the owning basic block.
+ DebugLoc debugLoc; // Source line information.
// OperandComplete - Return true if it's illegal to add a new operand
bool OperandsComplete() const;
- MachineInstr(const MachineInstr&);
+ MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
void operator=(const MachineInstr&); // DO NOT IMPLEMENT
// Intrusive list support
- //
friend struct ilist_traits<MachineInstr>;
+ friend struct ilist_traits<MachineBasicBlock>;
+ void setParent(MachineBasicBlock *P) { Parent = P; }
+
+ /// MachineInstr ctor - This constructor creates a copy of the given
+ /// MachineInstr in the given MachineFunction.
+ MachineInstr(MachineFunction &, const MachineInstr &);
-public:
/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
/// TID NULL and no operands.
MachineInstr();
+ // The next two constructors have DebugLoc and non-DebugLoc versions;
+ // over time, the non-DebugLoc versions should be phased out and eventually
+ // removed.
+
/// MachineInstr ctor - This constructor create a MachineInstr and add the
- /// implicit operands. It reserves space for number of operands specified by
- /// TargetInstrDescriptor.
- MachineInstr(const TargetInstrDescriptor &TID);
+ /// implicit operands. It reserves space for number of operands specified by
+ /// TargetInstrDesc. The version with a DebugLoc should be preferred.
+ explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
+
+ /// MachineInstr ctor - Work exactly the same as the ctor above, except that
+ /// the MachineInstr is created and added to the end of the specified basic
+ /// block. The version with a DebugLoc should be preferred.
+ ///
+ MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
+
+ /// MachineInstr ctor - This constructor create a MachineInstr and add the
+ /// implicit operands. It reserves space for number of operands specified by
+ /// TargetInstrDesc. An explicit DebugLoc is supplied.
+ explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
+ bool NoImp = false);
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
/// the MachineInstr is created and added to the end of the specified basic
/// block.
///
- MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
+ MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
+ const TargetInstrDesc &TID);
~MachineInstr();
- const MachineBasicBlock* getParent() const { return parent; }
- MachineBasicBlock* getParent() { return parent; }
+ // MachineInstrs are pool-allocated and owned by MachineFunction.
+ friend class MachineFunction;
+
+public:
+ const MachineBasicBlock* getParent() const { return Parent; }
+ MachineBasicBlock* getParent() { return Parent; }
+
+ /// getAsmPrinterFlags - Return the asm printer flags bitvector.
+ ///
+ unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; }
+
+ /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
+ ///
+ bool getAsmPrinterFlag(AsmPrinter::CommentFlag Flag) const {
+ return AsmPrinterFlags & Flag;
+ }
+
+ /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
+ ///
+ void setAsmPrinterFlag(unsigned short Flag) {
+ AsmPrinterFlags |= Flag;
+ }
+
+ /// getDebugLoc - Returns the debug location id of this MachineInstr.
+ ///
+ DebugLoc getDebugLoc() const { return debugLoc; }
- /// getInstrDescriptor - Returns the target instruction descriptor of this
+ /// getDesc - Returns the target instruction descriptor of this
/// MachineInstr.
- const TargetInstrDescriptor *getInstrDescriptor() const { return TID; }
+ const TargetInstrDesc &getDesc() const { return *TID; }
/// getOpcode - Returns the opcode of this MachineInstr.
///
- const int getOpcode() const;
+ int getOpcode() const { return TID->Opcode; }
/// Access to explicit operands of the instruction.
///
- unsigned getNumOperands() const { return Operands.size(); }
+ unsigned getNumOperands() const { return (unsigned)Operands.size(); }
const MachineOperand& getOperand(unsigned i) const {
assert(i < getNumOperands() && "getOperand() out of range!");
return Operands[i];
}
+ /// getNumExplicitOperands - Returns the number of non-implicit operands.
+ ///
+ unsigned getNumExplicitOperands() const;
+ /// Access to memory operands of the instruction
+ mmo_iterator memoperands_begin() const { return MemRefs; }
+ mmo_iterator memoperands_end() const { return MemRefsEnd; }
+ bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
+
+ /// hasOneMemOperand - Return true if this instruction has exactly one
+ /// MachineMemOperand.
+ bool hasOneMemOperand() const {
+ return MemRefsEnd - MemRefs == 1;
+ }
+
/// isIdenticalTo - Return true if this instruction is identical to (same
/// opcode and same operands as) the specified instruction.
bool isIdenticalTo(const MachineInstr *Other) const {
return true;
}
- /// clone - Create a copy of 'this' instruction that is identical in
- /// all ways except the the instruction has no parent, prev, or next.
- MachineInstr* clone() const { return new MachineInstr(*this); }
-
/// removeFromParent - This method unlinks 'this' from the containing basic
/// block, and returns it, but does not delete it.
MachineInstr *removeFromParent();
/// eraseFromParent - This method unlinks 'this' from the containing basic
/// block and deletes it.
- void eraseFromParent() {
- delete removeFromParent();
- }
+ void eraseFromParent();
- /// findRegisterUseOperand() - Returns the MachineOperand that is a use of
- /// the specific register or NULL if it is not found.
- MachineOperand *findRegisterUseOperand(unsigned Reg);
+ /// isLabel - Returns true if the MachineInstr represents a label.
+ ///
+ bool isLabel() const {
+ return getOpcode() == TargetOpcode::DBG_LABEL ||
+ getOpcode() == TargetOpcode::EH_LABEL ||
+ getOpcode() == TargetOpcode::GC_LABEL;
+ }
- /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
- /// the specific register or NULL if it is not found.
- MachineOperand *findRegisterDefOperand(unsigned Reg);
+ bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
+ bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
+ bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
+ bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
- /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
- ///
- void copyKillDeadInfo(const MachineInstr *MI);
-
- //
- // Debugging support
- //
- void print(std::ostream *OS, const TargetMachine *TM) const {
- if (OS) print(*OS, TM);
+ bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
+ bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
+ bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
+ bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
+ bool isExtractSubreg() const {
+ return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
}
- void print(std::ostream &OS, const TargetMachine *TM) const;
- void print(std::ostream &OS) const;
- void print(std::ostream *OS) const { if (OS) print(*OS); }
- void dump() const;
- friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr){
- minstr.print(os);
- return os;
+ bool isInsertSubreg() const {
+ return getOpcode() == TargetOpcode::INSERT_SUBREG;
}
-
- //===--------------------------------------------------------------------===//
- // Accessors to add operands when building up machine instructions.
- //
-
- /// addRegOperand - Add a register operand.
- ///
- void addRegOperand(unsigned Reg, bool IsDef, bool IsImp = false,
- bool IsKill = false, bool IsDead = false) {
- MachineOperand &Op = AddNewOperand(IsImp);
- Op.opType = MachineOperand::MO_Register;
- Op.IsDef = IsDef;
- Op.IsImp = IsImp;
- Op.IsKill = IsKill;
- Op.IsDead = IsDead;
- Op.contents.RegNo = Reg;
- Op.offset = 0;
+ bool isSubregToReg() const {
+ return getOpcode() == TargetOpcode::SUBREG_TO_REG;
}
-
- /// addImmOperand - Add a zero extended constant argument to the
- /// machine instruction.
- ///
- void addImmOperand(int64_t Val) {
- MachineOperand &Op = AddNewOperand();
- Op.opType = MachineOperand::MO_Immediate;
- Op.contents.immedVal = Val;
- Op.offset = 0;
+
+ /// readsRegister - Return true if the MachineInstr reads the specified
+ /// register. If TargetRegisterInfo is passed, then it also checks if there
+ /// is a read of a super-register.
+ bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
+ return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
}
- void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
- MachineOperand &Op = AddNewOperand();
- Op.opType = MachineOperand::MO_MachineBasicBlock;
- Op.contents.MBB = MBB;
- Op.offset = 0;
+ /// killsRegister - Return true if the MachineInstr kills the specified
+ /// register. If TargetRegisterInfo is passed, then it also checks if there is
+ /// a kill of a super-register.
+ bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
+ return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
}
- /// addFrameIndexOperand - Add an abstract frame index to the instruction
- ///
- void addFrameIndexOperand(unsigned Idx) {
- MachineOperand &Op = AddNewOperand();
- Op.opType = MachineOperand::MO_FrameIndex;
- Op.contents.immedVal = Idx;
- Op.offset = 0;
+ /// modifiesRegister - Return true if the MachineInstr modifies the
+ /// specified register. If TargetRegisterInfo is passed, then it also checks
+ /// if there is a def of a super-register.
+ bool modifiesRegister(unsigned Reg,
+ const TargetRegisterInfo *TRI = NULL) const {
+ return findRegisterDefOperandIdx(Reg, false, TRI) != -1;
}
- /// addConstantPoolndexOperand - Add a constant pool object index to the
- /// instruction.
- ///
- void addConstantPoolIndexOperand(unsigned Idx, int Offset) {
- MachineOperand &Op = AddNewOperand();
- Op.opType = MachineOperand::MO_ConstantPoolIndex;
- Op.contents.immedVal = Idx;
- Op.offset = Offset;
+ /// registerDefIsDead - Returns true if the register is dead in this machine
+ /// instruction. If TargetRegisterInfo is passed, then it also checks
+ /// if there is a dead def of a super-register.
+ bool registerDefIsDead(unsigned Reg,
+ const TargetRegisterInfo *TRI = NULL) const {
+ return findRegisterDefOperandIdx(Reg, true, TRI) != -1;
}
- /// addJumpTableIndexOperand - Add a jump table object index to the
- /// instruction.
- ///
- void addJumpTableIndexOperand(unsigned Idx) {
- MachineOperand &Op = AddNewOperand();
- Op.opType = MachineOperand::MO_JumpTableIndex;
- Op.contents.immedVal = Idx;
- Op.offset = 0;
+ /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
+ /// the specific register or -1 if it is not found. It further tightens
+ /// the search criteria to a use that kills the register if isKill is true.
+ int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
+ const TargetRegisterInfo *TRI = NULL) const;
+
+ /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
+ /// a pointer to the MachineOperand rather than an index.
+ MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
+ const TargetRegisterInfo *TRI = NULL) {
+ int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
+ return (Idx == -1) ? NULL : &getOperand(Idx);
}
- void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
- MachineOperand &Op = AddNewOperand();
- Op.opType = MachineOperand::MO_GlobalAddress;
- Op.contents.GV = GV;
- Op.offset = Offset;
- }
+ /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
+ /// the specified register or -1 if it is not found. If isDead is true, defs
+ /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
+ /// also checks if there is a def of a super-register.
+ int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false,
+ const TargetRegisterInfo *TRI = NULL) const;
+
+ /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
+ /// a pointer to the MachineOperand rather than an index.
+ MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
+ const TargetRegisterInfo *TRI = NULL) {
+ int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
+ return (Idx == -1) ? NULL : &getOperand(Idx);
+ }
+
+ /// findFirstPredOperandIdx() - Find the index of the first operand in the
+ /// operand list that is used to represent the predicate. It returns -1 if
+ /// none is found.
+ int findFirstPredOperandIdx() const;
+
+ /// isRegTiedToUseOperand - Given the index of a register def operand,
+ /// check if the register def is tied to a source operand, due to either
+ /// two-address elimination or inline assembly constraints. Returns the
+ /// first tied use operand index by reference is UseOpIdx is not null.
+ bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
- /// addExternalSymbolOperand - Add an external symbol operand to this instr
+ /// isRegTiedToDefOperand - Return true if the use operand of the specified
+ /// index is tied to an def operand. It also returns the def operand index by
+ /// reference if DefOpIdx is not null.
+ bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
+
+ /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
///
- void addExternalSymbolOperand(const char *SymName) {
- MachineOperand &Op = AddNewOperand();
- Op.opType = MachineOperand::MO_ExternalSymbol;
- Op.contents.SymbolName = SymName;
- Op.offset = 0;
- }
+ void copyKillDeadInfo(const MachineInstr *MI);
+
+ /// copyPredicates - Copies predicate operand(s) from MI.
+ void copyPredicates(const MachineInstr *MI);
+
+ /// addRegisterKilled - We have determined MI kills a register. Look for the
+ /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
+ /// add a implicit operand if it's not found. Returns true if the operand
+ /// exists / is added.
+ bool addRegisterKilled(unsigned IncomingReg,
+ const TargetRegisterInfo *RegInfo,
+ bool AddIfNotFound = false);
+
+ /// addRegisterDead - We have determined MI defined a register without a use.
+ /// Look for the operand that defines it and mark it as IsDead. If
+ /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
+ /// true if the operand exists / is added.
+ bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
+ bool AddIfNotFound = false);
+
+ /// addRegisterDefined - We have determined MI defines a register. Make sure
+ /// there is an operand defining Reg.
+ void addRegisterDefined(unsigned IncomingReg,
+ const TargetRegisterInfo *RegInfo);
+
+ /// isSafeToMove - Return true if it is safe to move this instruction. If
+ /// SawStore is set to true, it means that there is a store (or call) between
+ /// the instruction's location and its intended destination.
+ bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore,
+ AliasAnalysis *AA) const;
+
+ /// isSafeToReMat - Return true if it's safe to rematerialize the specified
+ /// instruction which defined the specified register instead of copying it.
+ bool isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg,
+ AliasAnalysis *AA) const;
+
+ /// hasVolatileMemoryRef - Return true if this instruction may have a
+ /// volatile memory reference, or if the information describing the
+ /// memory reference is not available. Return false if it is known to
+ /// have no volatile memory references.
+ bool hasVolatileMemoryRef() const;
+
+ /// isInvariantLoad - Return true if this instruction is loading from a
+ /// location whose value is invariant across the function. For example,
+ /// loading a value from the constant pool or from from the argument area of
+ /// a function if it does not change. This should only return true of *all*
+ /// loads the instruction does are invariant (if it does multiple loads).
+ bool isInvariantLoad(AliasAnalysis *AA) const;
+
+ /// isConstantValuePHI - If the specified instruction is a PHI that always
+ /// merges together the same virtual register, return the register, otherwise
+ /// return 0.
+ unsigned isConstantValuePHI() const;
- //===--------------------------------------------------------------------===//
- // Accessors used to modify instructions in place.
//
+ // Debugging support
+ //
+ void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
+ void dump() const;
+
+ //===--------------------------------------------------------------------===//
+ // Accessors used to build up machine instructions.
- /// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
+ /// addOperand - Add the specified operand to the instruction. If it is an
+ /// implicit operand, it is added to the end of the operand list. If it is
+ /// an explicit operand it is added at the end of the explicit operand list
+ /// (before the first implicit operand).
+ void addOperand(const MachineOperand &Op);
+
+ /// setDesc - Replace the instruction descriptor (thus opcode) of
/// the current instruction with a new one.
///
- void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
+ void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
+
+ /// setDebugLoc - Replace current source information with new such.
+ /// Avoid using this, the constructor argument is preferable.
+ ///
+ void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with.
///
- void RemoveOperand(unsigned i) {
- Operands.erase(Operands.begin()+i);
+ void RemoveOperand(unsigned i);
+
+ /// addMemOperand - Add a MachineMemOperand to the machine instruction.
+ /// This function should be used only occasionally. The setMemRefs function
+ /// is the primary method for setting up a MachineInstr's MemRefs list.
+ void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
+
+ /// setMemRefs - Assign this MachineInstr's memory reference descriptor
+ /// list. This does not transfer ownership.
+ void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
+ MemRefs = NewMemRefs;
+ MemRefsEnd = NewMemRefsEnd;
}
+
private:
- MachineOperand &AddNewOperand(bool IsImp = false) {
- assert((IsImp || !OperandsComplete()) &&
- "Trying to add an operand to a machine instr that is already done!");
- if (NumImplicitOps == 0) { // This is true most of the time.
- Operands.push_back(MachineOperand());
- return Operands.back();
- } else {
- return *Operands.insert(Operands.begin()+Operands.size()-NumImplicitOps,
- MachineOperand());
- }
- }
+ /// getRegInfo - If this instruction is embedded into a MachineFunction,
+ /// return the MachineRegisterInfo object for the current function, otherwise
+ /// return null.
+ MachineRegisterInfo *getRegInfo();
/// addImplicitDefUseOperands - Add all implicit def and use operands to
/// this instruction.
void addImplicitDefUseOperands();
+
+ /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
+ /// this instruction from their respective use lists. This requires that the
+ /// operands already be on their use lists.
+ void RemoveRegOperandsFromUseLists();
+
+ /// AddRegOperandsToUseLists - Add all of the register operands in
+ /// this instruction from their respective use lists. This requires that the
+ /// operands not be on their use lists yet.
+ void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
};
//===----------------------------------------------------------------------===//
// Debugging Support
-std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
-std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
+inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
+ MI.print(OS);
+ return OS;
+}
} // End llvm namespace
projects / oota-llvm.git / blobdiff