Increase the size of PMTopLevelManager::ImmutablePasses from 8 to 16.

[oota-llvm.git] / docs / index.rst

diff --git a/docs/index.rst b/docs/index.rst
index 62766f10342fe0b6d512172cb6658d46808b1136..1d4fbd9d34d0c03799bc09ae49dc57d1fc762f5e 100644 (file)
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -215,6 +215,7 @@ For API clients and LLVM developers.
 
    AliasAnalysis
    BitCodeFormat
+   BlockFrequencyTerminology
    BranchWeightMetadata
    Bugpoint
    CodeGenerator
@@ -222,6 +223,7 @@ For API clients and LLVM developers.
    LinkTimeOptimization
    SegmentedStacks
    TableGenFundamentals
+   TableGen/index
    DebuggingJITedCode
    GoldPlugin
    MarkedUpDisassembly
@@ -231,9 +233,11 @@ For API clients and LLVM developers.
    WritingAnLLVMBackend
    GarbageCollection
    WritingAnLLVMPass
-   TableGen/LangRef
    HowToUseAttributes
    NVPTXUsage
+   StackMaps
+   InAlloca
+   BigEndianNEON
 
 :doc:`WritingAnLLVMPass`
    Information on how to write LLVM transformations and analyses.
@@ -246,7 +250,7 @@ For API clients and LLVM developers.
    working on retargetting LLVM to a new architecture, designing a new codegen
    pass, or enhancing existing components.
 
-:doc:`TableGenFundamentals`
+:doc:`TableGen <TableGen/index>`
    Describes the TableGen tool, which is used heavily by the LLVM code
    generator.
 
@@ -296,6 +300,10 @@ For API clients and LLVM developers.
 :doc:`BranchWeightMetadata`
    Provides information about Branch Prediction Information.
 
+:doc:`BlockFrequencyTerminology`
+   Provides information about terminology used in the ``BlockFrequencyInfo``
+   analysis pass.
+
 :doc:`SegmentedStacks`
    This document describes segmented stacks and how they are used in LLVM.
 
@@ -308,6 +316,14 @@ For API clients and LLVM developers.
 :doc:`NVPTXUsage`
    This document describes using the NVPTX back-end to compile GPU kernels.
 
+:doc:`StackMaps`
+  LLVM support for mapping instruction addresses to the location of
+  values and allowing code to be patched.
+
+:doc:`BigEndianNEON`
+  LLVM's support for generating NEON instructions on big endian ARM targets is
+  somewhat nonintuitive. This document explains the implementation and rationale.
+
 
 Development Process Documentation
 =================================