"http://www.w3.org/TR/html4/strict.dtd">
<html>
<head>
+ <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
<title>Writing an LLVM Compiler Backend</title>
<link rel="stylesheet" href="llvm.css" type="text/css">
</head>
<body>
-<div class="doc_title">
+<h1>
Writing an LLVM Compiler Backend
-</div>
+</h1>
<ol>
<li><a href="#intro">Introduction</a>
<li><a href="#Preliminaries">Preliminaries</a></li>
</ul>
<li><a href="#TargetMachine">Target Machine</a></li>
+ <li><a href="#TargetRegistration">Target Registration</a></li>
<li><a href="#RegisterSet">Register Set and Register Classes</a>
<ul>
<li><a href="#RegisterDef">Defining a Register</a></li>
</div>
<!-- *********************************************************************** -->
-<div class="doc_section">
+<h2>
<a name="intro">Introduction</a>
-</div>
+</h2>
<!-- *********************************************************************** -->
-<div class="doc_text">
+<div>
<p>
This document describes techniques for writing compiler backends that convert
conventions.
</p>
-</div>
-
-<div class="doc_subsection">
+<h3>
<a name="Audience">Audience</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
The audience for this document is anyone who needs to write an LLVM backend to
</div>
-<div class="doc_subsection">
+<h3>
<a name="Prerequisite">Prerequisite Reading</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
These essential documents must be read before reading this document:
</p>
<ul>
-<li><i><a href="http://www.llvm.org/docs/LangRef.html">LLVM Language Reference
+<li><i><a href="LangRef.html">LLVM Language Reference
Manual</a></i> — a reference manual for the LLVM assembly language.</li>
-<li><i><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
+<li><i><a href="CodeGenerator.html">The LLVM
Target-Independent Code Generator</a></i> — a guide to the components
(classes and code generation algorithms) for translating the LLVM internal
representation into machine code for a specified target. Pay particular
Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations,
and Code Emission.</li>
-<li><i><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen
+<li><i><a href="TableGenFundamentals.html">TableGen
Fundamentals</a></i> —a document that describes the TableGen
(<tt>tblgen</tt>) application that manages domain-specific information to
support LLVM code generation. TableGen processes input from a target
description file (<tt>.td</tt> suffix) and generates C++ code that can be
used for code generation.</li>
-<li><i><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM
+<li><i><a href="WritingAnLLVMPass.html">Writing an LLVM
Pass</a></i> — The assembly printer is a <tt>FunctionPass</tt>, as are
several SelectionDAG processing steps.</li>
</ul>
</div>
-<div class="doc_subsection">
+<h3>
<a name="Basic">Basic Steps</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
To write a compiler backend for LLVM that converts the LLVM IR to code for a
</div>
-<div class="doc_subsection">
+<h3>
<a name="Preliminaries">Preliminaries</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
To actually create your compiler backend, you need to create and modify a few
files. The absolute minimum is discussed here. But to actually use the LLVM
target-independent code generator, you must perform the steps described in
-the <a href="http://www.llvm.org/docs/CodeGenerator.html">LLVM
+the <a href="CodeGenerator.html">LLVM
Target-Independent Code Generator</a> document.
</p>
</div>
+</div>
+
<!-- *********************************************************************** -->
-<div class="doc_section">
+<h2>
<a name="TargetMachine">Target Machine</a>
-</div>
+</h2>
<!-- *********************************************************************** -->
-<div class="doc_text">
+<div>
<p>
<tt>LLVMTargetMachine</tt> is designed as a base class for targets implemented
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
- std::ostream &Out);
};
} // end namespace llvm
</pre>
</div>
-</div>
-
-
-<div class="doc_text">
-
<ul>
<li><tt>getInstrInfo()</tt></li>
<li><tt>getRegisterInfo()</tt></li>
</pre>
</div>
-</div>
-
-<div class="doc_text">
-
<p>Hyphens separate portions of the <tt>TargetDescription</tt> string.</p>
<ul>
alignment, and then ABI preferred alignment.</li>
</ul>
+</div>
+
+<!-- *********************************************************************** -->
+<h2>
+ <a name="TargetRegistration">Target Registration</a>
+</h2>
+<!-- *********************************************************************** -->
+
+<div>
+
+<p>
+You must also register your target with the <tt>TargetRegistry</tt>, which is
+what other LLVM tools use to be able to lookup and use your target at
+runtime. The <tt>TargetRegistry</tt> can be used directly, but for most targets
+there are helper templates which should take care of the work for you.</p>
+
<p>
-You must also register your target using the <tt>RegisterTarget</tt>
-template. (See the <tt>TargetMachineRegistry</tt> class.) For example,
-in <tt>SparcTargetMachine.cpp</tt>, the target is registered with:
+All targets should declare a global <tt>Target</tt> object which is used to
+represent the target during registration. Then, in the target's TargetInfo
+library, the target should define that object and use
+the <tt>RegisterTarget</tt> template to register the target. For example, the Sparc registration code looks like this:
</p>
<div class="doc_code">
<pre>
-namespace {
- // Register the target.
- RegisterTarget<SparcTargetMachine>X("sparc", "SPARC");
+Target llvm::TheSparcTarget;
+
+extern "C" void LLVMInitializeSparcTargetInfo() {
+ RegisterTarget<Triple::sparc, /*HasJIT=*/false>
+ X(TheSparcTarget, "sparc", "Sparc");
}
</pre>
</div>
+<p>
+This allows the <tt>TargetRegistry</tt> to look up the target by name or by
+target triple. In addition, most targets will also register additional features
+which are available in separate libraries. These registration steps are
+separate, because some clients may wish to only link in some parts of the target
+-- the JIT code generator does not require the use of the assembler printer, for
+example. Here is an example of registering the Sparc assembly printer:
+</p>
+
+<div class="doc_code">
+<pre>
+extern "C" void LLVMInitializeSparcAsmPrinter() {
+ RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
+}
+</pre>
+</div>
+
+<p>
+For more information, see
+"<a href="/doxygen/TargetRegistry_8h-source.html">llvm/Target/TargetRegistry.h</a>".
+</p>
+
</div>
<!-- *********************************************************************** -->
-<div class="doc_section">
+<h2>
<a name="RegisterSet">Register Set and Register Classes</a>
-</div>
+</h2>
<!-- *********************************************************************** -->
-<div class="doc_text">
+<div>
<p>
You should describe a concrete target-specific class that represents the
implementation of <tt>XXXRegisterInfo</tt> requires hand-coding.
</p>
-</div>
-
<!-- ======================================================================= -->
-<div class="doc_subsection">
+<h3>
<a name="RegisterDef">Defining a Register</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
The <tt>XXXRegisterInfo.td</tt> file typically starts with register definitions
<p>
This defines the register <tt>AL</tt> and assigns it values (with
<tt>DwarfRegNum</tt>) that are used by <tt>gcc</tt>, <tt>gdb</tt>, or a debug
-information writer (such as <tt>DwarfWriter</tt>
-in <tt>llvm/lib/CodeGen/AsmPrinter</tt>) to identify a register. For register
+information writer to identify a register. For register
<tt>AL</tt>, <tt>DwarfRegNum</tt> takes an array of 3 values representing 3
different modes: the first element is for X86-64, the second for exception
handling (EH) on X86-32, and the third is generic. -1 is a special Dwarf number
</div>
<!-- ======================================================================= -->
-<div class="doc_subsection">
+<h3>
<a name="RegisterClassDef">Defining a Register Class</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
The <tt>RegisterClass</tt> class (specified in <tt>Target.td</tt>) is used to
<div class="doc_code">
<pre>
class RegisterClass<string namespace,
-list<ValueType> regTypes, int alignment,
- list<Register> regList> {
+list<ValueType> regTypes, int alignment, dag regList> {
string Namespace = namespace;
list<ValueType> RegTypes = regTypes;
int Size = 0; // spill size, in bits; zero lets tblgen pick the size
// default value 1 means a single instruction
// A negative value means copying is extremely expensive or impossible
int CopyCost = 1;
- list<Register> MemberList = regList;
+ dag MemberList = regList;
// for register classes that are subregisters of this class
list<RegisterClass> SubRegClassList = [];
memory.</li>
<li>The final argument, <tt>regList</tt>, specifies which registers are in this
- class. If an <tt>allocation_order_*</tt> method is not specified,
- then <tt>regList</tt> also defines the order of allocation used by the
- register allocator.</li>
+ class. If an alternative allocation order method is not specified, then
+ <tt>regList</tt> also defines the order of allocation used by the register
+ allocator. Besides simply listing registers with <tt>(add R0, R1, ...)</tt>,
+ more advanced set operators are available. See
+ <tt>include/llvm/Target/Target.td</tt> for more information.</li>
</ul>
<p>
'<tt>SP</tt>'. <tt>FPRegs</tt> defines a group of 32 single-precision
floating-point registers (<tt>F0</tt> to <tt>F31</tt>); <tt>DFPRegs</tt> defines
a group of 16 double-precision registers
-(<tt>D0-D15</tt>). For <tt>IntRegs</tt>, the <tt>MethodProtos</tt>
-and <tt>MethodBodies</tt> methods are used by TableGen to insert the specified
-code into generated output.
+(<tt>D0-D15</tt>).
</p>
<div class="doc_code">
<pre>
-def FPRegs : RegisterClass<"SP", [f32], 32,
- [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,
- F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+// F0, F1, F2, ..., F31
+def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
def DFPRegs : RegisterClass<"SP", [f64], 64,
- [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15]>;
+ (add D0, D1, D2, D3, D4, D5, D6, D7, D8,
+ D9, D10, D11, D12, D13, D14, D15)>;
def IntRegs : RegisterClass<"SP", [i32], 32,
- [L0, L1, L2, L3, L4, L5, L6, L7,
- I0, I1, I2, I3, I4, I5,
- O0, O1, O2, O3, O4, O5, O7,
- G1,
- // Non-allocatable regs:
- G2, G3, G4,
- O6, // stack ptr
- I6, // frame ptr
- I7, // return address
- G0, // constant zero
- G5, G6, G7 // reserved for kernel
- ]> {
- let MethodProtos = [{
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- IntRegsClass::iterator
- IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
- return end() - 10 // Don't allocate special registers
- -1;
- }
- }];
-}
+ (add L0, L1, L2, L3, L4, L5, L6, L7,
+ I0, I1, I2, I3, I4, I5,
+ O0, O1, O2, O3, O4, O5, O7,
+ G1,
+ // Non-allocatable regs:
+ G2, G3, G4,
+ O6, // stack ptr
+ I6, // frame ptr
+ I7, // return address
+ G0, // constant zero
+ G5, G6, G7 // reserved for kernel
+ )>;
</pre>
</div>
register implementation. The code below shows only the generated integer
registers and associated register classes. The order of registers
in <tt>IntRegs</tt> reflects the order in the definition of <tt>IntRegs</tt> in
-the target description file. Take special note of the use
-of <tt>MethodBodies</tt> in <tt>SparcRegisterInfo.td</tt> to create code in
-<tt>SparcGenRegisterInfo.inc</tt>. <tt>MethodProtos</tt> generates similar code
-in <tt>SparcGenRegisterInfo.h.inc</tt>.
+the target description file.
</p>
<div class="doc_code">
static const TargetRegisterClass* const IntRegsSuperclasses [] = {
NULL
};
-...
- IntRegsClass::iterator
- IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
- return end()-10 // Don't allocate special registers
- -1;
- }
-
+
IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID,
IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses,
IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
</pre>
</div>
+<p>
+The register allocators will avoid using reserved registers, and callee saved
+registers are not used until all the volatile registers have been used. That
+is usually good enough, but in some cases it may be necessary to provide custom
+allocation orders.
+</p>
+
</div>
<!-- ======================================================================= -->
-<div class="doc_subsection">
+<h3>
<a name="implementRegister">Implement a subclass of</a>
- <a href="http://www.llvm.org/docs/CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a>
-</div>
+ <a href="CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a>
+</h3>
-<div class="doc_text">
+<div>
<p>
The final step is to hand code portions of <tt>XXXRegisterInfo</tt>, which
<li><tt>getCalleeSavedRegs</tt> — Returns a list of callee-saved registers
in the order of the desired callee-save stack frame offset.</li>
-<li><tt>getCalleeSavedRegClasses</tt> — Returns a list of preferred
- register classes with which to spill each callee saved register.</li>
-
<li><tt>getReservedRegs</tt> — Returns a bitset indexed by physical
register numbers, indicating if a particular register is unavailable.</li>
</div>
+</div>
+
<!-- *********************************************************************** -->
-<div class="doc_section">
+<h2>
<a name="InstructionSet">Instruction Set</a>
-</div>
+</h2>
<!-- *********************************************************************** -->
-<div class="doc_text">
+<div>
<p>
During the early stages of code generation, the LLVM IR code is converted to a
left as an empty string until the assembly printer interface is implemented. The
sixth and final parameter is the pattern used to match the instruction during
the SelectionDAG Select Phase described in
-(<a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
+(<a href="CodeGenerator.html">The LLVM
Target-Independent Code Generator</a>). This parameter is detailed in the next
section, <a href="#InstructionSelector">Instruction Selector</a>.
</p>
<tt>SPCC::ICC_NE = 9</tt>, <tt>SPCC::FCC_U = 23</tt> and so on.)
</p>
-</div>
-
<!-- ======================================================================= -->
-<div class="doc_subsection">
+<h3>
<a name="operandMapping">Instruction Operand Mapping</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
The code generator backend maps instruction operands to fields in the
</div>
<!-- ======================================================================= -->
-<div class="doc_subsection">
+<h3>
<a name="implementInstr">Implement a subclass of </a>
- <a href="http://www.llvm.org/docs/CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a>
-</div>
+ <a href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a>
+</h3>
-<div class="doc_text">
+<div>
<p>
The final step is to hand code portions of <tt>XXXInstrInfo</tt>, which
</p>
<ul>
-<li><tt>isMoveInstr</tt> — Return true if the instruction is a register to
- register move; false, otherwise.</li>
-
<li><tt>isLoadFromStackSlot</tt> — If the specified machine instruction is
a direct load from a stack slot, return the register number of the
destination and the <tt>FrameIndex</tt> of the stack slot.</li>
a direct store to a stack slot, return the register number of the
destination and the <tt>FrameIndex</tt> of the stack slot.</li>
-<li><tt>copyRegToReg</tt> — Copy values between a pair of registers.</li>
+<li><tt>copyPhysReg</tt> — Copy values between a pair of physical
+ registers.</li>
<li><tt>storeRegToStackSlot</tt> — Store a register value to a stack
slot.</li>
</div>
<!-- ======================================================================= -->
-<div class="doc_subsection">
+<h3>
<a name="branchFolding">Branch Folding and If Conversion</a>
-</div>
-<div class="doc_text">
+</h3>
+<div>
<p>
Performance can be improved by combining instructions or by eliminating
</div>
+</div>
+
<!-- *********************************************************************** -->
-<div class="doc_section">
+<h2>
<a name="InstructionSelector">Instruction Selector</a>
-</div>
+</h2>
<!-- *********************************************************************** -->
-<div class="doc_text">
+<div>
<p>
LLVM uses a <tt>SelectionDAG</tt> to represent LLVM IR instructions, and nodes
The LLVM static compiler (<tt>llc</tt>) is an excellent tool for visualizing the
contents of DAGs. To display the <tt>SelectionDAG</tt> before or after specific
processing phases, use the command line options for <tt>llc</tt>, described
-at <a href="http://llvm.org/docs/CodeGenerator.html#selectiondag_process">
+at <a href="CodeGenerator.html#selectiondag_process">
SelectionDAG Instruction Selection Process</a>.
</p>
</pre>
</div>
-</div>
-
<!-- ======================================================================= -->
-<div class="doc_subsection">
+<h3>
<a name="LegalizePhase">The SelectionDAG Legalize Phase</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
The Legalize phase converts a DAG to use types and operations that are natively
contains examples of all four <tt>LegalAction</tt> values.
</p>
-</div>
-
<!-- _______________________________________________________________________ -->
-<div class="doc_subsubsection">
+<h4>
<a name="promote">Promote</a>
-</div>
+</h4>
-<div class="doc_text">
+<div>
<p>
For an operation without native support for a given type, the specified type may
</div>
<!-- _______________________________________________________________________ -->
-<div class="doc_subsubsection">
+<h4>
<a name="expand">Expand</a>
-</div>
+</h4>
-<div class="doc_text">
+<div>
<p>
For a type without native support, a value may need to be broken down further,
</div>
<!-- _______________________________________________________________________ -->
-<div class="doc_subsubsection">
+<h4>
<a name="custom">Custom</a>
-</div>
+</h4>
-<div class="doc_text">
+<div>
<p>
For some operations, simple type promotion or operation expansion may be
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
assert(Op.getValueType() == MVT::i32);
Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
- return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
+ return DAG.getNode(ISD::BITCAST, MVT::i32, Op);
}
</pre>
</div>
</div>
<!-- _______________________________________________________________________ -->
-<div class="doc_subsubsection">
+<h4>
<a name="legal">Legal</a>
-</div>
+</h4>
-<div class="doc_text">
+<div>
<p>
The <tt>Legal</tt> LegalizeAction enum value simply indicates that an
</div>
+</div>
+
<!-- ======================================================================= -->
-<div class="doc_subsection">
+<h3>
<a name="callingConventions">Calling Conventions</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
To support target-specific calling conventions, <tt>XXXGenCallingConv.td</tt>
</div>
+</div>
+
<!-- *********************************************************************** -->
-<div class="doc_section">
+<h2>
<a name="assemblyPrinter">Assembly Printer</a>
-</div>
+</h2>
<!-- *********************************************************************** -->
-<div class="doc_text">
+<div>
<p>
During the code emission stage, the code generator may utilize an LLVM pass to
<p>
The X86 assembly printer implementation (<tt>X86TargetAsmInfo</tt>) is an
-example where the target specific <tt>TargetAsmInfo</tt> class uses overridden
-methods: <tt>ExpandInlineAsm</tt> and <tt>PreferredEHDataFormat</tt>.
+example where the target specific <tt>TargetAsmInfo</tt> class uses an
+overridden methods: <tt>ExpandInlineAsm</tt>.
</p>
<p>
<li><tt>printImplicitDef</tt></li>
<li><tt>printInlineAsm</tt></li>
-
-<li><tt>printLabel</tt></li>
-
-<li><tt>printPICJumpTableEntry</tt></li>
-
-<li><tt>printPICJumpTableSetLabel</tt></li>
</ul>
<p>
The implementations of <tt>printDeclare</tt>, <tt>printImplicitDef</tt>,
<tt>printInlineAsm</tt>, and <tt>printLabel</tt> in <tt>AsmPrinter.cpp</tt> are
generally adequate for printing assembly and do not need to be
-overridden. (<tt>printBasicBlockLabel</tt> is another method that is implemented
-in <tt>AsmPrinter.cpp</tt> that may be directly used in an implementation of
-<tt>XXXAsmPrinter</tt>.)
+overridden.
</p>
<p>
</div>
<!-- *********************************************************************** -->
-<div class="doc_section">
+<h2>
<a name="subtargetSupport">Subtarget Support</a>
-</div>
+</h2>
<!-- *********************************************************************** -->
-<div class="doc_text">
+<div>
<p>
Subtarget support is used to inform the code generation process of instruction
</div>
<!-- *********************************************************************** -->
-<div class="doc_section">
+<h2>
<a name="jitSupport">JIT Support</a>
-</div>
+</h2>
<!-- *********************************************************************** -->
-<div class="doc_text">
+<div>
<p>
The implementation of a target machine optionally includes a Just-In-Time (JIT)
that write data (in bytes, words, strings, etc.) to the output stream.
</p>
-</div>
-
<!-- ======================================================================= -->
-<div class="doc_subsection">
+<h3>
<a name="mce">Machine Code Emitter</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
In <tt>XXXCodeEmitter.cpp</tt>, a target-specific of the <tt>Emitter</tt> class
</div>
<!-- ======================================================================= -->
-<div class="doc_subsection">
+<h3>
<a name="targetJITInfo">Target JIT Info</a>
-</div>
+</h3>
-<div class="doc_text">
+<div>
<p>
<tt>XXXJITInfo.cpp</tt> implements the JIT interfaces for target-specific
</div>
+</div>
+
<!-- *********************************************************************** -->
<hr>
src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a>
<a href="http://www.woo.com">Mason Woo</a> and <a href="http://misha.brukman.net">Misha Brukman</a><br>
- <a href="http://llvm.org">The LLVM Compiler Infrastructure</a>
+ <a href="http://llvm.org/">The LLVM Compiler Infrastructure</a>
<br>
Last modified: $Date$
</address>
projects / oota-llvm.git / blobdiff