======================
-LLVM 3.3 Release Notes
+LLVM 3.5 Release Notes
======================
.. contents::
:local:
.. warning::
- These are in-progress notes for the upcoming LLVM 3.3 release. You may
- prefer the `LLVM 3.2 Release Notes <http://llvm.org/releases/3.2/docs
+ These are in-progress notes for the upcoming LLVM 3.5 release. You may
+ prefer the `LLVM 3.4 Release Notes <http://llvm.org/releases/3.4/docs
/ReleaseNotes.html>`_.
============
This document contains the release notes for the LLVM Compiler Infrastructure,
-release 3.3. Here we describe the status of LLVM, including major improvements
+release 3.5. Here we describe the status of LLVM, including major improvements
from the previous release, improvements in various subprojects of LLVM, and
some of the current users of the code. All LLVM releases may be downloaded
from the `LLVM releases web site <http://llvm.org/releases/>`_.
Non-comprehensive list of changes in this release
=================================================
-.. NOTE
- For small 1-3 sentence descriptions, just add an entry at the end of
- this list. If your description won't fit comfortably in one bullet
- point (e.g. maybe you would like to give an example of the
- functionality, or simply have a lot to talk about), see the `NOTE` below
- for adding a new subsection.
-
-* The CellSPU port has been removed. It can still be found in older versions.
-
-* The IR-level extended linker APIs (for example, to link bitcode files out of
- archives) have been removed. Any existing clients of these features should
- move to using a linker with integrated LTO support.
+* All backends have been changed to use the MC asm printer and support for the
+ non MC one has been removed.
-* LLVM and Clang's documentation has been migrated to the `Sphinx
- <http://sphinx-doc.org/>`_ documentation generation system which uses
- easy-to-write reStructuredText. See `llvm/docs/README.txt` for more
- information.
+* Clang can now successfully self-host itself on Linux/Sparc64 and on
+ FreeBSD/Sparc64.
-* TargetTransformInfo (TTI) is a new interface that can be used by IR-level
- passes to obtain target-specific information, such as the costs of
- instructions. Only "Lowering" passes such as LSR and the vectorizer are
- allowed to use the TTI infrastructure.
+* LLVM now assumes the assembler supports ``.loc`` for generating debug line
+ numbers. The old support for printing the debug line info directly was only
+ used by ``llc`` and has been removed.
-* We've improved the X86 and ARM cost model.
+* All inline assembly is parsed by the integrated assembler when it is enabled.
+ Previously this was only the case for object-file output. It is now the case
+ for assembly output as well. The integrated assembler can be disabled with
+ the ``-no-integrated-as`` option,
-* The Attributes classes have been completely rewritten and expanded. They now
- support not only enumerated attributes and alignments, but "string"
- attributes, which are useful for passing information to code generation. See
- :doc:`HowToUseAttributes` for more details.
+* llvm-ar now handles IR files like regular object files. In particular, a
+ regular symbol table is created for symbols defined in IR files, including
+ those in file scope inline assembly.
-* TableGen's syntax for instruction selection patterns has been simplified.
- Instead of specifying types indirectly with register classes, you should now
- specify types directly in the input patterns. See ``SparcInstrInfo.td`` for
- examples of the new syntax. The old syntax using register classes still
- works, but it will be removed in a future LLVM release.
+* LLVM now always uses cfi directives for producing most stack
+ unwinding information.
-* MCJIT now supports exception handling. Support for it in the old jit will be
- removed in the 3.4 release.
+* The prefix for loop vectorizer hint metadata has been changed from
+ ``llvm.vectorizer`` to ``llvm.loop.vectorize``.
-* Command line options can now be grouped into categories which are shown in
- the output of ``-help``. See :ref:`grouping options into categories`.
+* Some backends previously implemented Atomic NAND(x,y) as ``x & ~y``. Now
+ all backends implement it as ``~(x & y)``, matching the semantics of GCC 4.4
+ and later.
-* The appearance of command line options in ``-help`` that are inherited by
- linking with libraries that use the LLVM Command line support library can now
- be modified at runtime. See :ref:`cl::getRegisteredOptions`.
+.. NOTE
+ For small 1-3 sentence descriptions, just add an entry at the end of
+ this list. If your description won't fit comfortably in one bullet
+ point (e.g. maybe you would like to give an example of the
+ functionality, or simply have a lot to talk about), see the `NOTE` below
+ for adding a new subsection.
* ... next change ...
Makes programs 10x faster by doing Special New Thing.
-AArch64 target
---------------
-
-We've added support for AArch64, ARM's 64-bit architecture. Development is still
-in fairly early stages, but we expect successful compilation when:
-
-- compiling standard compliant C99 and C++03 with Clang;
-- using Linux as a target platform;
-- where code + static data doesn't exceed 4GB in size (heap allocated data has
- no limitation).
-
-Some additional functionality is also implemented, notably DWARF debugging,
-GNU-style thread local storage and inline assembly.
-
-Hexagon Target
---------------
-
-- Removed support for legacy hexagonv2 and hexagonv3 processor
- architectures which are no longer in use. Currently supported
- architectures are hexagonv4 and hexagonv5.
-
-Loop Vectorizer
----------------
-
-We've continued the work on the loop vectorizer. The loop vectorizer now
-has the following features:
-
-- Loops with unknown trip counts.
-- Runtime checks of pointers.
-- Reductions, Inductions.
-- Min/Max reductions of integers.
-- If Conversion.
-- Pointer induction variables.
-- Reverse iterators.
-- Vectorization of mixed types.
-- Vectorization of function calls.
-- Partial unrolling during vectorization.
-
-The loop vectorizer is now enabled by default for -O3.
-
-SLP Vectorizer
---------------
-
-LLVM now has a new SLP vectorizer. The new SLP vectorizer is not enabled by
-default but can be enabled using the clang flag -fslp-vectorize. The BB-vectorizer
-can also be enabled using the command line flag -fslp-vectorize-aggressive.
-
-R600 Backend
-------------
-
-The R600 backend was added in this release, it supports AMD GPUs
-(HD2XXX - HD7XXX). This backend is used in AMD's Open Source
-graphics / compute drivers which are developed as part of the `Mesa3D
-<http://www.mesa3d.org>`_ project.
-
-SystemZ/s390x Backend
----------------------
-
-LLVM and clang now support IBM's z/Architecture. At present this support
-is restricted to GNU/Linux (GNU triplet s390x-linux-gnu) and requires
-z10 or greater.
-
-
-External Open Source Projects Using LLVM 3.3
+Changes to the ARM Backend
+--------------------------
+
+Since release 3.3, a lot of new features have been included in the ARM
+back-end but weren't production ready (ie. well tested) on release 3.4.
+Just after the 3.4 release, we started heavily testing two major parts
+of the back-end: the integrated assembler (IAS) and the ARM exception
+handling (EHABI), and now they are enabled by default on LLVM/Clang.
+
+The IAS received a lot of GNU extensions and directives, as well as some
+specific pre-UAL instructions. Not all remaining directives will be
+implemented, as we made judgement calls on the need versus the complexity,
+and have chosen simplicity and future compatibility where hard decisions
+had to be made. The major difference is, as stated above, the IAS validates
+all inline ASM, not just for object emission, and that cause trouble with
+some uses of inline ASM as pre-processor magic.
+
+So, while the IAS is good enough to compile large projects (including most
+of the Linux kernel), there are a few things that we can't (and probably
+won't) do. For those cases, please use ``-fno-integrated-as`` in Clang.
+
+Exception handling is another big change. After extensive testing and
+changes to cooperate with Dwarf unwinding, EHABI is enabled by default.
+The options ``-arm-enable-ehabi`` and ``-arm-enable-ehabi-descriptors``,
+which were used to enable EHABI in the previous releases, are removed now.
+
+This means all ARM code will emit EH unwind tables, or CFI unwinding (for
+debug/profiling), or both. To avoid run-time inconsistencies, C code will
+also emit EH tables (in case they interoperate with C++ code), as is the
+case for other architectures (ex. x86_64).
+
+External Open Source Projects Using LLVM 3.5
============================================
An exciting aspect of LLVM is that it is used as an enabling technology for
a lot of other language and tools projects. This section lists some of the
-projects that have already been updated to work with LLVM 3.3.
-
-
-Portable Computing Language (pocl)
-----------------------------------
-
-In addition to producing an easily portable open source OpenCL
-implementation, another major goal of `pocl <http://pocl.sourceforge.net/>`_
-is improving performance portability of OpenCL programs with
-compiler optimizations, reducing the need for target-dependent manual
-optimizations. An important part of pocl is a set of LLVM passes used to
-statically parallelize multiple work-items with the kernel compiler, even in
-the presence of work-group barriers. This enables static parallelization of
-the fine-grained static concurrency in the work groups in multiple ways.
-
-TTA-based Co-design Environment (TCE)
--------------------------------------
-
-`TCE <http://tce.cs.tut.fi/>`_ is a toolset for designing new
-processors based on the Transport triggered architecture (TTA).
-The toolset provides a complete co-design flow from C/C++
-programs down to synthesizable VHDL/Verilog and parallel program binaries.
-Processor customization points include the register files, function units,
-supported operations, and the interconnection network.
-
-TCE uses Clang and LLVM for C/C++/OpenCL C language support, target independent
-optimizations and also for parts of code generation. It generates new
-LLVM-based code generators "on the fly" for the designed TTA processors and
-loads them in to the compiler backend as runtime libraries to avoid
-per-target recompilation of larger parts of the compiler chain.
-
-Just-in-time Adaptive Decoder Engine (Jade)
--------------------------------------------
-
-`Jade <https://github.com/orcc/jade>`_ (Just-in-time Adaptive Decoder Engine)
-is a generic video decoder engine using LLVM for just-in-time compilation of
-video decoder configurations. Those configurations are designed by MPEG
-Reconfigurable Video Coding (RVC) committee. MPEG RVC standard is built on a
-stream-based dataflow representation of decoders. It is composed of a standard
-library of coding tools written in RVC-CAL language and a dataflow
-configuration --- block diagram --- of a decoder.
-
-Jade project is hosted as part of the Open RVC-CAL Compiler
-(`Orcc <http://orcc.sf.net>`_) and requires it to translate the RVC-CAL standard
-library of video coding tools into an LLVM assembly code.
+projects that have already been updated to work with LLVM 3.5.
+
Additional Information
======================
projects / oota-llvm.git / blobdiff