======================
-LLVM 3.3 Release Notes
+LLVM 3.7 Release Notes
======================
.. contents::
:local:
.. warning::
- These are in-progress notes for the upcoming LLVM 3.3 release. You may
- prefer the `LLVM 3.2 Release Notes <http://llvm.org/releases/3.2/docs
+ These are in-progress notes for the upcoming LLVM 3.7 release. You may
+ prefer the `LLVM 3.6 Release Notes <http://llvm.org/releases/3.6.0/docs
/ReleaseNotes.html>`_.
============
This document contains the release notes for the LLVM Compiler Infrastructure,
-release 3.3. Here we describe the status of LLVM, including major improvements
+release 3.7. Here we describe the status of LLVM, including major improvements
from the previous release, improvements in various subprojects of LLVM, and
some of the current users of the code. All LLVM releases may be downloaded
from the `LLVM releases web site <http://llvm.org/releases/>`_.
functionality, or simply have a lot to talk about), see the `NOTE` below
for adding a new subsection.
-* The CellSPU port has been removed. It can still be found in older versions.
+* The minimum required Visual Studio version for building LLVM is now 2013
+ Update 4.
-* The IR-level extended linker APIs (for example, to link bitcode files out of
- archives) have been removed. Any existing clients of these features should
- move to using a linker with integrated LTO support.
+* A new documentation page, :doc:`Frontend/PerformanceTips`, contains a
+ collection of tips for frontend authors on how to generate IR which LLVM is
+ able to effectively optimize.
-* LLVM and Clang's documentation has been migrated to the `Sphinx
- <http://sphinx-doc.org/>`_ documentation generation system which uses
- easy-to-write reStructuredText. See `llvm/docs/README.txt` for more
- information.
-
-* TargetTransformInfo (TTI) is a new interface that can be used by IR-level
- passes to obtain target-specific information, such as the costs of
- instructions. Only "Lowering" passes such as LSR and the vectorizer are
- allowed to use the TTI infrastructure.
-
-* We've improved the X86 and ARM cost model.
-
-* The Attributes classes have been completely rewritten and expanded. They now
- support not only enumerated attributes and alignments, but "string"
- attributes, which are useful for passing information to code generation. See
- :doc:`HowToUseAttributes` for more details.
-
-* TableGen's syntax for instruction selection patterns has been simplified.
- Instead of specifying types indirectly with register classes, you should now
- specify types directly in the input patterns. See ``SparcInstrInfo.td`` for
- examples of the new syntax. The old syntax using register classes still
- works, but it will be removed in a future LLVM release.
+* The DataLayout is no longer optional. All the IR level optimizations expects
+ it to be present and the API has been changed to use a reference instead of
+ a pointer to make it explicit. The Module owns the datalayout and it has to
+ match the one attached to the TargetMachine for generating code.
* ... next change ...
Makes programs 10x faster by doing Special New Thing.
-AArch64 target
---------------
+Changes to the ARM Backend
+--------------------------
-We've added support for AArch64, ARM's 64-bit architecture. Development is still
-in fairly early stages, but we expect successful compilation when:
+ During this release ...
-- compiling standard compliant C99 and C++03 with Clang;
-- using Linux as a target platform;
-- where code + static data doesn't exceed 4GB in size (heap allocated data has
- no limitation).
-Some additional functionality is also implemented, notably DWARF debugging,
-GNU-style thread local storage and inline assembly.
+Changes to the MIPS Target
+--------------------------
-Hexagon Target
---------------
+ During this release ...
-- Removed support for legacy hexagonv2 and hexagonv3 processor
- architectures which are no longer in use. Currently supported
- architectures are hexagonv4 and hexagonv5.
-Loop Vectorizer
----------------
+Changes to the PowerPC Target
+-----------------------------
-We've continued the work on the loop vectorizer. The loop vectorizer now
-has the following features:
+ During this release ...
-- Loops with unknown trip counts.
-- Runtime checks of pointers.
-- Reductions, Inductions.
-- Min/Max reductions of integers.
-- If Conversion.
-- Pointer induction variables.
-- Reverse iterators.
-- Vectorization of mixed types.
-- Vectorization of function calls.
-- Partial unrolling during vectorization.
-The loop vectorizer is now enabled by default for -O3.
+Changes to the OCaml bindings
+-----------------------------
-SLP Vectorizer
---------------
+ During this release ...
-LLVM now has a new SLP vectorizer. The new SLP vectorizer is not enabled by
-default but can be enabled using the clang flag -fslp-vectorize. The BB-vectorizer
-can also be enabled using the command line flag -fslp-vectorize-aggressive.
-R600 Backend
-------------
+External Open Source Projects Using LLVM 3.7
+============================================
-The R600 backend was added in this release, it supports AMD GPUs
-(HD2XXX - HD7XXX). This backend is used in AMD's Open Source
-graphics / compute drivers which are developed as part of the `Mesa3D
-<http://www.mesa3d.org>`_ project.
+An exciting aspect of LLVM is that it is used as an enabling technology for
+a lot of other language and tools projects. This section lists some of the
+projects that have already been updated to work with LLVM 3.7.
+* A project
Additional Information
projects / oota-llvm.git / blobdiff