======================
-LLVM 3.4 Release Notes
+LLVM 3.5 Release Notes
======================
.. contents::
:local:
.. warning::
- These are in-progress notes for the upcoming LLVM 3.4 release. You may
- prefer the `LLVM 3.3 Release Notes <http://llvm.org/releases/3.3/docs
+ These are in-progress notes for the upcoming LLVM 3.5 release. You may
+ prefer the `LLVM 3.4 Release Notes <http://llvm.org/releases/3.4/docs
/ReleaseNotes.html>`_.
============
This document contains the release notes for the LLVM Compiler Infrastructure,
-release 3.4. Here we describe the status of LLVM, including major improvements
+release 3.5. Here we describe the status of LLVM, including major improvements
from the previous release, improvements in various subprojects of LLVM, and
some of the current users of the code. All LLVM releases may be downloaded
from the `LLVM releases web site <http://llvm.org/releases/>`_.
Non-comprehensive list of changes in this release
=================================================
+* All backends have been changed to use the MC asm printer and support for the
+ non MC one has been removed.
+
+* Clang can now successfully self-host itself on Linux/Sparc64 and on
+ FreeBSD/Sparc64.
+
+* LLVM now assumes the assembler supports ``.loc`` for generating debug line
+ numbers. The old support for printing the debug line info directly was only
+ used by ``llc`` and has been removed.
+
+* All inline assembly is parsed by the integrated assembler when it is enabled.
+ Previously this was only the case for object-file output. It is now the case
+ for assembly output as well. The integrated assembler can be disabled with
+ the ``-no-integrated-as`` option.
+
+* llvm-ar now handles IR files like regular object files. In particular, a
+ regular symbol table is created for symbols defined in IR files, including
+ those in file scope inline assembly.
+
+* LLVM now always uses cfi directives for producing most stack
+ unwinding information.
+
+* The prefix for loop vectorizer hint metadata has been changed from
+ ``llvm.vectorizer`` to ``llvm.loop.vectorize``. In addition,
+ ``llvm.vectorizer.unroll`` metadata has been renamed
+ ``llvm.loop.interleave.count``.
+
+* Some backends previously implemented Atomic NAND(x,y) as ``x & ~y``. Now
+ all backends implement it as ``~(x & y)``, matching the semantics of GCC 4.4
+ and later.
+
.. NOTE
For small 1-3 sentence descriptions, just add an entry at the end of
this list. If your description won't fit comfortably in one bullet
functionality, or simply have a lot to talk about), see the `NOTE` below
for adding a new subsection.
-* This is expected to be the last release of LLVM which compiles using a C++98
- toolchain. We expect to start using some C++11 features in LLVM and other
- sub-projects starting after this release. That said, we are committed to
- supporting a reasonable set of modern C++ toolchains as the host compiler on
- all of the platforms. This will at least include Visual Studio 2012 on
- Windows, and Clang 3.1 or GCC 4.7.x on Mac and Linux. The final set of
- compilers (and the C++11 features they support) is not set in stone, but we
- wanted users of LLVM to have a heads up that the next release will involve
- a substantial change in the host toolchain requirements.
+* ... next change ...
-* The regression tests now fail if any command in a pipe fails. To disable it in
- a directory, just add ``config.pipefail = False`` to its ``lit.local.cfg``.
- See :doc:`Lit <CommandGuide/lit>` for the details.
+.. NOTE
+ If you would like to document a larger change, then you can add a
+ subsection about it right here. You can copy the following boilerplate
+ and un-indent it (the indentation causes it to be inside this comment).
-* Support for exception handling has been removed from the old JIT. Use MCJIT
- if you need EH support.
+ Special New Feature
+ -------------------
-* The R600 backend is not marked experimental anymore and is built by default.
+ Makes programs 10x faster by doing Special New Thing.
-* APFloat::isNormal() was renamed to APFloat::isFiniteNonZero() and
- APFloat::isIEEENormal() was renamed to APFloat::isNormal(). This ensures that
- APFloat::isNormal() conforms to IEEE-754R-2008.
+Changes to the ARM Backend
+--------------------------
+
+Since release 3.3, a lot of new features have been included in the ARM
+back-end but weren't production ready (ie. well tested) on release 3.4.
+Just after the 3.4 release, we started heavily testing two major parts
+of the back-end: the integrated assembler (IAS) and the ARM exception
+handling (EHABI), and now they are enabled by default on LLVM/Clang.
+
+The IAS received a lot of GNU extensions and directives, as well as some
+specific pre-UAL instructions. Not all remaining directives will be
+implemented, as we made judgement calls on the need versus the complexity,
+and have chosen simplicity and future compatibility where hard decisions
+had to be made. The major difference is, as stated above, the IAS validates
+all inline ASM, not just for object emission, and that cause trouble with
+some uses of inline ASM as pre-processor magic.
+
+So, while the IAS is good enough to compile large projects (including most
+of the Linux kernel), there are a few things that we can't (and probably
+won't) do. For those cases, please use ``-fno-integrated-as`` in Clang.
+
+Exception handling is another big change. After extensive testing and
+changes to cooperate with Dwarf unwinding, EHABI is enabled by default.
+The options ``-arm-enable-ehabi`` and ``-arm-enable-ehabi-descriptors``,
+which were used to enable EHABI in the previous releases, are removed now.
-* The library call simplification pass has been removed. Its functionality
- has been integrated into the instruction combiner and function attribute
- marking passes.
+This means all ARM code will emit EH unwind tables, or CFI unwinding (for
+debug/profiling), or both. To avoid run-time inconsistencies, C code will
+also emit EH tables (in case they interoperate with C++ code), as is the
+case for other architectures (ex. x86_64).
-* Support for building using Visual Studio 2008 has been dropped. Use VS 2010
- or later instead. For more information, see the `Getting Started using Visual
- Studio <GettingStartedVS.html>`_ page.
+Changes to the MIPS Target
+--------------------------
-* The Loop Vectorizer that was previously enabled for -O3 is now enabled for
- -Os and -O2.
+There has been a large amount of improvements to the MIPS target which can be
+broken down into subtarget, ABI, and Integrated Assembler changes.
-* The new SLP Vectorizer is now enabled by default.
+Subtargets
+^^^^^^^^^^
-* llvm-ar now uses the new Object library and produces archives and
- symbol tables in the gnu format.
+Added support for Release 6 of the MIPS32 and MIPS64 architecture (MIPS32r6
+and MIPS64r6). Release 6 makes a number of significant changes to the MIPS32
+and MIPS64 architectures. For example, FPU registers are always 64-bits wide,
+FPU NaN values conform to IEEE 754 (2008), and the unaligned memory instructions
+(such as lwl and lwr) have been replaced with a requirement for ordinary memory
+operations to support unaligned operations. Full details of MIPS32 and MIPS64
+Release 6 can be found on the `MIPS64 Architecture page at Imagination
+Technologies <http://www.imgtec.com/mips/architectures/mips64.asp>`_.
-* FileCheck now allows specifing -check-prefix multiple times. This
- helps reduce duplicate check lines when using multiple RUN lines.
+This release also adds experimental support for MIPS-IV, cnMIPS, and Cavium
+Octeon CPU's.
-* ... next change ...
+Support for the MIPS SIMD Architecture (MSA) has been improved to support MSA
+on MIPS64.
-.. NOTE
- If you would like to document a larger change, then you can add a
- subsection about it right here. You can copy the following boilerplate
- and un-indent it (the indentation causes it to be inside this comment).
+Support for IEEE 754 (2008) NaN values has been added.
- Special New Feature
- -------------------
+ABI and ABI extensions
+^^^^^^^^^^^^^^^^^^^^^^
- Makes programs 10x faster by doing Special New Thing.
+There has also been considerable ABI work since the 3.4 release. This release
+adds support for the N32 ABI, the O32-FPXX ABI Extension, the O32-FP64 ABI
+Extension, and the O32-FP64A ABI Extension.
+The N32 ABI is an existing ABI that has now been implemented in LLVM. It is a
+64-bit ABI that is similar to N64 but retains 32-bit pointers. N64 remains the
+default 64-bit ABI in LLVM. This differs from GCC where N32 is the default
+64-bit ABI.
-External Open Source Projects Using LLVM 3.4
-============================================
+The O32-FPXX ABI Extension is 100% compatible with the O32-ABI and the O32-FP64
+ABI Extension and may be linked with either but may not be linked with both of
+these simultaneously. It extends the O32 ABI to allow the same code to execute
+without modification on processors with 32-bit FPU registers as well as 64-bit
+FPU registers. The O32-FPXX ABI Extension is enabled by default for the O32 ABI
+on mips*-img-linux-gnu and mips*-mti-linux-gnu triples and is selected with
+-mfpxx. It is expected that future releases of LLVM will enable the FPXX
+Extension for O32 on all triples.
-An exciting aspect of LLVM is that it is used as an enabling technology for
-a lot of other language and tools projects. This section lists some of the
-projects that have already been updated to work with LLVM 3.4.
+The O32-FP64 ABI Extension is an extension to the O32 ABI to fully exploit FPU's
+with 64-bit registers and is enabled with -mfp64. This replaces an undocumented
+and unsupported O32 extension which was previously enabled with -mfp64. It is
+100% compatible with the O32-FPXX ABI Extension.
+
+The O32-FP64A ABI Extension is a restricted form of the O32-FP64 ABI Extension
+which allows interlinking with unmodified binaries that use the base O32 ABI.
+
+Integrated Assembler
+^^^^^^^^^^^^^^^^^^^^
+The MIPS Integrated Assembler has undergone a substantial overhaul including a
+rewrite of the assembly parser. It's not ready for general use in this release
+but adventurous users may wish to enable it using ``-fintegrated-as``.
-LDC - the LLVM-based D compiler
--------------------------------
+In this release, the integrated assembler supports the majority of MIPS-I,
+MIPS-II, MIPS-III, MIPS-IV, MIPS-V, MIPS32, MIPS32r2, MIPS32r6, MIPS64,
+MIPS64r2, and MIPS64r6 as well as some of the Application Specific Extensions
+such as MSA. It also supports several of the MIPS specific assembler directives
+such as ``.set``, ``.module``, ``.cpload``, etc.
-`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It
-pragmatically combines efficiency, control, and modeling power, with safety and
-programmer productivity. D supports powerful concepts like Compile-Time Function
-Execution (CTFE) and Template Meta-Programming, provides an innovative approach
-to concurrency and offers many classical paradigms.
+Changes to the PowerPC Target
+-----------------------------
+
+The PowerPC 64-bit Little Endian subtarget (powerpc64le-unknown-linux-gnu) is
+now fully supported. This includes support for the Altivec instruction set.
+
+The Power Architecture 64-Bit ELFv2 ABI Specification is now supported, and
+is the default ABI for Little Endian. The ELFv1 ABI remains the default ABI
+for Big Endian. Currently, it is not possible to override these defaults.
+That capability will be available (albeit not recommended) in a future release.
+
+Links to the ELFv2 ABI specification and to the Power ISA Version 2.07
+specification may be found `here <https://www-03.ibm.com/technologyconnect/tgcm/TGCMServlet.wss?alias=OpenPOWER&linkid=1n0000>`_ (free registration required).
+Efforts are underway to move this to a location that doesn't require
+registration, but the planned site isn't ready yet.
-`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler
-combined with LLVM as backend to produce efficient native code. LDC targets
-x86/x86_64 systems like Linux, OS X, FreeBSD and Windows and also Linux/PPC64.
-Ports to other architectures like ARM and AArch64 are underway.
+Experimental support for the VSX instruction set introduced with ISA 2.06
+is now available using the ``-mvsx`` switch. Work remains on this, so it
+is not recommended for production use. VSX is disabled for Little Endian
+regardless of this switch setting.
+
+Load/store cost estimates have been improved.
+
+Constant hoisting has been enabled.
+
+Global named register support has been enabled.
+
+Initial support for PIC code has been added for the 32-bit ELF subtarget.
+Further support will be available in a future release.
+
+External Open Source Projects Using LLVM 3.5
+============================================
+
+An exciting aspect of LLVM is that it is used as an enabling technology for
+a lot of other language and tools projects. This section lists some of the
+projects that have already been updated to work with LLVM 3.5.
Additional Information
projects / oota-llvm.git / blobdiff