+
+Changes to the ARM Backends
+---------------------------
+
+During this release the AArch64 target has:
+
+* Added support for more sanitizers (MSAN, TSAN) and made them compatible with
+ all VMA kernel configurations (currently tested on 39 and 42 bits).
+* Gained initial LLD support in the new ELF back-end
+* Extended the Load/Store optimiser and cleaned up some of the bad decisions
+ made earlier.
+* Expanded LLDB support, including watchpoints, native building, Renderscript,
+ LLDB-server, debugging 32-bit applications.
+* Added support for the ``Exynos M1`` chip.
+
+During this release the ARM target has:
+
+* Gained massive performance improvements on embedded benchmarks due to finally
+ running the stride vectorizer in full form, incrementing the performance gains
+ that we already had in the previous releases with limited stride vectorization.
+* Expanded LLDB support, including watchpoints, unwind tables
+* Extended the Load/Store optimiser and cleaned up some of the bad decisions
+ made earlier.
+* Simplified code generation for global variable addresses in ELF, resulting in
+ a significant (4% in Chromium) reduction in code size.
+* Gained some additional code size improvements, though there's still a long road
+ ahead, especially for older cores.
+* Added some EABI floating point comparison functions to Compiler-RT
+* Added support for Windows+GNU triple, +features in -mcpu/-march options.
+
+
+Changes to the MIPS Target
+--------------------------
+
+During this release the MIPS target has:
+
+* Significantly extended support for the Integrated Assembler. See below for
+ more information
+* Added support for the ``P5600`` processor.
+* Added support for the ``interrupt`` attribute for MIPS32R2 and later. This
+ attribute will generate a function which can be used as a interrupt handler
+ on bare metal MIPS targets using the static relocation model.
+* Added support for the ``ERETNC`` instruction found in MIPS32R5 and later.
+* Added support for OpenCL. See http://portablecl.org/.
+
+ * Address spaces 1 to 255 are now reserved for software use and conversions
+ between them are no-op casts.
+
+* Removed the ``mips16`` value for the -mcpu option since it is an :abbr:`ASE
+ (Application Specific Extension)` and not a processor. If you were using this,
+ please specify another CPU and use ``-mips16`` to enable MIPS16.
+* Removed ``copy_u.w`` from 32-bit MSA and ``copy_u.d`` from 64-bit MSA since
+ they have been removed from the MSA specification due to forward compatibility
+ issues. For example, 32-bit MSA code containing ``copy_u.w`` would behave
+ differently on a 64-bit processor supporting MSA. The corresponding intrinsics
+ are still available and may expand to ``copy_s.[wd]`` where this is
+ appropriate for forward compatibility purposes.
+* Relaxed the ``-mnan`` option to allow ``-mnan=2008`` on MIPS32R2/MIPS64R2 for
+ compatibility with GCC.
+* Made MIPS64R6 the default CPU for 64-bit Android triples.
+
+The MIPS target has also fixed various bugs including the following notable
+fixes:
+
+* Fixed reversed operands on ``mthi``/``mtlo`` in the DSP :abbr:`ASE
+ (Application Specific Extension)`.
+* The code generator no longer uses ``jal`` for calls to absolute immediate
+ addresses.
+* Disabled fast instruction selection on MIPS32R6 and MIPS64R6 since this is not
+ yet supported.
+* Corrected addend for ``R_MIPS_HI16`` and ``R_MIPS_PCHI16`` in MCJIT
+* The code generator no longer crashes when handling subregisters of an 64-bit
+ FPU register with undefined value.
+* The code generator no longer attempts to use ``$zero`` for operands that do
+ not permit ``$zero``.
+* Corrected the opcode used for ``ll``/``sc`` when using MIPS32R6/MIPS64R6 and
+ the Integrated Assembler.
+* Added support for atomic load and atomic store.
+* Corrected debug info when dynamically re-aligning the stack.
+
+Integrated Assembler
+^^^^^^^^^^^^^^^^^^^^
+We have made a large number of improvements to the integrated assembler for
+MIPS. In this release, the integrated assembler isn't quite production-ready
+since there are a few known issues related to bare-metal support, checking
+immediates on instructions, and the N32/N64 ABI's. However, the current support
+should be sufficient for many users of the O32 ABI, particularly those targeting
+MIPS32 on Linux or bare-metal MIPS32.
+
+If you would like to try the integrated assembler, please use
+``-fintegrated-as``.
+
+Changes to the PowerPC Target
+-----------------------------
+
+ During this release ...
+
+
+Changes to the X86 Target
+-----------------------------
+
+ During this release ...
+
+* TLS is enabled for Cygwin as emutls.
+
+* Smaller code for materializing 32-bit 1 and -1 constants at ``-Os``.
+
+* More efficient code for wide integer compares. (E.g. 64-bit compares
+ on 32-bit targets.)
+
+* Tail call support for ``thiscall``, ``stdcall``, ``vectorcall``, and
+ ``fastcall`` functions.
+
+Changes to the Hexagon Target
+-----------------------------
+
+In addition to general code size and performance improvements, Hexagon target
+now has basic support for Hexagon V60 architecture and Hexagon Vector
+Extensions (HVX).
+
+Changes to the AVR Target
+-------------------------
+
+Slightly less than half of the AVR backend has been merged in at this point. It is still
+missing a number large parts which cause it to be unusable, but is well on the
+road to being completely merged and workable.
+
+Changes to the OCaml bindings
+-----------------------------
+
+ During this release ...
+
+* The ocaml function link_modules has been replaced with link_modules' which
+ uses LLVMLinkModules2.
+
+
+External Open Source Projects Using LLVM 3.8