Fix typo noticed by 'Danny' in PR1901

[oota-llvm.git] / docs / CodeGenerator.html

diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index b454b6b9d0b9055b1dc2021cbdbf6f1936ea4d8b..7be4689562bbe37bbff0f3396ece8055a0a375e4 100644 (file)
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -719,8 +719,7 @@ comes from.</p>
 corresponds one-to-one with the LLVM function input to the instruction selector.
 In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
 a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
-<tt>MachineFunctionInfo</tt>, a <tt>SSARegMap</tt>, and a set of live in and
-live out registers for the function.  See
+<tt>MachineFunctionInfo</tt>, and a <tt>MachineRegisterInfo</tt>.  See
 <tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
 
 </div>
@@ -754,7 +753,8 @@ instruction selector.
 
 <p>Portions of the DAG instruction selector are generated from the target 
 description (<tt>*.td</tt>) files.  Our goal is for the entire instruction
-selector to be generated from these <tt>.td</tt> files.</p>
+selector to be generated from these <tt>.td</tt> files, though currently
+there are still things that require custom C++ code.</p>
 </div>
 
 <!-- _______________________________________________________________________ -->
@@ -862,7 +862,11 @@ of the code compiled (if you only get errors printed to the console while using
 this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
 your system</a> to add support for it).  The <tt>-view-sched-dags</tt> option
 views the SelectionDAG output from the Select phase and input to the Scheduler
-phase.</p>
+phase.  The <tt>-view-sunit-dags</tt> option views the ScheduleDAG, which is
+based on the final SelectionDAG, with nodes that must be scheduled as a unit
+bundled together into a single node, and with immediate operands and other
+nodes that aren't relevent for scheduling omitted.
+</p>
 
 </div>
 
@@ -1108,7 +1112,8 @@ primarily because it is a work in progress and is not yet finished:</p>
 <li>There is no great way to support matching complex addressing modes yet.  In
     the future, we will extend pattern fragments to allow them to define
     multiple values (e.g. the four operands of the <a href="#x86_memory">X86
-    addressing mode</a>).  In addition, we'll extend fragments so that a
+    addressing mode</a>, which are currently matched with custom C++ code).
+    In addition, we'll extend fragments so that a
     fragment can match multiple different patterns.</li>
 <li>We don't automatically infer flags like isStore/isLoad yet.</li>
 <li>We don't automatically generate the set of supported registers and
@@ -1307,8 +1312,8 @@ bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
                                       unsigned p_reg) {
   assert(MRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
          "Target register must be physical");
-  const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg);
-  return trc->contains(p_reg);
+  const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
+  return trc-&gt;contains(p_reg);
 }
 </pre>
 </div>
@@ -1337,7 +1342,7 @@ register. Whereas physical registers are statically defined in a
 <tt>TargetRegisterInfo.td</tt> file and cannot be created by the
 application developer, that is not the case with virtual registers.
 In order to create new virtual registers, use the method
-<tt>SSARegMap::createVirtualRegister()</tt>. This method will return a
+<tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method will return a
 virtual register with the highest code.
 </p>
 
@@ -1625,11 +1630,9 @@ are specific to the code generator for a particular target.</p>
 <div class="doc_text">
 
 <p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory.  This
-code generator currently targets a generic P6-like processor.  As such, it
-produces a few P6-and-above instructions (like conditional moves), but it does
-not make use of newer features like MMX or SSE.  In the future, the X86 backend
-will have sub-target support added for specific processor families and 
-implementations.</p>
+code generator is capable of targeting a variety of x86-32 and x86-64
+processors, and includes support for ISA extensions such as MMX and SSE.
+</p>
 
 </div>