Add LDC compiler to list of external OS projects using LLVM 3.8

[oota-llvm.git] / docs / BigEndianNEON.rst

diff --git a/docs/BigEndianNEON.rst b/docs/BigEndianNEON.rst
index 4dc1628a0ea1b3f99fa112ef4992d327a7d5c7c0..242eb0e73d2fe9daac676f011d1311a696c38ceb 100644 (file)
--- a/docs/BigEndianNEON.rst
+++ b/docs/BigEndianNEON.rst
@@ -58,7 +58,7 @@ A "little endian" layout has the least significant byte first (lowest in memory
     Big endian vector load using ``LDR``.
 
 
-A vector is a consecutive sequence of items that are operated on simultaneously. To load a 64-bit vector, 64 bits need to be read from memory. In little endian mode, we can do this by just performing a 64-bit load - ``LDR q0, [foo]``. However if we try this in big endian mode, because of the byte swapping the lane indices end up being swapped! The zero'th item as layed out in memory becomes the n'th lane in the vector.
+A vector is a consecutive sequence of items that are operated on simultaneously. To load a 64-bit vector, 64 bits need to be read from memory. In little endian mode, we can do this by just performing a 64-bit load - ``LDR q0, [foo]``. However if we try this in big endian mode, because of the byte swapping the lane indices end up being swapped! The zero'th item as laid out in memory becomes the n'th lane in the vector.
 
 .. figure:: ARM-BE-ld1.png
     :align: right