[IR] Limit bits used for CallingConv::ID, update tests

[oota-llvm.git] / docs / Atomics.rst

diff --git a/docs/Atomics.rst b/docs/Atomics.rst
index d035bac8d8d1dfdf5dfd072799759bf71995808b..79ab74792dd476fd83fdfc83044d29b57d88d6ee 100644 (file)
--- a/docs/Atomics.rst
+++ b/docs/Atomics.rst
@@ -173,7 +173,7 @@ Notes for code generation
   also expected to generate an i8 store as an i8 store, and not an instruction
   which writes to surrounding bytes.  (If you are writing a backend for an
   architecture which cannot satisfy these restrictions and cares about
-  concurrency, please send an email to llvmdev.)
+  concurrency, please send an email to llvm-dev.)
 
 Unordered
 ---------
@@ -444,8 +444,9 @@ on ARM, etc.).
 
 It is often easiest for backends to use AtomicExpandPass to lower some of the
 atomic constructs. Here are some lowerings it can do:
+
 * cmpxchg -> loop with load-linked/store-conditional
-  by overriding ``hasLoadLinkedStoreConditional()``, ``emitLoadLinked()``,
+  by overriding ``shouldExpandAtomicCmpXchgInIR()``, ``emitLoadLinked()``,
   ``emitStoreConditional()``
 * large loads/stores -> ll-sc/cmpxchg
   by overriding ``shouldExpandAtomicStoreInIR()``/``shouldExpandAtomicLoadInIR()``
@@ -454,4 +455,5 @@ atomic constructs. Here are some lowerings it can do:
   and ``emitTrailingFence()``
 * atomic rmw -> loop with cmpxchg or load-linked/store-conditional
   by overriding ``expandAtomicRMWInIR()``
+
 For an example of all of these, look at the ARM backend.