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MCSchedule.h: fix VS2012 build after r216919
[oota-llvm.git]
/
CREDITS.TXT
diff --git
a/CREDITS.TXT
b/CREDITS.TXT
index 195d7d139e6ae037c55459fc3c07977a98374f26..40d67f4f2dce46a6d215094a8847a65a91488a14 100644
(file)
--- a/
CREDITS.TXT
+++ b/
CREDITS.TXT
@@
-107,6
+107,10
@@
N: Rafael Avila de Espindola
E: rafael.espindola@gmail.com
D: The ARM backend
E: rafael.espindola@gmail.com
D: The ARM backend
+N: Dave Estes
+E: cestes@codeaurora.org
+D: AArch64 machine description for Cortex-A53
+
N: Alkis Evlogimenos
E: alkis@evlogimenos.com
D: Linear scan register allocator, many codegen improvements, Java frontend
N: Alkis Evlogimenos
E: alkis@evlogimenos.com
D: Linear scan register allocator, many codegen improvements, Java frontend
@@
-115,6
+119,10
@@
N: Hal Finkel
E: hfinkel@anl.gov
D: Basic-block autovectorization, PowerPC backend improvements
E: hfinkel@anl.gov
D: Basic-block autovectorization, PowerPC backend improvements
+N: Eric Fiselier
+E: eric@efcs.ca
+D: LIT patches and documentation.
+
N: Ryan Flynn
E: pizza@parseerror.com
D: Miscellaneous bug fixes
N: Ryan Flynn
E: pizza@parseerror.com
D: Miscellaneous bug fixes
@@
-132,6
+140,7
@@
W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
D: PPC backend fixes for Linux
N: Louis Gerbarg
D: PPC backend fixes for Linux
N: Louis Gerbarg
+E: lgg@apple.com
D: Portions of the PowerPC backend
N: Saem Ghani
D: Portions of the PowerPC backend
N: Saem Ghani
@@
-161,10
+170,12
@@
D: Improvements for space efficiency
N: James Grosbach
E: grosbach@apple.com
N: James Grosbach
E: grosbach@apple.com
+I: grosbach
D: SjLj exception handling support
D: General fixes and improvements for the ARM back-end
D: MCJIT
D: ARM integrated assembler and assembly parser
D: SjLj exception handling support
D: General fixes and improvements for the ARM back-end
D: MCJIT
D: ARM integrated assembler and assembly parser
+D: Led effort for the backend formerly known as ARM64
N: Lang Hames
E: lhames@gmail.com
N: Lang Hames
E: lhames@gmail.com
@@
-251,6
+262,13
@@
D: The initial llvm-ar tool, converted regression testsuite to dejagnu
D: Modulo scheduling in the SparcV9 backend
D: Release manager (1.7+)
D: Modulo scheduling in the SparcV9 backend
D: Release manager (1.7+)
+N: Sylvestre Ledru
+E: sylvestre@debian.org
+W: http://sylvestre.ledru.info/
+W: http://llvm.org/apt/
+D: Debian and Ubuntu packaging
+D: Continuous integration with jenkins
+
N: Andrew Lenharth
E: alenhar2@cs.uiuc.edu
W: http://www.lenharth.org/~andrewl/
N: Andrew Lenharth
E: alenhar2@cs.uiuc.edu
W: http://www.lenharth.org/~andrewl/
@@
-267,8
+285,11
@@
D: Backend for Qualcomm's Hexagon VLIW processor.
N: Bruno Cardoso Lopes
E: bruno.cardoso@gmail.com
N: Bruno Cardoso Lopes
E: bruno.cardoso@gmail.com
-W: http://www.brunocardoso.org
-D: The Mips backend
+I: bruno
+W: http://brunocardoso.cc
+D: Mips backend
+D: Random ARM integrated assembler and assembly parser improvements
+D: General X86 AVX1 support
N: Duraid Madina
E: duraid@octopus.com.au
N: Duraid Madina
E: duraid@octopus.com.au
@@
-294,6
+315,7
@@
D: Added STI Cell SPU backend.
N: Kai Nacke
E: kai@redstar.de
D: Support for implicit TLS model used with MS VC runtime
N: Kai Nacke
E: kai@redstar.de
D: Support for implicit TLS model used with MS VC runtime
+D: Dumping of Win64 EH structures
N: Takumi Nakamura
E: geek4civic@gmail.com
N: Takumi Nakamura
E: geek4civic@gmail.com
@@
-330,6
+352,10
@@
D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
D: Optimizer improvements, Loop Index Split
D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
D: Optimizer improvements, Loop Index Split
+N: Ana Pazos
+E: apazos@codeaurora.org
+D: Fixes and improvements to the AArch64 backend
+
N: Wesley Peck
E: peckw@wesleypeck.com
W: http://wesleypeck.com/
N: Wesley Peck
E: peckw@wesleypeck.com
W: http://wesleypeck.com/
@@
-358,9
+384,11
@@
I: arosenberg
D: ARM calling conventions rewrite, hard float support
N: Chad Rosier
D: ARM calling conventions rewrite, hard float support
N: Chad Rosier
-E: mcrosier@apple.com
-D: ARM fast-isel improvements
-D: Performance monitoring
+E: mcrosier@codeaurora.org
+I: mcrosier
+D: AArch64 fast instruction selection pass
+D: Fixes and improvements to the ARM fast-isel pass
+D: Fixes and improvements to the AArch64 backend
N: Nadav Rotem
E: nrotem@apple.com
N: Nadav Rotem
E: nrotem@apple.com
@@
-404,6
+432,11
@@
E: rspencer@reidspencer.com
W: http://reidspencer.com/
D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
W: http://reidspencer.com/
D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
+N: Alp Toker
+E: alp@nuanti.com
+W: http://atoker.com/
+D: C++ frontend next generation standards implementation
+
N: Craig Topper
E: craig.topper@gmail.com
D: X86 codegen and disassembler improvements. AVX2 support.
N: Craig Topper
E: craig.topper@gmail.com
D: X86 codegen and disassembler improvements. AVX2 support.
@@
-422,10
+455,12
@@
D: ARM backend improvements
D: Thread Local Storage implementation
N: Bill Wendling
D: Thread Local Storage implementation
N: Bill Wendling
-E: wendling@apple.com
-D: Release manager
+I: wendling
+E: isanbard@gmail.com
+D: Release manager, IR Linker, LTO
D: Bunches of stuff
N: Bob Wilson
E: bob.wilson@acm.org
D: Bunches of stuff
N: Bob Wilson
E: bob.wilson@acm.org
-D: Advanced SIMD (NEON) support in the ARM backend
+D: Advanced SIMD (NEON) support in the ARM backend.
+