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[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH instructions.
[oota-llvm.git]
/
CODE_OWNERS.TXT
diff --git
a/CODE_OWNERS.TXT
b/CODE_OWNERS.TXT
index 369aba1307b9ff42c862513dc885bcc7450cb762..86d401ee4498c78a33f9241f93f750f09482a8dc 100644
(file)
--- a/
CODE_OWNERS.TXT
+++ b/
CODE_OWNERS.TXT
@@
-29,6
+29,10
@@
N: Evan Cheng
E: evan.cheng@apple.com
D: ARM target, parts of code generator not covered by someone else
E: evan.cheng@apple.com
D: ARM target, parts of code generator not covered by someone else
+N: Renato Golin
+E: renato.golin@linaro.org
+D: ARM Linux support
+
N: Eric Christopher
E: echristo@gmail.com
D: Debug Information, autotools/configure/make build, inline assembly
N: Eric Christopher
E: echristo@gmail.com
D: Debug Information, autotools/configure/make build, inline assembly
@@
-45,7
+49,7
@@
D: Hexagon Backend
N: Hal Finkel
E: hfinkel@anl.gov
N: Hal Finkel
E: hfinkel@anl.gov
-D: BBVectorize and the PowerPC target
+D: BBVectorize
, the loop reroller
and the PowerPC target
N: Venkatraman Govindaraju
E: venkatra@cs.wisc.edu
N: Venkatraman Govindaraju
E: venkatra@cs.wisc.edu
@@
-58,15
+62,16
@@
N: James Grosbach
E: grosbach@apple.com
D: MC layer
E: grosbach@apple.com
D: MC layer
-N: Howard Hinnant
+N: Marshall Clow
+E: mclow.lists@gmail.com
D: libc++
N: Justin Holewinski
E: jholewinski@nvidia.com
D: NVPTX Target (lib/Target/NVPTX/*)
D: libc++
N: Justin Holewinski
E: jholewinski@nvidia.com
D: NVPTX Target (lib/Target/NVPTX/*)
-N:
Andy Kaylor
-E:
andrew.kaylor@inte
l.com
+N:
Lang Hames
+E:
lhames@gmai
l.com
D: MCJIT, RuntimeDyld and JIT event listeners
N: Galina Kistanova
D: MCJIT, RuntimeDyld and JIT event listeners
N: Galina Kistanova
@@
-91,7
+96,7
@@
W: http://nondot.org/~sabre/
D: Everything not covered by someone else
N: Tim Northover
D: Everything not covered by someone else
N: Tim Northover
-E:
Tim.Northover@arm
.com
+E:
t.p.northover@gmail
.com
D: AArch64 backend
N: Jakob Olesen
D: AArch64 backend
N: Jakob Olesen
@@
-102,13
+107,17
@@
E: richard@xmos.com
D: XCore Backend
N: Chad Rosier
D: XCore Backend
N: Chad Rosier
-E: mcrosier@
apple.com
+E: mcrosier@
codeaurora.org
D: Fast-Isel
N: Nadav Rotem
E: nrotem@apple.com
D: X86 Backend, Loop Vectorizer
D: Fast-Isel
N: Nadav Rotem
E: nrotem@apple.com
D: X86 Backend, Loop Vectorizer
+N: Daniel Sanders
+E: daniel.sanders@imgtec.com
+D: MIPS Backend (lib/Target/Mips/*)
+
N: Richard Sandiford
E: rsandifo@linux.vnet.ibm.com
D: SystemZ Backend
N: Richard Sandiford
E: rsandifo@linux.vnet.ibm.com
D: SystemZ Backend
@@
-139,5
+148,9
@@
E: atrick@apple.com
D: IndVar Simplify, Loop Strength Reduction, Instruction Scheduling
N: Bill Wendling
D: IndVar Simplify, Loop Strength Reduction, Instruction Scheduling
N: Bill Wendling
-E:
wendling@apple
.com
+E:
isanbard@gmail
.com
D: libLTO, IR Linker
D: libLTO, IR Linker
+
+N: Peter Zotov
+E: whitequark@whitequark.org
+D: OCaml bindings