1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
233 SegOvr = byteFromRec(Rec, "SegOvrBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
248 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
249 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
250 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
251 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
253 Name = Rec->getName();
254 AsmString = Rec->getValueAsString("AsmString");
256 Operands = &insn.Operands.OperandList;
258 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
259 (Name.find("CRC32") != Name.npos);
260 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
262 // Check for 64-bit inst which does not require REX
265 // FIXME: Is there some better way to check for In64BitMode?
266 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
267 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
268 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
269 Predicates[i]->getName().find("In32Bit") != Name.npos) {
273 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
279 ShouldBeEmitted = true;
282 void RecognizableInstr::processInstr(DisassemblerTables &tables,
283 const CodeGenInstruction &insn,
286 // Ignore "asm parser only" instructions.
287 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
290 RecognizableInstr recogInstr(tables, insn, uid);
292 recogInstr.emitInstructionSpecifier();
294 if (recogInstr.shouldBeEmitted())
295 recogInstr.emitDecodePath(tables);
298 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
299 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
300 (HasEVEX_KZ ? n##_KZ : \
301 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
303 InstructionContext RecognizableInstr::insnContext() const {
304 InstructionContext insnContext;
307 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
308 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
309 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
312 if (HasVEX_LPrefix && HasVEX_WPrefix) {
314 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
315 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
316 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
317 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
318 Prefix == X86Local::TAXD)
319 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
321 insnContext = EVEX_KB(IC_EVEX_L_W);
322 } else if (HasVEX_LPrefix) {
325 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
326 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
327 insnContext = EVEX_KB(IC_EVEX_L_XS);
328 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
329 Prefix == X86Local::TAXD)
330 insnContext = EVEX_KB(IC_EVEX_L_XD);
332 insnContext = EVEX_KB(IC_EVEX_L);
334 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
337 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
338 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
339 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
340 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
341 Prefix == X86Local::TAXD)
342 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
344 insnContext = EVEX_KB(IC_EVEX_L2_W);
345 } else if (HasEVEX_L2Prefix) {
348 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
349 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
350 Prefix == X86Local::TAXD)
351 insnContext = EVEX_KB(IC_EVEX_L2_XD);
352 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
353 insnContext = EVEX_KB(IC_EVEX_L2_XS);
355 insnContext = EVEX_KB(IC_EVEX_L2);
357 else if (HasVEX_WPrefix) {
360 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
361 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
362 insnContext = EVEX_KB(IC_EVEX_W_XS);
363 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
364 Prefix == X86Local::TAXD)
365 insnContext = EVEX_KB(IC_EVEX_W_XD);
367 insnContext = EVEX_KB(IC_EVEX_W);
370 else if (HasOpSizePrefix)
371 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
372 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
373 Prefix == X86Local::TAXD)
374 insnContext = EVEX_KB(IC_EVEX_XD);
375 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
376 insnContext = EVEX_KB(IC_EVEX_XS);
378 insnContext = EVEX_KB(IC_EVEX);
380 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
381 if (HasVEX_LPrefix && HasVEX_WPrefix) {
383 insnContext = IC_VEX_L_W_OPSIZE;
384 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
385 insnContext = IC_VEX_L_W_XS;
386 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
387 Prefix == X86Local::TAXD)
388 insnContext = IC_VEX_L_W_XD;
390 insnContext = IC_VEX_L_W;
391 } else if (HasOpSizePrefix && HasVEX_LPrefix)
392 insnContext = IC_VEX_L_OPSIZE;
393 else if (HasOpSizePrefix && HasVEX_WPrefix)
394 insnContext = IC_VEX_W_OPSIZE;
395 else if (HasOpSizePrefix)
396 insnContext = IC_VEX_OPSIZE;
397 else if (HasVEX_LPrefix &&
398 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
399 insnContext = IC_VEX_L_XS;
400 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
401 Prefix == X86Local::T8XD ||
402 Prefix == X86Local::TAXD))
403 insnContext = IC_VEX_L_XD;
404 else if (HasVEX_WPrefix &&
405 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
406 insnContext = IC_VEX_W_XS;
407 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
408 Prefix == X86Local::T8XD ||
409 Prefix == X86Local::TAXD))
410 insnContext = IC_VEX_W_XD;
411 else if (HasVEX_WPrefix)
412 insnContext = IC_VEX_W;
413 else if (HasVEX_LPrefix)
414 insnContext = IC_VEX_L;
415 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
416 Prefix == X86Local::TAXD)
417 insnContext = IC_VEX_XD;
418 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
419 insnContext = IC_VEX_XS;
421 insnContext = IC_VEX;
422 } else if (Is64Bit || HasREX_WPrefix) {
423 if (HasREX_WPrefix && HasOpSizePrefix)
424 insnContext = IC_64BIT_REXW_OPSIZE;
425 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
426 Prefix == X86Local::T8XD ||
427 Prefix == X86Local::TAXD))
428 insnContext = IC_64BIT_XD_OPSIZE;
429 else if (HasOpSizePrefix &&
430 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
431 insnContext = IC_64BIT_XS_OPSIZE;
432 else if (HasOpSizePrefix)
433 insnContext = IC_64BIT_OPSIZE;
434 else if (HasAdSizePrefix)
435 insnContext = IC_64BIT_ADSIZE;
436 else if (HasREX_WPrefix &&
437 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
438 insnContext = IC_64BIT_REXW_XS;
439 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
440 Prefix == X86Local::T8XD ||
441 Prefix == X86Local::TAXD))
442 insnContext = IC_64BIT_REXW_XD;
443 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
444 Prefix == X86Local::TAXD)
445 insnContext = IC_64BIT_XD;
446 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
447 insnContext = IC_64BIT_XS;
448 else if (HasREX_WPrefix)
449 insnContext = IC_64BIT_REXW;
451 insnContext = IC_64BIT;
453 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
454 Prefix == X86Local::T8XD ||
455 Prefix == X86Local::TAXD))
456 insnContext = IC_XD_OPSIZE;
457 else if (HasOpSizePrefix &&
458 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
459 insnContext = IC_XS_OPSIZE;
460 else if (HasOpSizePrefix)
461 insnContext = IC_OPSIZE;
462 else if (HasAdSizePrefix)
463 insnContext = IC_ADSIZE;
464 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
465 Prefix == X86Local::TAXD)
467 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
468 Prefix == X86Local::REP)
477 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
482 // Filter out intrinsics
484 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
486 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
487 return FILTER_STRONG;
490 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
491 // printed as a separate "instruction".
493 // Filter out instructions with segment override prefixes.
494 // They're too messy to handle now and we'll special case them if needed.
497 return FILTER_STRONG;
505 // Filter out instructions with a LOCK prefix;
506 // prefer forms that do not have the prefix
510 // Filter out alternate forms of AVX instructions
511 if ((Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
512 Name.find("_64mr") != Name.npos ||
513 Name.find("rr64") != Name.npos)
518 if (Name == "PUSH64i16" ||
519 Name == "MOVPQI2QImr" ||
520 Name == "VMOVPQI2QImr" ||
521 Name == "VMASKMOVDQU64")
524 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
525 // For now, just prefer the REP versions.
526 if (Name == "XACQUIRE_PREFIX" ||
527 Name == "XRELEASE_PREFIX")
530 return FILTER_NORMAL;
533 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
534 unsigned &physicalOperandIndex,
535 unsigned &numPhysicalOperands,
536 const unsigned *operandMapping,
537 OperandEncoding (*encodingFromString)
539 bool hasOpSizePrefix)) {
541 if (physicalOperandIndex >= numPhysicalOperands)
544 assert(physicalOperandIndex < numPhysicalOperands);
547 while (operandMapping[operandIndex] != operandIndex) {
548 Spec->operands[operandIndex].encoding = ENCODING_DUP;
549 Spec->operands[operandIndex].type =
550 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
554 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
556 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
558 Spec->operands[operandIndex].type = typeFromString(typeName,
564 ++physicalOperandIndex;
567 void RecognizableInstr::emitInstructionSpecifier() {
570 if (!ShouldBeEmitted)
575 Spec->filtered = true;
578 ShouldBeEmitted = false;
584 Spec->insnContext = insnContext();
586 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
588 unsigned numOperands = OperandList.size();
589 unsigned numPhysicalOperands = 0;
591 // operandMapping maps from operands in OperandList to their originals.
592 // If operandMapping[i] != i, then the entry is a duplicate.
593 unsigned operandMapping[X86_MAX_OPERANDS];
594 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
596 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
597 if (OperandList[operandIndex].Constraints.size()) {
598 const CGIOperandList::ConstraintInfo &Constraint =
599 OperandList[operandIndex].Constraints[0];
600 if (Constraint.isTied()) {
601 operandMapping[operandIndex] = operandIndex;
602 operandMapping[Constraint.getTiedOperand()] = operandIndex;
604 ++numPhysicalOperands;
605 operandMapping[operandIndex] = operandIndex;
608 ++numPhysicalOperands;
609 operandMapping[operandIndex] = operandIndex;
613 #define HANDLE_OPERAND(class) \
614 handleOperand(false, \
616 physicalOperandIndex, \
617 numPhysicalOperands, \
619 class##EncodingFromString);
621 #define HANDLE_OPTIONAL(class) \
622 handleOperand(true, \
624 physicalOperandIndex, \
625 numPhysicalOperands, \
627 class##EncodingFromString);
629 // operandIndex should always be < numOperands
630 unsigned operandIndex = 0;
631 // physicalOperandIndex should always be < numPhysicalOperands
632 unsigned physicalOperandIndex = 0;
635 case X86Local::RawFrm:
636 // Operand 1 (optional) is an address or immediate.
637 // Operand 2 (optional) is an immediate.
638 assert(numPhysicalOperands <= 2 &&
639 "Unexpected number of operands for RawFrm");
640 HANDLE_OPTIONAL(relocation)
641 HANDLE_OPTIONAL(immediate)
643 case X86Local::AddRegFrm:
644 // Operand 1 is added to the opcode.
645 // Operand 2 (optional) is an address.
646 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
647 "Unexpected number of operands for AddRegFrm");
648 HANDLE_OPERAND(opcodeModifier)
649 HANDLE_OPTIONAL(relocation)
651 case X86Local::MRMDestReg:
652 // Operand 1 is a register operand in the R/M field.
653 // Operand 2 is a register operand in the Reg/Opcode field.
654 // - In AVX, there is a register operand in the VEX.vvvv field here -
655 // Operand 3 (optional) is an immediate.
657 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
658 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
660 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
661 "Unexpected number of operands for MRMDestRegFrm");
663 HANDLE_OPERAND(rmRegister)
666 // FIXME: In AVX, the register below becomes the one encoded
667 // in ModRMVEX and the one above the one in the VEX.VVVV field
668 HANDLE_OPERAND(vvvvRegister)
670 HANDLE_OPERAND(roRegister)
671 HANDLE_OPTIONAL(immediate)
673 case X86Local::MRMDestMem:
674 // Operand 1 is a memory operand (possibly SIB-extended)
675 // Operand 2 is a register operand in the Reg/Opcode field.
676 // - In AVX, there is a register operand in the VEX.vvvv field here -
677 // Operand 3 (optional) is an immediate.
679 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
680 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
682 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
683 "Unexpected number of operands for MRMDestMemFrm");
684 HANDLE_OPERAND(memory)
687 HANDLE_OPERAND(writemaskRegister)
690 // FIXME: In AVX, the register below becomes the one encoded
691 // in ModRMVEX and the one above the one in the VEX.VVVV field
692 HANDLE_OPERAND(vvvvRegister)
694 HANDLE_OPERAND(roRegister)
695 HANDLE_OPTIONAL(immediate)
697 case X86Local::MRMSrcReg:
698 // Operand 1 is a register operand in the Reg/Opcode field.
699 // Operand 2 is a register operand in the R/M field.
700 // - In AVX, there is a register operand in the VEX.vvvv field here -
701 // Operand 3 (optional) is an immediate.
702 // Operand 4 (optional) is an immediate.
704 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
705 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
706 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
708 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
709 "Unexpected number of operands for MRMSrcRegFrm");
711 HANDLE_OPERAND(roRegister)
714 HANDLE_OPERAND(writemaskRegister)
717 // FIXME: In AVX, the register below becomes the one encoded
718 // in ModRMVEX and the one above the one in the VEX.VVVV field
719 HANDLE_OPERAND(vvvvRegister)
722 HANDLE_OPERAND(immediate)
724 HANDLE_OPERAND(rmRegister)
726 if (HasVEX_4VOp3Prefix)
727 HANDLE_OPERAND(vvvvRegister)
729 if (!HasMemOp4Prefix)
730 HANDLE_OPTIONAL(immediate)
731 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
732 HANDLE_OPTIONAL(immediate)
734 case X86Local::MRMSrcMem:
735 // Operand 1 is a register operand in the Reg/Opcode field.
736 // Operand 2 is a memory operand (possibly SIB-extended)
737 // - In AVX, there is a register operand in the VEX.vvvv field here -
738 // Operand 3 (optional) is an immediate.
740 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
741 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
742 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
744 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
745 "Unexpected number of operands for MRMSrcMemFrm");
747 HANDLE_OPERAND(roRegister)
750 HANDLE_OPERAND(writemaskRegister)
753 // FIXME: In AVX, the register below becomes the one encoded
754 // in ModRMVEX and the one above the one in the VEX.VVVV field
755 HANDLE_OPERAND(vvvvRegister)
758 HANDLE_OPERAND(immediate)
760 HANDLE_OPERAND(memory)
762 if (HasVEX_4VOp3Prefix)
763 HANDLE_OPERAND(vvvvRegister)
765 if (!HasMemOp4Prefix)
766 HANDLE_OPTIONAL(immediate)
767 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
769 case X86Local::MRM0r:
770 case X86Local::MRM1r:
771 case X86Local::MRM2r:
772 case X86Local::MRM3r:
773 case X86Local::MRM4r:
774 case X86Local::MRM5r:
775 case X86Local::MRM6r:
776 case X86Local::MRM7r:
778 // Operand 1 is a register operand in the R/M field.
779 // Operand 2 (optional) is an immediate or relocation.
780 // Operand 3 (optional) is an immediate.
781 unsigned kOp = (HasEVEX_K) ? 1:0;
782 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
783 if (numPhysicalOperands > 3 + kOp + Op4v)
784 llvm_unreachable("Unexpected number of operands for MRMnr");
787 HANDLE_OPERAND(vvvvRegister)
790 HANDLE_OPERAND(writemaskRegister)
791 HANDLE_OPTIONAL(rmRegister)
792 HANDLE_OPTIONAL(relocation)
793 HANDLE_OPTIONAL(immediate)
795 case X86Local::MRM0m:
796 case X86Local::MRM1m:
797 case X86Local::MRM2m:
798 case X86Local::MRM3m:
799 case X86Local::MRM4m:
800 case X86Local::MRM5m:
801 case X86Local::MRM6m:
802 case X86Local::MRM7m:
804 // Operand 1 is a memory operand (possibly SIB-extended)
805 // Operand 2 (optional) is an immediate or relocation.
806 unsigned kOp = (HasEVEX_K) ? 1:0;
807 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
808 if (numPhysicalOperands < 1 + kOp + Op4v ||
809 numPhysicalOperands > 2 + kOp + Op4v)
810 llvm_unreachable("Unexpected number of operands for MRMnm");
813 HANDLE_OPERAND(vvvvRegister)
815 HANDLE_OPERAND(writemaskRegister)
816 HANDLE_OPERAND(memory)
817 HANDLE_OPTIONAL(relocation)
819 case X86Local::RawFrmImm8:
820 // operand 1 is a 16-bit immediate
821 // operand 2 is an 8-bit immediate
822 assert(numPhysicalOperands == 2 &&
823 "Unexpected number of operands for X86Local::RawFrmImm8");
824 HANDLE_OPERAND(immediate)
825 HANDLE_OPERAND(immediate)
827 case X86Local::RawFrmImm16:
828 // operand 1 is a 16-bit immediate
829 // operand 2 is a 16-bit immediate
830 HANDLE_OPERAND(immediate)
831 HANDLE_OPERAND(immediate)
833 case X86Local::MRM_F8:
834 if (Opcode == 0xc6) {
835 assert(numPhysicalOperands == 1 &&
836 "Unexpected number of operands for X86Local::MRM_F8");
837 HANDLE_OPERAND(immediate)
838 } else if (Opcode == 0xc7) {
839 assert(numPhysicalOperands == 1 &&
840 "Unexpected number of operands for X86Local::MRM_F8");
841 HANDLE_OPERAND(relocation)
844 case X86Local::MRMInitReg:
849 #undef HANDLE_OPERAND
850 #undef HANDLE_OPTIONAL
853 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
854 // Special cases where the LLVM tables are not complete
856 #define MAP(from, to) \
857 case X86Local::MRM_##from: \
858 filter = new ExactFilter(0x##from); \
861 OpcodeType opcodeType = (OpcodeType)-1;
863 ModRMFilter* filter = NULL;
864 uint8_t opcodeToSet = 0;
867 default: llvm_unreachable("Invalid prefix!");
868 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
872 opcodeType = TWOBYTE;
876 if (needsModRMForDecode(Form))
877 filter = new ModFilter(isRegFormat(Form));
879 filter = new DumbFilter();
881 #define EXTENSION_TABLE(n) case 0x##n:
882 TWO_BYTE_EXTENSION_TABLES
883 #undef EXTENSION_TABLE
886 llvm_unreachable("Unhandled two-byte extended opcode");
887 case X86Local::MRM0r:
888 case X86Local::MRM1r:
889 case X86Local::MRM2r:
890 case X86Local::MRM3r:
891 case X86Local::MRM4r:
892 case X86Local::MRM5r:
893 case X86Local::MRM6r:
894 case X86Local::MRM7r:
895 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
897 case X86Local::MRM0m:
898 case X86Local::MRM1m:
899 case X86Local::MRM2m:
900 case X86Local::MRM3m:
901 case X86Local::MRM4m:
902 case X86Local::MRM5m:
903 case X86Local::MRM6m:
904 case X86Local::MRM7m:
905 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
911 opcodeToSet = Opcode;
916 opcodeType = THREEBYTE_38;
919 if (needsModRMForDecode(Form))
920 filter = new ModFilter(isRegFormat(Form));
922 filter = new DumbFilter();
924 #define EXTENSION_TABLE(n) case 0x##n:
925 THREE_BYTE_38_EXTENSION_TABLES
926 #undef EXTENSION_TABLE
929 llvm_unreachable("Unhandled two-byte extended opcode");
930 case X86Local::MRM0r:
931 case X86Local::MRM1r:
932 case X86Local::MRM2r:
933 case X86Local::MRM3r:
934 case X86Local::MRM4r:
935 case X86Local::MRM5r:
936 case X86Local::MRM6r:
937 case X86Local::MRM7r:
938 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
940 case X86Local::MRM0m:
941 case X86Local::MRM1m:
942 case X86Local::MRM2m:
943 case X86Local::MRM3m:
944 case X86Local::MRM4m:
945 case X86Local::MRM5m:
946 case X86Local::MRM6m:
947 case X86Local::MRM7m:
948 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
954 opcodeToSet = Opcode;
958 opcodeType = THREEBYTE_3A;
959 if (needsModRMForDecode(Form))
960 filter = new ModFilter(isRegFormat(Form));
962 filter = new DumbFilter();
963 opcodeToSet = Opcode;
966 opcodeType = THREEBYTE_A6;
967 if (needsModRMForDecode(Form))
968 filter = new ModFilter(isRegFormat(Form));
970 filter = new DumbFilter();
971 opcodeToSet = Opcode;
974 opcodeType = THREEBYTE_A7;
975 if (needsModRMForDecode(Form))
976 filter = new ModFilter(isRegFormat(Form));
978 filter = new DumbFilter();
979 opcodeToSet = Opcode;
982 opcodeType = XOP8_MAP;
983 if (needsModRMForDecode(Form))
984 filter = new ModFilter(isRegFormat(Form));
986 filter = new DumbFilter();
987 opcodeToSet = Opcode;
990 opcodeType = XOP9_MAP;
993 if (needsModRMForDecode(Form))
994 filter = new ModFilter(isRegFormat(Form));
996 filter = new DumbFilter();
998 #define EXTENSION_TABLE(n) case 0x##n:
999 XOP9_MAP_EXTENSION_TABLES
1000 #undef EXTENSION_TABLE
1003 llvm_unreachable("Unhandled XOP9 extended opcode");
1004 case X86Local::MRM0r:
1005 case X86Local::MRM1r:
1006 case X86Local::MRM2r:
1007 case X86Local::MRM3r:
1008 case X86Local::MRM4r:
1009 case X86Local::MRM5r:
1010 case X86Local::MRM6r:
1011 case X86Local::MRM7r:
1012 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1014 case X86Local::MRM0m:
1015 case X86Local::MRM1m:
1016 case X86Local::MRM2m:
1017 case X86Local::MRM3m:
1018 case X86Local::MRM4m:
1019 case X86Local::MRM5m:
1020 case X86Local::MRM6m:
1021 case X86Local::MRM7m:
1022 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1027 } // switch (Opcode)
1028 opcodeToSet = Opcode;
1030 case X86Local::XOPA:
1031 opcodeType = XOPA_MAP;
1032 if (needsModRMForDecode(Form))
1033 filter = new ModFilter(isRegFormat(Form));
1035 filter = new DumbFilter();
1036 opcodeToSet = Opcode;
1046 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1047 assert(Form == X86Local::RawFrm);
1048 opcodeType = ONEBYTE;
1049 filter = new ExactFilter(Opcode);
1050 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1054 opcodeType = ONEBYTE;
1056 #define EXTENSION_TABLE(n) case 0x##n:
1057 ONE_BYTE_EXTENSION_TABLES
1058 #undef EXTENSION_TABLE
1061 llvm_unreachable("Fell through the cracks of a single-byte "
1063 case X86Local::MRM0r:
1064 case X86Local::MRM1r:
1065 case X86Local::MRM2r:
1066 case X86Local::MRM3r:
1067 case X86Local::MRM4r:
1068 case X86Local::MRM5r:
1069 case X86Local::MRM6r:
1070 case X86Local::MRM7r:
1071 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1073 case X86Local::MRM0m:
1074 case X86Local::MRM1m:
1075 case X86Local::MRM2m:
1076 case X86Local::MRM3m:
1077 case X86Local::MRM4m:
1078 case X86Local::MRM5m:
1079 case X86Local::MRM6m:
1080 case X86Local::MRM7m:
1081 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1096 llvm_unreachable("Unhandled escape opcode form");
1097 case X86Local::MRM0r:
1098 case X86Local::MRM1r:
1099 case X86Local::MRM2r:
1100 case X86Local::MRM3r:
1101 case X86Local::MRM4r:
1102 case X86Local::MRM5r:
1103 case X86Local::MRM6r:
1104 case X86Local::MRM7r:
1105 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1107 case X86Local::MRM0m:
1108 case X86Local::MRM1m:
1109 case X86Local::MRM2m:
1110 case X86Local::MRM3m:
1111 case X86Local::MRM4m:
1112 case X86Local::MRM5m:
1113 case X86Local::MRM6m:
1114 case X86Local::MRM7m:
1115 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1120 if (needsModRMForDecode(Form))
1121 filter = new ModFilter(isRegFormat(Form));
1123 filter = new DumbFilter();
1125 } // switch (Opcode)
1126 opcodeToSet = Opcode;
1127 } // switch (Prefix)
1129 assert(opcodeType != (OpcodeType)-1 &&
1130 "Opcode type not set");
1131 assert(filter && "Filter not set");
1133 if (Form == X86Local::AddRegFrm) {
1134 assert(((opcodeToSet & 7) == 0) &&
1135 "ADDREG_FRM opcode not aligned");
1137 uint8_t currentOpcode;
1139 for (currentOpcode = opcodeToSet;
1140 currentOpcode < opcodeToSet + 8;
1142 tables.setTableFields(opcodeType,
1146 UID, Is32Bit, IgnoresVEX_L);
1148 tables.setTableFields(opcodeType,
1152 UID, Is32Bit, IgnoresVEX_L);
1160 #define TYPE(str, type) if (s == str) return type;
1161 OperandType RecognizableInstr::typeFromString(const std::string &s,
1163 bool hasREX_WPrefix,
1164 bool hasOpSizePrefix) {
1166 // For SSE instructions, we ignore the OpSize prefix and force operand
1168 TYPE("GR16", TYPE_R16)
1169 TYPE("GR32", TYPE_R32)
1170 TYPE("GR64", TYPE_R64)
1172 if(hasREX_WPrefix) {
1173 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1175 TYPE("GR32", TYPE_R32)
1177 if(!hasOpSizePrefix) {
1178 // For instructions without an OpSize prefix, a declared 16-bit register or
1179 // immediate encoding is special.
1180 TYPE("GR16", TYPE_R16)
1181 TYPE("i16imm", TYPE_IMM16)
1183 TYPE("i16mem", TYPE_Mv)
1184 TYPE("i16imm", TYPE_IMMv)
1185 TYPE("i16i8imm", TYPE_IMMv)
1186 TYPE("GR16", TYPE_Rv)
1187 TYPE("i32mem", TYPE_Mv)
1188 TYPE("i32imm", TYPE_IMMv)
1189 TYPE("i32i8imm", TYPE_IMM32)
1190 TYPE("u32u8imm", TYPE_IMM32)
1191 TYPE("GR32", TYPE_Rv)
1192 TYPE("GR32orGR64", TYPE_R32)
1193 TYPE("i64mem", TYPE_Mv)
1194 TYPE("i64i32imm", TYPE_IMM64)
1195 TYPE("i64i8imm", TYPE_IMM64)
1196 TYPE("GR64", TYPE_R64)
1197 TYPE("i8mem", TYPE_M8)
1198 TYPE("i8imm", TYPE_IMM8)
1199 TYPE("GR8", TYPE_R8)
1200 TYPE("VR128", TYPE_XMM128)
1201 TYPE("VR128X", TYPE_XMM128)
1202 TYPE("f128mem", TYPE_M128)
1203 TYPE("f256mem", TYPE_M256)
1204 TYPE("f512mem", TYPE_M512)
1205 TYPE("FR64", TYPE_XMM64)
1206 TYPE("FR64X", TYPE_XMM64)
1207 TYPE("f64mem", TYPE_M64FP)
1208 TYPE("sdmem", TYPE_M64FP)
1209 TYPE("FR32", TYPE_XMM32)
1210 TYPE("FR32X", TYPE_XMM32)
1211 TYPE("f32mem", TYPE_M32FP)
1212 TYPE("ssmem", TYPE_M32FP)
1213 TYPE("RST", TYPE_ST)
1214 TYPE("i128mem", TYPE_M128)
1215 TYPE("i256mem", TYPE_M256)
1216 TYPE("i512mem", TYPE_M512)
1217 TYPE("i64i32imm_pcrel", TYPE_REL64)
1218 TYPE("i16imm_pcrel", TYPE_REL16)
1219 TYPE("i32imm_pcrel", TYPE_REL32)
1220 TYPE("SSECC", TYPE_IMM3)
1221 TYPE("AVXCC", TYPE_IMM5)
1222 TYPE("AVX512RC", TYPE_IMM32)
1223 TYPE("brtarget", TYPE_RELv)
1224 TYPE("uncondbrtarget", TYPE_RELv)
1225 TYPE("brtarget8", TYPE_REL8)
1226 TYPE("f80mem", TYPE_M80FP)
1227 TYPE("lea32mem", TYPE_LEA)
1228 TYPE("lea64_32mem", TYPE_LEA)
1229 TYPE("lea64mem", TYPE_LEA)
1230 TYPE("VR64", TYPE_MM64)
1231 TYPE("i64imm", TYPE_IMMv)
1232 TYPE("opaque32mem", TYPE_M1616)
1233 TYPE("opaque48mem", TYPE_M1632)
1234 TYPE("opaque80mem", TYPE_M1664)
1235 TYPE("opaque512mem", TYPE_M512)
1236 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1237 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1238 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1239 TYPE("offset8", TYPE_MOFFS8)
1240 TYPE("offset16", TYPE_MOFFS16)
1241 TYPE("offset32", TYPE_MOFFS32)
1242 TYPE("offset64", TYPE_MOFFS64)
1243 TYPE("VR256", TYPE_XMM256)
1244 TYPE("VR256X", TYPE_XMM256)
1245 TYPE("VR512", TYPE_XMM512)
1246 TYPE("VK1", TYPE_VK1)
1247 TYPE("VK1WM", TYPE_VK1)
1248 TYPE("VK8", TYPE_VK8)
1249 TYPE("VK8WM", TYPE_VK8)
1250 TYPE("VK16", TYPE_VK16)
1251 TYPE("VK16WM", TYPE_VK16)
1252 TYPE("GR16_NOAX", TYPE_Rv)
1253 TYPE("GR32_NOAX", TYPE_Rv)
1254 TYPE("GR64_NOAX", TYPE_R64)
1255 TYPE("vx32mem", TYPE_M32)
1256 TYPE("vy32mem", TYPE_M32)
1257 TYPE("vz32mem", TYPE_M32)
1258 TYPE("vx64mem", TYPE_M64)
1259 TYPE("vy64mem", TYPE_M64)
1260 TYPE("vy64xmem", TYPE_M64)
1261 TYPE("vz64mem", TYPE_M64)
1262 errs() << "Unhandled type string " << s << "\n";
1263 llvm_unreachable("Unhandled type string");
1267 #define ENCODING(str, encoding) if (s == str) return encoding;
1268 OperandEncoding RecognizableInstr::immediateEncodingFromString
1269 (const std::string &s,
1270 bool hasOpSizePrefix) {
1271 if(!hasOpSizePrefix) {
1272 // For instructions without an OpSize prefix, a declared 16-bit register or
1273 // immediate encoding is special.
1274 ENCODING("i16imm", ENCODING_IW)
1276 ENCODING("i32i8imm", ENCODING_IB)
1277 ENCODING("u32u8imm", ENCODING_IB)
1278 ENCODING("SSECC", ENCODING_IB)
1279 ENCODING("AVXCC", ENCODING_IB)
1280 ENCODING("AVX512RC", ENCODING_IB)
1281 ENCODING("i16imm", ENCODING_Iv)
1282 ENCODING("i16i8imm", ENCODING_IB)
1283 ENCODING("i32imm", ENCODING_Iv)
1284 ENCODING("i64i32imm", ENCODING_ID)
1285 ENCODING("i64i8imm", ENCODING_IB)
1286 ENCODING("i8imm", ENCODING_IB)
1287 // This is not a typo. Instructions like BLENDVPD put
1288 // register IDs in 8-bit immediates nowadays.
1289 ENCODING("FR32", ENCODING_IB)
1290 ENCODING("FR64", ENCODING_IB)
1291 ENCODING("VR128", ENCODING_IB)
1292 ENCODING("VR256", ENCODING_IB)
1293 ENCODING("FR32X", ENCODING_IB)
1294 ENCODING("FR64X", ENCODING_IB)
1295 ENCODING("VR128X", ENCODING_IB)
1296 ENCODING("VR256X", ENCODING_IB)
1297 ENCODING("VR512", ENCODING_IB)
1298 errs() << "Unhandled immediate encoding " << s << "\n";
1299 llvm_unreachable("Unhandled immediate encoding");
1302 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1303 (const std::string &s,
1304 bool hasOpSizePrefix) {
1305 ENCODING("RST", ENCODING_FP)
1306 ENCODING("GR16", ENCODING_RM)
1307 ENCODING("GR32", ENCODING_RM)
1308 ENCODING("GR32orGR64", ENCODING_RM)
1309 ENCODING("GR64", ENCODING_RM)
1310 ENCODING("GR8", ENCODING_RM)
1311 ENCODING("VR128", ENCODING_RM)
1312 ENCODING("VR128X", ENCODING_RM)
1313 ENCODING("FR64", ENCODING_RM)
1314 ENCODING("FR32", ENCODING_RM)
1315 ENCODING("FR64X", ENCODING_RM)
1316 ENCODING("FR32X", ENCODING_RM)
1317 ENCODING("VR64", ENCODING_RM)
1318 ENCODING("VR256", ENCODING_RM)
1319 ENCODING("VR256X", ENCODING_RM)
1320 ENCODING("VR512", ENCODING_RM)
1321 ENCODING("VK1", ENCODING_RM)
1322 ENCODING("VK8", ENCODING_RM)
1323 ENCODING("VK16", ENCODING_RM)
1324 errs() << "Unhandled R/M register encoding " << s << "\n";
1325 llvm_unreachable("Unhandled R/M register encoding");
1328 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1329 (const std::string &s,
1330 bool hasOpSizePrefix) {
1331 ENCODING("GR16", ENCODING_REG)
1332 ENCODING("GR32", ENCODING_REG)
1333 ENCODING("GR32orGR64", ENCODING_REG)
1334 ENCODING("GR64", ENCODING_REG)
1335 ENCODING("GR8", ENCODING_REG)
1336 ENCODING("VR128", ENCODING_REG)
1337 ENCODING("FR64", ENCODING_REG)
1338 ENCODING("FR32", ENCODING_REG)
1339 ENCODING("VR64", ENCODING_REG)
1340 ENCODING("SEGMENT_REG", ENCODING_REG)
1341 ENCODING("DEBUG_REG", ENCODING_REG)
1342 ENCODING("CONTROL_REG", ENCODING_REG)
1343 ENCODING("VR256", ENCODING_REG)
1344 ENCODING("VR256X", ENCODING_REG)
1345 ENCODING("VR128X", ENCODING_REG)
1346 ENCODING("FR64X", ENCODING_REG)
1347 ENCODING("FR32X", ENCODING_REG)
1348 ENCODING("VR512", ENCODING_REG)
1349 ENCODING("VK1", ENCODING_REG)
1350 ENCODING("VK8", ENCODING_REG)
1351 ENCODING("VK16", ENCODING_REG)
1352 ENCODING("VK1WM", ENCODING_REG)
1353 ENCODING("VK8WM", ENCODING_REG)
1354 ENCODING("VK16WM", ENCODING_REG)
1355 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1356 llvm_unreachable("Unhandled reg/opcode register encoding");
1359 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1360 (const std::string &s,
1361 bool hasOpSizePrefix) {
1362 ENCODING("GR32", ENCODING_VVVV)
1363 ENCODING("GR64", ENCODING_VVVV)
1364 ENCODING("FR32", ENCODING_VVVV)
1365 ENCODING("FR64", ENCODING_VVVV)
1366 ENCODING("VR128", ENCODING_VVVV)
1367 ENCODING("VR256", ENCODING_VVVV)
1368 ENCODING("FR32X", ENCODING_VVVV)
1369 ENCODING("FR64X", ENCODING_VVVV)
1370 ENCODING("VR128X", ENCODING_VVVV)
1371 ENCODING("VR256X", ENCODING_VVVV)
1372 ENCODING("VR512", ENCODING_VVVV)
1373 ENCODING("VK1", ENCODING_VVVV)
1374 ENCODING("VK8", ENCODING_VVVV)
1375 ENCODING("VK16", ENCODING_VVVV)
1376 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1377 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1380 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1381 (const std::string &s,
1382 bool hasOpSizePrefix) {
1383 ENCODING("VK1WM", ENCODING_WRITEMASK)
1384 ENCODING("VK8WM", ENCODING_WRITEMASK)
1385 ENCODING("VK16WM", ENCODING_WRITEMASK)
1386 errs() << "Unhandled mask register encoding " << s << "\n";
1387 llvm_unreachable("Unhandled mask register encoding");
1390 OperandEncoding RecognizableInstr::memoryEncodingFromString
1391 (const std::string &s,
1392 bool hasOpSizePrefix) {
1393 ENCODING("i16mem", ENCODING_RM)
1394 ENCODING("i32mem", ENCODING_RM)
1395 ENCODING("i64mem", ENCODING_RM)
1396 ENCODING("i8mem", ENCODING_RM)
1397 ENCODING("ssmem", ENCODING_RM)
1398 ENCODING("sdmem", ENCODING_RM)
1399 ENCODING("f128mem", ENCODING_RM)
1400 ENCODING("f256mem", ENCODING_RM)
1401 ENCODING("f512mem", ENCODING_RM)
1402 ENCODING("f64mem", ENCODING_RM)
1403 ENCODING("f32mem", ENCODING_RM)
1404 ENCODING("i128mem", ENCODING_RM)
1405 ENCODING("i256mem", ENCODING_RM)
1406 ENCODING("i512mem", ENCODING_RM)
1407 ENCODING("f80mem", ENCODING_RM)
1408 ENCODING("lea32mem", ENCODING_RM)
1409 ENCODING("lea64_32mem", ENCODING_RM)
1410 ENCODING("lea64mem", ENCODING_RM)
1411 ENCODING("opaque32mem", ENCODING_RM)
1412 ENCODING("opaque48mem", ENCODING_RM)
1413 ENCODING("opaque80mem", ENCODING_RM)
1414 ENCODING("opaque512mem", ENCODING_RM)
1415 ENCODING("vx32mem", ENCODING_RM)
1416 ENCODING("vy32mem", ENCODING_RM)
1417 ENCODING("vz32mem", ENCODING_RM)
1418 ENCODING("vx64mem", ENCODING_RM)
1419 ENCODING("vy64mem", ENCODING_RM)
1420 ENCODING("vy64xmem", ENCODING_RM)
1421 ENCODING("vz64mem", ENCODING_RM)
1422 errs() << "Unhandled memory encoding " << s << "\n";
1423 llvm_unreachable("Unhandled memory encoding");
1426 OperandEncoding RecognizableInstr::relocationEncodingFromString
1427 (const std::string &s,
1428 bool hasOpSizePrefix) {
1429 if(!hasOpSizePrefix) {
1430 // For instructions without an OpSize prefix, a declared 16-bit register or
1431 // immediate encoding is special.
1432 ENCODING("i16imm", ENCODING_IW)
1434 ENCODING("i16imm", ENCODING_Iv)
1435 ENCODING("i16i8imm", ENCODING_IB)
1436 ENCODING("i32imm", ENCODING_Iv)
1437 ENCODING("i32i8imm", ENCODING_IB)
1438 ENCODING("i64i32imm", ENCODING_ID)
1439 ENCODING("i64i8imm", ENCODING_IB)
1440 ENCODING("i8imm", ENCODING_IB)
1441 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1442 ENCODING("i16imm_pcrel", ENCODING_IW)
1443 ENCODING("i32imm_pcrel", ENCODING_ID)
1444 ENCODING("brtarget", ENCODING_Iv)
1445 ENCODING("brtarget8", ENCODING_IB)
1446 ENCODING("i64imm", ENCODING_IO)
1447 ENCODING("offset8", ENCODING_Ia)
1448 ENCODING("offset16", ENCODING_Ia)
1449 ENCODING("offset32", ENCODING_Ia)
1450 ENCODING("offset64", ENCODING_Ia)
1451 errs() << "Unhandled relocation encoding " << s << "\n";
1452 llvm_unreachable("Unhandled relocation encoding");
1455 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1456 (const std::string &s,
1457 bool hasOpSizePrefix) {
1458 ENCODING("GR32", ENCODING_Rv)
1459 ENCODING("GR64", ENCODING_RO)
1460 ENCODING("GR16", ENCODING_Rv)
1461 ENCODING("GR8", ENCODING_RB)
1462 ENCODING("GR16_NOAX", ENCODING_Rv)
1463 ENCODING("GR32_NOAX", ENCODING_Rv)
1464 ENCODING("GR64_NOAX", ENCODING_RO)
1465 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1466 llvm_unreachable("Unhandled opcode modifier encoding");