1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
20 #include "llvm/TableGen/TableGenBackend.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/Format.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_XD) ||
45 inheritsFrom(child, IC_XS));
47 return(inheritsFrom(child, IC_64BIT_REXW) ||
48 inheritsFrom(child, IC_64BIT_OPSIZE) ||
49 inheritsFrom(child, IC_64BIT_XD) ||
50 inheritsFrom(child, IC_64BIT_XS));
52 return inheritsFrom(child, IC_64BIT_OPSIZE);
54 return inheritsFrom(child, IC_64BIT_XD);
56 return inheritsFrom(child, IC_64BIT_XS);
58 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
60 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
62 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
63 inheritsFrom(child, IC_64BIT_REXW_XD) ||
64 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
66 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
68 return(inheritsFrom(child, IC_64BIT_REXW_XD));
70 return(inheritsFrom(child, IC_64BIT_REXW_XS));
71 case IC_64BIT_XD_OPSIZE:
72 case IC_64BIT_XS_OPSIZE:
74 case IC_64BIT_REXW_XD:
75 case IC_64BIT_REXW_XS:
76 case IC_64BIT_REXW_OPSIZE:
79 return inheritsFrom(child, IC_VEX_W) ||
80 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
82 return inheritsFrom(child, IC_VEX_W_XS) ||
83 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
85 return inheritsFrom(child, IC_VEX_W_XD) ||
86 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
88 return inheritsFrom(child, IC_VEX_W_OPSIZE) ||
89 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
100 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
101 case IC_VEX_L_W_OPSIZE:
104 llvm_unreachable("Unknown instruction class");
108 /// outranks - Indicates whether, if an instruction has two different applicable
109 /// classes, which class should be preferred when performing decode. This
110 /// imposes a total ordering (ties are resolved toward "lower")
112 /// @param upper - The class that may be preferable
113 /// @param lower - The class that may be less preferable
114 /// @return - True if upper is to be preferred, false otherwise.
115 static inline bool outranks(InstructionContext upper,
116 InstructionContext lower) {
117 assert(upper < IC_max);
118 assert(lower < IC_max);
120 #define ENUM_ENTRY(n, r, d) r,
121 static int ranks[IC_max] = {
126 return (ranks[upper] > ranks[lower]);
129 /// stringForContext - Returns a string containing the name of a particular
130 /// InstructionContext, usually for diagnostic purposes.
132 /// @param insnContext - The instruction class to transform to a string.
133 /// @return - A statically-allocated string constant that contains the
134 /// name of the instruction class.
135 static inline const char* stringForContext(InstructionContext insnContext) {
136 switch (insnContext) {
138 llvm_unreachable("Unhandled instruction class");
139 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
147 /// stringForOperandType - Like stringForContext, but for OperandTypes.
148 static inline const char* stringForOperandType(OperandType type) {
151 llvm_unreachable("Unhandled type");
152 #define ENUM_ENTRY(i, d) case i: return #i;
158 /// stringForOperandEncoding - like stringForContext, but for
159 /// OperandEncodings.
160 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
163 llvm_unreachable("Unhandled encoding");
164 #define ENUM_ENTRY(i, d) case i: return #i;
170 void DisassemblerTables::emitOneID(raw_ostream &o,
173 bool addComma) const {
175 o.indent(i * 2) << format("0x%hx", id);
177 o.indent(i * 2) << 0;
185 o << InstructionSpecifiers[id].name;
191 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
192 /// all ModR/M decisions for instructions that are invalid for all possible
193 /// ModR/M byte values.
195 /// @param o - The output stream on which to emit the table.
196 /// @param i - The indentation level for that output stream.
197 static void emitEmptyTable(raw_ostream &o, uint32_t &i)
199 o.indent(i * 2) << "0x0, /* EmptyTable */\n";
202 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
203 /// be compacted by eliminating redundant information.
205 /// @param decision - The decision to be compacted.
206 /// @return - The compactest available representation for the decision.
207 static ModRMDecisionType getDecisionType(ModRMDecision &decision)
209 bool satisfiesOneEntry = true;
210 bool satisfiesSplitRM = true;
211 bool satisfiesSplitReg = true;
215 for (index = 0; index < 256; ++index) {
216 if (decision.instructionIDs[index] != decision.instructionIDs[0])
217 satisfiesOneEntry = false;
219 if (((index & 0xc0) == 0xc0) &&
220 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
221 satisfiesSplitRM = false;
223 if (((index & 0xc0) != 0xc0) &&
224 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
225 satisfiesSplitRM = false;
227 if (((index & 0xc0) == 0xc0) &&
228 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
229 satisfiesSplitReg = false;
231 if (((index & 0xc0) != 0xc0) &&
232 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
233 satisfiesSplitReg = false;
236 if (satisfiesOneEntry)
237 return MODRM_ONEENTRY;
239 if (satisfiesSplitRM)
240 return MODRM_SPLITRM;
242 if (satisfiesSplitReg)
243 return MODRM_SPLITREG;
248 /// stringForDecisionType - Returns a statically-allocated string corresponding
249 /// to a particular decision type.
251 /// @param dt - The decision type.
252 /// @return - A pointer to the statically-allocated string (e.g.,
253 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
254 static const char* stringForDecisionType(ModRMDecisionType dt)
256 #define ENUM_ENTRY(n) case n: return #n;
259 llvm_unreachable("Unknown decision type");
265 /// stringForModifierType - Returns a statically-allocated string corresponding
266 /// to an opcode modifier type.
268 /// @param mt - The modifier type.
269 /// @return - A pointer to the statically-allocated string (e.g.,
270 /// "MODIFIER_NONE" for MODIFIER_NONE).
271 static const char* stringForModifierType(ModifierType mt)
273 #define ENUM_ENTRY(n) case n: return #n;
276 llvm_unreachable("Unknown modifier type");
282 DisassemblerTables::DisassemblerTables() {
285 for (i = 0; i < array_lengthof(Tables); i++) {
286 Tables[i] = new ContextDecision;
287 memset(Tables[i], 0, sizeof(ContextDecision));
290 HasConflicts = false;
293 DisassemblerTables::~DisassemblerTables() {
296 for (i = 0; i < array_lengthof(Tables); i++)
300 void DisassemblerTables::emitModRMDecision(raw_ostream &o1,
304 ModRMDecision &decision)
306 static uint64_t sTableNumber = 0;
307 static uint64_t sEntryNumber = 1;
308 ModRMDecisionType dt = getDecisionType(decision);
311 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
313 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
316 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
317 o2.indent(i2) << 0 << " /* EmptyTable */\n";
320 o2.indent(i2) << "}";
324 o1 << "/* Table" << sTableNumber << " */\n";
329 llvm_unreachable("Unknown decision type");
331 emitOneID(o1, i1, decision.instructionIDs[0], true);
334 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
335 emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11
338 for (index = 0; index < 64; index += 8)
339 emitOneID(o1, i1, decision.instructionIDs[index], true);
340 for (index = 0xc0; index < 256; index += 8)
341 emitOneID(o1, i1, decision.instructionIDs[index], true);
344 for (index = 0; index < 256; ++index)
345 emitOneID(o1, i1, decision.instructionIDs[index], true);
351 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
354 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
355 o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n";
358 o2.indent(i2) << "}";
362 llvm_unreachable("Unknown decision type");
380 void DisassemblerTables::emitOpcodeDecision(
385 OpcodeDecision &decision) const {
388 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
390 o2.indent(i2) << "{" << "\n";
393 for (index = 0; index < 256; ++index) {
396 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
398 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
407 o2.indent(i2) << "}" << "\n";
409 o2.indent(i2) << "}" << "\n";
412 void DisassemblerTables::emitContextDecision(
417 ContextDecision &decision,
418 const char* name) const {
419 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
421 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
426 for (index = 0; index < IC_max; ++index) {
427 o2.indent(i2) << "/* ";
428 o2 << stringForContext((InstructionContext)index);
432 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
434 if (index + 1 < IC_max)
439 o2.indent(i2) << "}" << "\n";
441 o2.indent(i2) << "};" << "\n";
444 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, uint32_t &i)
446 o.indent(i * 2) << "static const struct InstructionSpecifier ";
447 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
451 uint16_t numInstructions = InstructionSpecifiers.size();
452 uint16_t index, operandIndex;
454 for (index = 0; index < numInstructions; ++index) {
455 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
459 stringForModifierType(InstructionSpecifiers[index].modifierType);
462 o.indent(i * 2) << "0x";
463 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
466 o.indent(i * 2) << "{" << "\n";
469 for (operandIndex = 0; operandIndex < X86_MAX_OPERANDS; ++operandIndex) {
470 o.indent(i * 2) << "{ ";
471 o << stringForOperandEncoding(InstructionSpecifiers[index]
472 .operands[operandIndex]
475 o << stringForOperandType(InstructionSpecifiers[index]
476 .operands[operandIndex]
480 if (operandIndex < X86_MAX_OPERANDS - 1)
487 o.indent(i * 2) << "}," << "\n";
489 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
493 o.indent(i * 2) << "}";
495 if (index + 1 < numInstructions)
502 o.indent(i * 2) << "};" << "\n";
505 void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
508 o.indent(i * 2) << "static const InstructionContext " CONTEXTS_STR
512 for (index = 0; index < 256; ++index) {
515 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
516 o << "IC_VEX_L_W_OPSIZE";
517 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
518 o << "IC_VEX_L_OPSIZE";
519 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
521 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
523 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
524 o << "IC_VEX_W_OPSIZE";
525 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
527 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
529 else if (index & ATTR_VEXL)
531 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
533 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
534 o << "IC_VEX_OPSIZE";
535 else if ((index & ATTR_VEX) && (index & ATTR_XD))
537 else if ((index & ATTR_VEX) && (index & ATTR_XS))
539 else if (index & ATTR_VEX)
541 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
542 o << "IC_64BIT_REXW_XS";
543 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
544 o << "IC_64BIT_REXW_XD";
545 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
546 (index & ATTR_OPSIZE))
547 o << "IC_64BIT_REXW_OPSIZE";
548 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
549 o << "IC_64BIT_XD_OPSIZE";
550 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
551 o << "IC_64BIT_XS_OPSIZE";
552 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
554 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
556 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
557 o << "IC_64BIT_OPSIZE";
558 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
559 o << "IC_64BIT_REXW";
560 else if ((index & ATTR_64BIT))
562 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
564 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
566 else if (index & ATTR_XS)
568 else if (index & ATTR_XD)
570 else if (index & ATTR_OPSIZE)
580 o << " /* " << index << " */";
586 o.indent(i * 2) << "};" << "\n";
589 void DisassemblerTables::emitContextDecisions(raw_ostream &o1,
594 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
595 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
596 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
597 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
598 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
599 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
602 void DisassemblerTables::emit(raw_ostream &o) const {
609 raw_string_ostream o1(s1);
610 raw_string_ostream o2(s2);
612 emitInstructionInfo(o, i2);
615 emitContextTable(o, i2);
618 o << "static const InstrUID modRMTable[] = {\n";
620 emitEmptyTable(o1, i1);
622 emitContextDecisions(o1, o2, i1, i2);
633 void DisassemblerTables::setTableFields(ModRMDecision &decision,
634 const ModRMFilter &filter,
639 for (index = 0; index < 256; ++index) {
640 if (filter.accepts(index)) {
641 if (decision.instructionIDs[index] == uid)
644 if (decision.instructionIDs[index] != 0) {
645 InstructionSpecifier &newInfo =
646 InstructionSpecifiers[uid];
647 InstructionSpecifier &previousInfo =
648 InstructionSpecifiers[decision.instructionIDs[index]];
651 continue; // filtered instructions get lowest priority
653 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
654 newInfo.name == "XCHG32ar" ||
655 newInfo.name == "XCHG32ar64" ||
656 newInfo.name == "XCHG64ar"))
657 continue; // special case for XCHG*ar and NOOP
659 if (outranks(previousInfo.insnContext, newInfo.insnContext))
662 if (previousInfo.insnContext == newInfo.insnContext &&
663 !previousInfo.filtered) {
664 errs() << "Error: Primary decode conflict: ";
665 errs() << newInfo.name << " would overwrite " << previousInfo.name;
667 errs() << "ModRM " << index << "\n";
668 errs() << "Opcode " << (uint16_t)opcode << "\n";
669 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
674 decision.instructionIDs[index] = uid;
679 void DisassemblerTables::setTableFields(OpcodeType type,
680 InstructionContext insnContext,
682 const ModRMFilter &filter,
688 ContextDecision &decision = *Tables[type];
690 for (index = 0; index < IC_max; ++index) {
691 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
694 if (inheritsFrom((InstructionContext)index,
695 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
696 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],