test/MC/ARM/thumb2-narrow-dp.ll

   1 // RUN: llvm-mc -triple thumbv7 -show-encoding < %s | FileCheck %s
   2
   3 // Test each of the Thumb1 data-processing instructions
   4 // The assembly syntax for these instructions allows an optional Rd register
   5 //   OP{S}{<c>}{<q>}  {<Rd>,} <Rn>, <Rm>
   6 // Assemblers should chose the narrow thumb encoding when possible, i.e.
   7 //   - Rd == Rn
   8 //   - Rd, Rn and Rm are < r8
   9 // In addition, some operations are commutative, allowing the transformation
  10 // when:
  11 //   - Rd == Rn || Rd == Rm
  12 //   - Rd, Rn and Rm are < r8
  13
  14 // ADD immediate (not SP) A8.8.4
  15     ADDS     r0, r0, #5          // T1
  16 // CHECK: adds  r0, r0, #5          @ encoding: [0x40,0x1d]
  17     ADDS     r1, r1, #8          // T2
  18 // CHECK: adds  r1, #8              @ encoding: [0x08,0x31]
  19     ADDS.W   r1, r1, #8          // .w => T3
  20 // CHECK: adds.w r1, r1, #8         @ encoding: [0x11,0xf1,0x08,0x01]
  21     ADDS     r8, r8, #8          // T3
  22 // CHECK: adds.w r8, r8, #8         @ encoding: [0x18,0xf1,0x08,0x08]
  23
  24     IT EQ
  25 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  26     ADDEQ    r0, r0, #5          // T1
  27 // CHECK: addeq r0, r0, #5          @ encoding: [0x40,0x1d]
  28     IT EQ
  29 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  30     ADDEQ    r1, r1, #8          // T2
  31 // CHECK: addeq r1, #8              @ encoding: [0x08,0x31]
  32
  33     IT EQ
  34 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  35     ADDSEQ   r0, r0, #5          // T3
  36 // CHECK: addseq.w r0, r0, #5       @ encoding: [0x10,0xf1,0x05,0x00]
  37     IT EQ
  38 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  39     ADDSEQ   r1, r1, #8          // T3
  40 // CHECK: addseq.w r1, r1, #8       @ encoding: [0x11,0xf1,0x08,0x01]
  41
  42 // ADD register (not SP) A8.8.6 (commutative)
  43     ADDS     r0, r2, r1          // ADDS has T1 narrow 3 operand
  44 // CHECK: adds  r0, r2, r1          @ encoding: [0x50,0x18]
  45     ADDS     r2, r2, r1          // ADDS has T1 narrow 3 operand
  46 // CHECK: adds  r2, r2, r1          @ encoding: [0x52,0x18]
  47
  48     IT EQ
  49 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  50     ADDEQ    r0, r2, r1          // (In IT) ADD has T1 narrow 3 operand
  51 // CHECK: addeq r0, r2, r1          @ encoding: [0x50,0x18]
  52     IT EQ
  53 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  54     ADDEQ    r2, r2, r1          // (In IT) ADD has T1 narrow 3 operand
  55 // CHECK: addeq r2, r2, r1          @ encoding: [0x52,0x18]
  56
  57     IT EQ
  58 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  59     ADDSEQ   r0, r2, r1          // T3
  60 // CHECK: addseq.w r0, r2, r1       @ encoding: [0x12,0xeb,0x01,0x00]
  61     IT EQ
  62 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  63     ADDSEQ   r2, r2, r1          // T3
  64 // CHECK: addseq.w r2, r2, r1       @ encoding: [0x12,0xeb,0x01,0x02]
  65
  66     ADD      r3, r3, r1          // T2
  67 // CHECK: add  r3, r1               @ encoding: [0x0b,0x44]
  68     ADD      r4, r4, pc          // T2
  69 // CHECK: add  r4, pc               @ encoding: [0x7c,0x44]
  70     ADD      r4, pc, r4          // T2
  71 // CHECK: add  r4, pc               @ encoding: [0x7c,0x44]
  72     ADD      pc, pc, r2          // T2
  73 // CHECK: add  pc, r2               @ encoding: [0x97,0x44]
  74     ADD      pc, r2, pc          // T2
  75 // CHECK: add  pc, r2               @ encoding: [0x97,0x44]
  76     ADD      pc, pc, sp          // T2
  77 // CHECK: add   pc, sp              @ encoding: [0xef,0x44]
  78     ADD      pc, sp, pc          // T2
  79 // CHECK: add   pc, sp, pc          @ encoding: [0xef,0x44]
  80
  81 // ADD (SP plus immediate) A8.8.9
  82     ADD      sp, sp, #20         // T2
  83 // FIXME: ARMARM says 'add   sp, sp, #20'
  84 // CHECK: add   sp, #20             @ encoding: [0x05,0xb0]
  85     ADD      sp, sp, #508        // T2
  86 // CHECK: add   sp, #508            @ encoding: [0x7f,0xb0]
  87     ADD      sp, sp, #512        // T3
  88 // CHECK: add.w sp, sp, #512        @ encoding: [0x0d,0xf5,0x00,0x7d]
  89
  90 // ADD (SP plus register) A8.8.10 (commutative)
  91     ADD      r9, sp, r9          // T1
  92 // CHECK: add   r9, sp, r9          @ encoding: [0xe9,0x44]
  93     ADD      r9, r9, sp          // T1
  94 // FIXME: ARMARM says 'add   r9, sp, r9'
  95 // CHECK: add   r9, sp              @ encoding: [0xe9,0x44]
  96     ADD      sp, sp, r10         // T2
  97 // CHECK: add   sp, r10             @ encoding: [0xd5,0x44]
  98     ADD      sp, r10, sp         // T2
  99 // CHECK: add   sp, r10             @ encoding: [0xd5,0x44]
 100     ADD      sp, sp, pc          // T2
 101 // CHECK: add   sp, pc              @ encoding: [0xfd,0x44]
 102
 103 // AND (commutative)
 104     ANDS     r0, r2, r1          // Must be wide - 3 distinct registers
 105     ANDS     r2, r2, r1          // Should choose narrow
 106     ANDS     r2, r1, r2          // Should choose narrow - commutative
 107     ANDS.W   r0, r0, r1          // Explicitly wide
 108     ANDS.W   r3, r1, r3
 109     AND      r0, r1, r0          // Must use wide encoding as not flag-setting
 110     ANDS     r7, r7, r1          // Should use narrow
 111     ANDS     r7, r1, r7          // Commutative
 112     ANDS     r8, r1, r8          // high registers so must use wide encoding
 113     ANDS     r8, r8, r1
 114     ANDS     r0, r8, r0
 115     ANDS     r1, r1, r8
 116     ANDS     r2, r2, r1, lsl #1  // Must use wide - shifted register
 117     ANDS     r0, r1, r0, lsr #1
 118 // CHECK: ands.w  r0, r2, r1              @ encoding: [0x12,0xea,0x01,0x00]
 119 // CHECK: ands    r2, r1                  @ encoding: [0x0a,0x40]
 120 // CHECK: ands    r2, r1                  @ encoding: [0x0a,0x40]
 121 // CHECK: ands.w  r0, r0, r1              @ encoding: [0x10,0xea,0x01,0x00]
 122 // CHECK: ands.w  r3, r1, r3              @ encoding: [0x11,0xea,0x03,0x03]
 123 // CHECK: and.w   r0, r1, r0              @ encoding: [0x01,0xea,0x00,0x00]
 124 // CHECK: ands    r7, r1                  @ encoding: [0x0f,0x40]
 125 // CHECK: ands    r7, r1                  @ encoding: [0x0f,0x40]
 126 // CHECK: ands.w  r8, r1, r8              @ encoding: [0x11,0xea,0x08,0x08]
 127 // CHECK: ands.w  r8, r8, r1              @ encoding: [0x18,0xea,0x01,0x08]
 128 // CHECK: ands.w  r0, r8, r0              @ encoding: [0x18,0xea,0x00,0x00]
 129 // CHECK: ands.w  r1, r1, r8              @ encoding: [0x11,0xea,0x08,0x01]
 130 // CHECK: ands.w  r2, r2, r1, lsl #1      @ encoding: [0x12,0xea,0x41,0x02]
 131 // CHECK: ands.w  r0, r1, r0, lsr #1      @ encoding: [0x11,0xea,0x50,0x00]
 132
 133     IT EQ
 134     ANDEQ    r0, r2, r1          // Must be wide - 3 distinct registers
 135     IT EQ
 136     ANDEQ    r3, r3, r1          // Should choose narrow
 137     IT EQ
 138     ANDEQ    r3, r1, r3          // Should choose narrow - commutative
 139     IT EQ
 140     ANDEQ.W  r0, r0, r1          // Explicitly wide
 141     IT EQ
 142     ANDEQ.W  r2, r1, r2
 143     IT EQ
 144     ANDSEQ   r0, r1, r0          // Must use wide encoding as flag-setting
 145     IT EQ
 146     ANDEQ    r7, r7, r1          // Should use narrow
 147     IT EQ
 148     ANDEQ    r7, r1, r7          // Commutative
 149     IT EQ
 150     ANDEQ    r8, r1, r8          // high registers so must use wide encoding
 151     IT EQ
 152     ANDEQ    r8, r8, r1
 153     IT EQ
 154     ANDEQ    r4, r8, r4
 155     IT EQ
 156     ANDEQ    r4, r4, r8
 157     IT EQ
 158     ANDEQ    r0, r0, r1, lsl #1  // Must use wide - shifted register
 159     IT EQ
 160     ANDEQ    r5, r1, r5, lsr #1
 161 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 162 // CHECK: andeq.w  r0, r2, r1             @ encoding: [0x02,0xea,0x01,0x00]
 163 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 164 // CHECK: andeq    r3, r1                 @ encoding: [0x0b,0x40]
 165 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 166 // CHECK: andeq    r3, r1                 @ encoding: [0x0b,0x40]
 167 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 168 // CHECK: andeq.w  r0, r0, r1             @ encoding: [0x00,0xea,0x01,0x00]
 169 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 170 // CHECK: andeq.w  r2, r1, r2             @ encoding: [0x01,0xea,0x02,0x02]
 171 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 172 // CHECK: andseq.w r0, r1, r0             @ encoding: [0x11,0xea,0x00,0x00]
 173 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 174 // CHECK: andeq    r7, r1                 @ encoding: [0x0f,0x40]
 175 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 176 // CHECK: andeq    r7, r1                 @ encoding: [0x0f,0x40]
 177 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 178 // CHECK: andeq.w  r8, r1, r8             @ encoding: [0x01,0xea,0x08,0x08]
 179 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 180 // CHECK: andeq.w  r8, r8, r1             @ encoding: [0x08,0xea,0x01,0x08]
 181 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 182 // CHECK: andeq.w  r4, r8, r4             @ encoding: [0x08,0xea,0x04,0x04]
 183 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 184 // CHECK: andeq.w  r4, r4, r8             @ encoding: [0x04,0xea,0x08,0x04]
 185 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 186 // CHECK: andeq.w  r0, r0, r1, lsl #1     @ encoding: [0x00,0xea,0x41,0x00]
 187 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 188 // CHECK: andeq.w  r5, r1, r5, lsr #1     @ encoding: [0x01,0xea,0x55,0x05]
 189
 190 // EOR (commutative)
 191     EORS     r0, r2, r1          // Must be wide - 3 distinct registers
 192     EORS     r5, r5, r1          // Should choose narrow
 193     EORS     r5, r1, r5          // Should choose narrow - commutative
 194     EORS.W   r0, r0, r1          // Explicitly wide
 195     EORS.W   r2, r1, r2
 196     EOR      r1, r1, r1          // Must use wide encoding as not flag-setting
 197     EORS     r7, r7, r1          // Should use narrow
 198     EORS     r7, r1, r7          // Commutative
 199     EORS     r8, r1, r8          // high registers so must use wide encoding
 200     EORS     r8, r8, r1
 201     EORS     r6, r8, r6
 202     EORS     r0, r0, r8
 203     EORS     r2, r2, r1, lsl #1  // Must use wide - shifted register
 204     EORS     r0, r1, r0, lsr #1
 205 // CHECK: eors.w  r0, r2, r1              @ encoding: [0x92,0xea,0x01,0x00]
 206 // CHECK: eors    r5, r1                  @ encoding: [0x4d,0x40]
 207 // CHECK: eors    r5, r1                  @ encoding: [0x4d,0x40]
 208 // CHECK: eors.w  r0, r0, r1              @ encoding: [0x90,0xea,0x01,0x00]
 209 // CHECK: eors.w  r2, r1, r2              @ encoding: [0x91,0xea,0x02,0x02]
 210 // CHECK: eor.w   r1, r1, r1              @ encoding: [0x81,0xea,0x01,0x01]
 211 // CHECK: eors    r7, r1                  @ encoding: [0x4f,0x40]
 212 // CHECK: eors    r7, r1                  @ encoding: [0x4f,0x40]
 213 // CHECK: eors.w  r8, r1, r8              @ encoding: [0x91,0xea,0x08,0x08]
 214 // CHECK: eors.w  r8, r8, r1              @ encoding: [0x98,0xea,0x01,0x08]
 215 // CHECK: eors.w  r6, r8, r6              @ encoding: [0x98,0xea,0x06,0x06]
 216 // CHECK: eors.w  r0, r0, r8              @ encoding: [0x90,0xea,0x08,0x00]
 217 // CHECK: eors.w  r2, r2, r1, lsl #1      @ encoding: [0x92,0xea,0x41,0x02]
 218 // CHECK: eors.w  r0, r1, r0, lsr #1      @ encoding: [0x91,0xea,0x50,0x00]
 219
 220     IT EQ
 221     EOREQ    r3, r2, r1          // Must be wide - 3 distinct registers
 222     IT EQ
 223     EOREQ    r0, r0, r1          // Should choose narrow
 224     IT EQ
 225     EOREQ    r2, r1, r2          // Should choose narrow - commutative
 226     IT EQ
 227     EOREQ.W  r3, r3, r1          // Explicitly wide
 228     IT EQ
 229     EOREQ.W  r0, r1, r0
 230     IT EQ
 231     EORSEQ   r1, r1, r1          // Must use wide encoding as flag-setting
 232     IT EQ
 233     EOREQ    r7, r7, r1          // Should use narrow
 234     IT EQ
 235     EOREQ    r7, r1, r7          // Commutative
 236     IT EQ
 237     EOREQ    r8, r1, r8          // high registers so must use wide encoding
 238     IT EQ
 239     EOREQ    r8, r8, r1
 240     IT EQ
 241     EOREQ    r0, r8, r0
 242     IT EQ
 243     EOREQ    r3, r3, r8
 244     IT EQ
 245     EOREQ    r4, r4, r1, lsl #1  // Must use wide - shifted register
 246     IT EQ
 247     EOREQ    r0, r1, r0, lsr #1
 248 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 249 // CHECK: eoreq.w  r3, r2, r1             @ encoding: [0x82,0xea,0x01,0x03]
 250 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 251 // CHECK: eoreq    r0, r1                 @ encoding: [0x48,0x40]
 252 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 253 // CHECK: eoreq    r2, r1                 @ encoding: [0x4a,0x40]
 254 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 255 // CHECK: eoreq.w  r3, r3, r1             @ encoding: [0x83,0xea,0x01,0x03]
 256 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 257 // CHECK: eoreq.w  r0, r1, r0             @ encoding: [0x81,0xea,0x00,0x00]
 258 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 259 // CHECK: eorseq.w r1, r1, r1             @ encoding: [0x91,0xea,0x01,0x01]
 260 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 261 // CHECK: eoreq    r7, r1                 @ encoding: [0x4f,0x40]
 262 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 263 // CHECK: eoreq    r7, r1                 @ encoding: [0x4f,0x40]
 264 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 265 // CHECK: eoreq.w  r8, r1, r8             @ encoding: [0x81,0xea,0x08,0x08]
 266 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 267 // CHECK: eoreq.w  r8, r8, r1             @ encoding: [0x88,0xea,0x01,0x08]
 268 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 269 // CHECK: eoreq.w  r0, r8, r0             @ encoding: [0x88,0xea,0x00,0x00]
 270 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 271 // CHECK: eoreq.w  r3, r3, r8             @ encoding: [0x83,0xea,0x08,0x03]
 272 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 273 // CHECK: eoreq.w  r4, r4, r1, lsl #1     @ encoding: [0x84,0xea,0x41,0x04]
 274 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 275 // CHECK: eoreq.w  r0, r1, r0, lsr #1     @ encoding: [0x81,0xea,0x50,0x00]
 276
 277 // LSL
 278     LSLS     r0, r2, r1          // Must be wide - 3 distinct registers
 279     LSLS     r2, r2, r1          // Should choose narrow
 280     LSLS     r2, r1, r2          // Should choose wide - not commutative
 281     LSLS.W   r0, r0, r1          // Explicitly wide
 282     LSLS.W   r4, r1, r4
 283     LSL      r4, r1, r4          // Must use wide encoding as not flag-setting
 284     LSLS     r7, r7, r1          // Should use narrow
 285     LSLS     r8, r1, r8          // high registers so must use wide encoding
 286     LSLS     r8, r8, r1
 287     LSLS     r3, r8, r3
 288     LSLS     r5, r5, r8
 289 // CHECK: lsls.w  r0, r2, r1              @ encoding: [0x12,0xfa,0x01,0xf0]
 290 // CHECK: lsls    r2, r1                  @ encoding: [0x8a,0x40]
 291 // CHECK: lsls.w  r2, r1, r2              @ encoding: [0x11,0xfa,0x02,0xf2]
 292 // CHECK: lsls.w  r0, r0, r1              @ encoding: [0x10,0xfa,0x01,0xf0]
 293 // CHECK: lsls.w  r4, r1, r4              @ encoding: [0x11,0xfa,0x04,0xf4]
 294 // CHECK: lsl.w   r4, r1, r4              @ encoding: [0x01,0xfa,0x04,0xf4]
 295 // CHECK: lsls    r7, r1                  @ encoding: [0x8f,0x40]
 296 // CHECK: lsls.w  r8, r1, r8              @ encoding: [0x11,0xfa,0x08,0xf8]
 297 // CHECK: lsls.w  r8, r8, r1              @ encoding: [0x18,0xfa,0x01,0xf8]
 298 // CHECK: lsls.w  r3, r8, r3              @ encoding: [0x18,0xfa,0x03,0xf3]
 299 // CHECK: lsls.w  r5, r5, r8              @ encoding: [0x15,0xfa,0x08,0xf5]
 300
 301     IT EQ
 302     LSLEQ    r0, r2, r1          // Must be wide - 3 distinct registers
 303     IT EQ
 304     LSLEQ    r2, r2, r1          // Should choose narrow
 305     IT EQ
 306     LSLEQ    r2, r1, r2          // Should choose wide - not commutative
 307     IT EQ
 308     LSLEQ.W  r0, r0, r1          // Explicitly wide
 309     IT EQ
 310     LSLEQ.W  r3, r1, r3
 311     IT EQ
 312     LSLSEQ   r4, r1, r4          // Must use wide encoding as flag-setting
 313     IT EQ
 314     LSLEQ    r7, r7, r1          // Should use narrow
 315     IT EQ
 316     LSLEQ    r8, r1, r8          // high registers so must use wide encoding
 317     IT EQ
 318     LSLEQ    r8, r8, r1
 319     IT EQ
 320     LSLEQ    r0, r8, r0
 321     IT EQ
 322     LSLEQ    r3, r3, r8
 323 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 324 // CHECK: lsleq.w  r0, r2, r1             @ encoding: [0x02,0xfa,0x01,0xf0]
 325 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 326 // CHECK: lsleq    r2, r1                 @ encoding: [0x8a,0x40]
 327 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 328 // CHECK: lsleq.w  r2, r1, r2             @ encoding: [0x01,0xfa,0x02,0xf2]
 329 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 330 // CHECK: lsleq.w  r0, r0, r1             @ encoding: [0x00,0xfa,0x01,0xf0]
 331 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 332 // CHECK: lsleq.w  r3, r1, r3             @ encoding: [0x01,0xfa,0x03,0xf3]
 333 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 334 // CHECK: lslseq.w r4, r1, r4             @ encoding: [0x11,0xfa,0x04,0xf4]
 335 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 336 // CHECK: lsleq    r7, r1                 @ encoding: [0x8f,0x40]
 337 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 338 // CHECK: lsleq.w  r8, r1, r8             @ encoding: [0x01,0xfa,0x08,0xf8]
 339 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 340 // CHECK: lsleq.w  r8, r8, r1             @ encoding: [0x08,0xfa,0x01,0xf8]
 341 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 342 // CHECK: lsleq.w  r0, r8, r0             @ encoding: [0x08,0xfa,0x00,0xf0]
 343 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 344 // CHECK: lsleq.w  r3, r3, r8             @ encoding: [0x03,0xfa,0x08,0xf3]
 345
 346 // LSR
 347     LSRS     r6, r2, r1          // Must be wide - 3 distinct registers
 348     LSRS     r2, r2, r1          // Should choose narrow
 349     LSRS     r2, r1, r2          // Should choose wide - not commutative
 350     LSRS.W   r2, r2, r1          // Explicitly wide
 351     LSRS.W   r3, r1, r3
 352     LSR      r4, r1, r4          // Must use wide encoding as not flag-setting
 353     LSRS     r7, r7, r1          // Should use narrow
 354     LSRS     r8, r1, r8          // high registers so must use wide encoding
 355     LSRS     r8, r8, r1
 356     LSRS     r2, r8, r2
 357     LSRS     r5, r5, r8
 358 // CHECK: lsrs.w  r6, r2, r1              @ encoding: [0x32,0xfa,0x01,0xf6]
 359 // CHECK: lsrs    r2, r1                  @ encoding: [0xca,0x40]
 360 // CHECK: lsrs.w  r2, r1, r2              @ encoding: [0x31,0xfa,0x02,0xf2]
 361 // CHECK: lsrs.w  r2, r2, r1              @ encoding: [0x32,0xfa,0x01,0xf2]
 362 // CHECK: lsrs.w  r3, r1, r3              @ encoding: [0x31,0xfa,0x03,0xf3]
 363 // CHECK: lsr.w   r4, r1, r4              @ encoding: [0x21,0xfa,0x04,0xf4]
 364 // CHECK: lsrs    r7, r1                  @ encoding: [0xcf,0x40]
 365 // CHECK: lsrs.w  r8, r1, r8              @ encoding: [0x31,0xfa,0x08,0xf8]
 366 // CHECK: lsrs.w  r8, r8, r1              @ encoding: [0x38,0xfa,0x01,0xf8]
 367 // CHECK: lsrs.w  r2, r8, r2              @ encoding: [0x38,0xfa,0x02,0xf2]
 368 // CHECK: lsrs.w  r5, r5, r8              @ encoding: [0x35,0xfa,0x08,0xf5]
 369
 370     IT EQ
 371     LSREQ    r6, r2, r1          // Must be wide - 3 distinct registers
 372     IT EQ
 373     LSREQ    r7, r7, r1          // Should choose narrow
 374     IT EQ
 375     LSREQ    r7, r1, r7          // Should choose wide - not commutative
 376     IT EQ
 377     LSREQ.W  r7, r7, r1          // Explicitly wide
 378     IT EQ
 379     LSREQ.W  r2, r1, r2
 380     IT EQ
 381     LSRSEQ   r0, r1, r0          // Must use wide encoding as flag-setting
 382     IT EQ
 383     LSREQ    r7, r7, r1          // Should use narrow
 384     IT EQ
 385     LSREQ    r8, r1, r8          // high registers so must use wide encoding
 386     IT EQ
 387     LSREQ    r8, r8, r1
 388     IT EQ
 389     LSREQ    r1, r8, r1
 390     IT EQ
 391     LSREQ    r4, r4, r8
 392 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 393 // CHECK: lsreq.w  r6, r2, r1             @ encoding: [0x22,0xfa,0x01,0xf6]
 394 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 395 // CHECK: lsreq    r7, r1                 @ encoding: [0xcf,0x40]
 396 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 397 // CHECK: lsreq.w  r7, r1, r7             @ encoding: [0x21,0xfa,0x07,0xf7]
 398 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 399 // CHECK: lsreq.w  r7, r7, r1             @ encoding: [0x27,0xfa,0x01,0xf7]
 400 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 401 // CHECK: lsreq.w  r2, r1, r2             @ encoding: [0x21,0xfa,0x02,0xf2]
 402 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 403 // CHECK: lsrseq.w r0, r1, r0             @ encoding: [0x31,0xfa,0x00,0xf0]
 404 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 405 // CHECK: lsreq    r7, r1                 @ encoding: [0xcf,0x40]
 406 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 407 // CHECK: lsreq.w  r8, r1, r8             @ encoding: [0x21,0xfa,0x08,0xf8]
 408 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 409 // CHECK: lsreq.w  r8, r8, r1             @ encoding: [0x28,0xfa,0x01,0xf8]
 410 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 411 // CHECK: lsreq.w  r1, r8, r1             @ encoding: [0x28,0xfa,0x01,0xf1]
 412 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 413 // CHECK: lsreq.w  r4, r4, r8             @ encoding: [0x24,0xfa,0x08,0xf4]
 414
 415 // ASR
 416     ASRS     r7, r6, r5          // Must be wide - 3 distinct registers
 417     ASRS     r0, r0, r1          // Should choose narrow
 418     ASRS     r0, r1, r0          // Should choose wide - not commutative
 419     ASRS.W   r3, r3, r1          // Explicitly wide
 420     ASRS.W   r1, r1, r1
 421     ASR      r0, r1, r0          // Must use wide encoding as not flag-setting
 422     ASRS     r7, r7, r1          // Should use narrow
 423     ASRS     r8, r1, r8          // high registers so must use wide encoding
 424     ASRS     r8, r8, r1
 425     ASRS     r5, r8, r5
 426     ASRS     r5, r5, r8
 427 // CHECK: asrs.w  r7, r6, r5              @ encoding: [0x56,0xfa,0x05,0xf7]
 428 // CHECK: asrs    r0, r1                  @ encoding: [0x08,0x41]
 429 // CHECK: asrs.w  r0, r1, r0              @ encoding: [0x51,0xfa,0x00,0xf0]
 430 // CHECK: asrs.w  r3, r3, r1              @ encoding: [0x53,0xfa,0x01,0xf3]
 431 // CHECK: asrs.w  r1, r1, r1              @ encoding: [0x51,0xfa,0x01,0xf1]
 432 // CHECK: asr.w   r0, r1, r0              @ encoding: [0x41,0xfa,0x00,0xf0]
 433 // CHECK: asrs    r7, r1                  @ encoding: [0x0f,0x41]
 434 // CHECK: asrs.w  r8, r1, r8              @ encoding: [0x51,0xfa,0x08,0xf8]
 435 // CHECK: asrs.w  r8, r8, r1              @ encoding: [0x58,0xfa,0x01,0xf8]
 436 // CHECK: asrs.w  r5, r8, r5              @ encoding: [0x58,0xfa,0x05,0xf5]
 437 // CHECK: asrs.w  r5, r5, r8              @ encoding: [0x55,0xfa,0x08,0xf5]
 438
 439     IT EQ
 440     ASREQ    r0, r2, r1          // Must be wide - 3 distinct registers
 441     IT EQ
 442     ASREQ    r2, r2, r1          // Should choose narrow
 443     IT EQ
 444     ASREQ    r1, r2, r1          // Should choose wide - not commutative
 445     IT EQ
 446     ASREQ.W  r4, r4, r1          // Explicitly wide
 447     IT EQ
 448     ASREQ.W  r6, r1, r6
 449     IT EQ
 450     ASRSEQ   r3, r1, r3          // Must use wide encoding as flag-setting
 451     IT EQ
 452     ASREQ    r7, r7, r1          // Should use narrow
 453     IT EQ
 454     ASREQ    r8, r1, r8          // high registers so must use wide encoding
 455     IT EQ
 456     ASREQ    r8, r8, r1
 457     IT EQ
 458     ASREQ    r1, r8, r1
 459     IT EQ
 460     ASREQ    r3, r3, r8
 461 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 462 // CHECK: asreq.w  r0, r2, r1             @ encoding: [0x42,0xfa,0x01,0xf0]
 463 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 464 // CHECK: asreq    r2, r1                 @ encoding: [0x0a,0x41]
 465 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 466 // CHECK: asreq.w  r1, r2, r1             @ encoding: [0x42,0xfa,0x01,0xf1]
 467 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 468 // CHECK: asreq.w  r4, r4, r1             @ encoding: [0x44,0xfa,0x01,0xf4]
 469 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 470 // CHECK: asreq.w  r6, r1, r6             @ encoding: [0x41,0xfa,0x06,0xf6]
 471 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 472 // CHECK: asrseq.w r3, r1, r3             @ encoding: [0x51,0xfa,0x03,0xf3]
 473 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 474 // CHECK: asreq    r7, r1                 @ encoding: [0x0f,0x41]
 475 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 476 // CHECK: asreq.w  r8, r1, r8             @ encoding: [0x41,0xfa,0x08,0xf8]
 477 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 478 // CHECK: asreq.w  r8, r8, r1             @ encoding: [0x48,0xfa,0x01,0xf8]
 479 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 480 // CHECK: asreq.w  r1, r8, r1             @ encoding: [0x48,0xfa,0x01,0xf1]
 481 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 482 // CHECK: asreq.w  r3, r3, r8             @ encoding: [0x43,0xfa,0x08,0xf3]
 483
 484 // ADC (commutative)
 485     ADCS     r5, r2, r1          // Must be wide - 3 distinct registers
 486     ADCS     r5, r5, r1          // Should choose narrow
 487     ADCS     r3, r1, r3          // Should choose narrow - commutative
 488     ADCS.W   r2, r2, r1          // Explicitly wide
 489     ADCS.W   r3, r1, r3
 490     ADC      r0, r1, r0          // Must use wide encoding as not flag-setting
 491     ADCS     r7, r7, r1          // Should use narrow
 492     ADCS     r7, r1, r7          // Commutative
 493     ADCS     r8, r1, r8          // high registers so must use wide encoding
 494     ADCS     r8, r8, r1
 495     ADCS     r5, r8, r5
 496     ADCS     r2, r2, r8
 497     ADCS     r3, r3, r1, lsl #1  // Must use wide - shifted register
 498     ADCS     r4, r1, r4, lsr #1
 499 // CHECK: adcs.w  r5, r2, r1              @ encoding: [0x52,0xeb,0x01,0x05]
 500 // CHECK: adcs    r5, r1                  @ encoding: [0x4d,0x41]
 501 // CHECK: adcs    r3, r1                  @ encoding: [0x4b,0x41]
 502 // CHECK: adcs.w  r2, r2, r1              @ encoding: [0x52,0xeb,0x01,0x02]
 503 // CHECK: adcs.w  r3, r1, r3              @ encoding: [0x51,0xeb,0x03,0x03]
 504 // CHECK: adc.w   r0, r1, r0              @ encoding: [0x41,0xeb,0x00,0x00]
 505 // CHECK: adcs    r7, r1                  @ encoding: [0x4f,0x41]
 506 // CHECK: adcs    r7, r1                  @ encoding: [0x4f,0x41]
 507 // CHECK: adcs.w  r8, r1, r8              @ encoding: [0x51,0xeb,0x08,0x08]
 508 // CHECK: adcs.w  r8, r8, r1              @ encoding: [0x58,0xeb,0x01,0x08]
 509 // CHECK: adcs.w  r5, r8, r5              @ encoding: [0x58,0xeb,0x05,0x05]
 510 // CHECK: adcs.w  r2, r2, r8              @ encoding: [0x52,0xeb,0x08,0x02]
 511 // CHECK: adcs.w  r3, r3, r1, lsl #1      @ encoding: [0x53,0xeb,0x41,0x03]
 512 // CHECK: adcs.w  r4, r1, r4, lsr #1      @ encoding: [0x51,0xeb,0x54,0x04]
 513
 514     IT EQ
 515     ADCEQ    r1, r2, r3          // Must be wide - 3 distinct registers
 516     IT EQ
 517     ADCEQ    r1, r1, r1          // Should choose narrow
 518     IT EQ
 519     ADCEQ    r3, r1, r3          // Should choose narrow - commutative
 520     IT EQ
 521     ADCEQ.W  r3, r3, r1          // Explicitly wide
 522     IT EQ
 523     ADCEQ.W  r0, r1, r0
 524     IT EQ
 525     ADCSEQ   r3, r1, r3          // Must use wide encoding as flag-setting
 526     IT EQ
 527     ADCEQ    r7, r7, r1          // Should use narrow
 528     IT EQ
 529     ADCEQ    r7, r1, r7          // Commutative
 530     IT EQ
 531     ADCEQ    r8, r1, r8          // high registers so must use wide encoding
 532     IT EQ
 533     ADCEQ    r8, r8, r1
 534     IT EQ
 535     ADCEQ    r3, r8, r3
 536     IT EQ
 537     ADCEQ    r1, r1, r8
 538     IT EQ
 539     ADCEQ    r2, r2, r1, lsl #1  // Must use wide - shifted register
 540     IT EQ
 541     ADCEQ    r1, r1, r1, lsr #1
 542 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 543 // CHECK: adceq.w  r1, r2, r3             @ encoding: [0x42,0xeb,0x03,0x01]
 544 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 545 // CHECK: adceq    r1, r1                 @ encoding: [0x49,0x41]
 546 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 547 // CHECK: adceq    r3, r1                 @ encoding: [0x4b,0x41]
 548 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 549 // CHECK: adceq.w  r3, r3, r1             @ encoding: [0x43,0xeb,0x01,0x03]
 550 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 551 // CHECK: adceq.w  r0, r1, r0             @ encoding: [0x41,0xeb,0x00,0x00]
 552 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 553 // CHECK: adcseq.w r3, r1, r3             @ encoding: [0x51,0xeb,0x03,0x03]
 554 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 555 // CHECK: adceq    r7, r1                 @ encoding: [0x4f,0x41]
 556 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 557 // CHECK: adceq    r7, r1                 @ encoding: [0x4f,0x41]
 558 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 559 // CHECK: adceq.w  r8, r1, r8             @ encoding: [0x41,0xeb,0x08,0x08]
 560 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 561 // CHECK: adceq.w  r8, r8, r1             @ encoding: [0x48,0xeb,0x01,0x08]
 562 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 563 // CHECK: adceq.w  r3, r8, r3             @ encoding: [0x48,0xeb,0x03,0x03]
 564 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 565 // CHECK: adceq.w  r1, r1, r8             @ encoding: [0x41,0xeb,0x08,0x01]
 566 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 567 // CHECK: adceq.w  r2, r2, r1, lsl #1     @ encoding: [0x42,0xeb,0x41,0x02]
 568 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 569 // CHECK: adceq.w  r1, r1, r1, lsr #1     @ encoding: [0x41,0xeb,0x51,0x01]
 570
 571 // SBC
 572     SBCS     r3, r2, r1          // Must be wide - 3 distinct registers
 573     SBCS     r4, r4, r1          // Should choose narrow
 574     SBCS     r1, r4, r1          // Should choose wide - not commutative
 575     SBCS.W   r4, r4, r1          // Explicitly wide
 576     SBCS.W   r2, r1, r2
 577     SBC      r0, r1, r0          // Must use wide encoding as not flag-setting
 578     SBCS     r7, r7, r1          // Should use narrow
 579     SBCS     r8, r1, r8          // high registers so must use wide encoding
 580     SBCS     r8, r8, r1
 581     SBCS     r4, r8, r4
 582     SBCS     r3, r3, r8
 583     SBCS     r2, r2, r1, lsl #1  // Must use wide - shifted register
 584     SBCS     r5, r1, r5, lsr #1
 585 // CHECK: sbcs.w  r3, r2, r1              @ encoding: [0x72,0xeb,0x01,0x03]
 586 // CHECK: sbcs    r4, r1                  @ encoding: [0x8c,0x41]
 587 // CHECK: sbcs.w  r1, r4, r1              @ encoding: [0x74,0xeb,0x01,0x01]
 588 // CHECK: sbcs.w  r4, r4, r1              @ encoding: [0x74,0xeb,0x01,0x04]
 589 // CHECK: sbcs.w  r2, r1, r2              @ encoding: [0x71,0xeb,0x02,0x02]
 590 // CHECK: sbc.w   r0, r1, r0              @ encoding: [0x61,0xeb,0x00,0x00]
 591 // CHECK: sbcs    r7, r1                  @ encoding: [0x8f,0x41]
 592 // CHECK: sbcs.w  r8, r1, r8              @ encoding: [0x71,0xeb,0x08,0x08]
 593 // CHECK: sbcs.w  r8, r8, r1              @ encoding: [0x78,0xeb,0x01,0x08]
 594 // CHECK: sbcs.w  r4, r8, r4              @ encoding: [0x78,0xeb,0x04,0x04]
 595 // CHECK: sbcs.w  r3, r3, r8              @ encoding: [0x73,0xeb,0x08,0x03]
 596 // CHECK: sbcs.w  r2, r2, r1, lsl #1      @ encoding: [0x72,0xeb,0x41,0x02]
 597 // CHECK: sbcs.w  r5, r1, r5, lsr #1      @ encoding: [0x71,0xeb,0x55,0x05]
 598
 599     IT EQ
 600     SBCEQ    r5, r2, r1          // Must be wide - 3 distinct registers
 601     IT EQ
 602     SBCEQ    r5, r5, r1          // Should choose narrow
 603     IT EQ
 604     SBCEQ    r1, r5, r1          // Should choose narrow
 605     IT EQ
 606     SBCEQ.W  r5, r5, r1          // Explicitly wide
 607     IT EQ
 608     SBCEQ.W  r0, r1, r0
 609     IT EQ
 610     SBCSEQ   r2, r1, r2          // Must use wide encoding as flag-setting
 611     IT EQ
 612     SBCEQ    r7, r7, r1          // Should use narrow
 613     IT EQ
 614     SBCEQ    r8, r1, r8          // high registers so must use wide encoding
 615     IT EQ
 616     SBCEQ    r8, r8, r1
 617     IT EQ
 618     SBCEQ    r7, r8, r7
 619     IT EQ
 620     SBCEQ    r7, r7, r8
 621     IT EQ
 622     SBCEQ    r2, r2, r1, lsl #1  // Must use wide - shifted register
 623     IT EQ
 624     SBCEQ    r5, r1, r5, lsr #1
 625 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 626 // CHECK: sbceq.w  r5, r2, r1             @ encoding: [0x62,0xeb,0x01,0x05]
 627 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 628 // CHECK: sbceq    r5, r1                 @ encoding: [0x8d,0x41]
 629 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 630 // CHECK: sbceq.w  r1, r5, r1             @ encoding: [0x65,0xeb,0x01,0x01]
 631 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 632 // CHECK: sbceq.w  r5, r5, r1             @ encoding: [0x65,0xeb,0x01,0x05]
 633 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 634 // CHECK: sbceq.w  r0, r1, r0             @ encoding: [0x61,0xeb,0x00,0x00]
 635 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 636 // CHECK: sbcseq.w r2, r1, r2             @ encoding: [0x71,0xeb,0x02,0x02]
 637 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 638 // CHECK: sbceq    r7, r1                 @ encoding: [0x8f,0x41]
 639 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 640 // CHECK: sbceq.w  r8, r1, r8             @ encoding: [0x61,0xeb,0x08,0x08]
 641 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 642 // CHECK: sbceq.w  r8, r8, r1             @ encoding: [0x68,0xeb,0x01,0x08]
 643 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 644 // CHECK: sbceq.w  r7, r8, r7             @ encoding: [0x68,0xeb,0x07,0x07]
 645 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 646 // CHECK: sbceq.w  r7, r7, r8             @ encoding: [0x67,0xeb,0x08,0x07]
 647 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 648 // CHECK: sbceq.w  r2, r2, r1, lsl #1     @ encoding: [0x62,0xeb,0x41,0x02]
 649 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 650 // CHECK: sbceq.w  r5, r1, r5, lsr #1     @ encoding: [0x61,0xeb,0x55,0x05]
 651
 652 // ROR
 653     RORS     r3, r2, r1          // Must be wide - 3 distinct registers
 654     RORS     r0, r0, r1          // Should choose narrow
 655     RORS     r1, r0, r1          // Should choose wide - not commutative
 656     RORS.W   r2, r2, r1          // Explicitly wide
 657     RORS.W   r2, r1, r2
 658     ROR      r5, r1, r5          // Must use wide encoding as not flag-setting
 659     RORS     r7, r7, r1          // Should use narrow
 660     RORS     r8, r1, r8          // high registers so must use wide encoding
 661     RORS     r8, r8, r1
 662     RORS     r6, r8, r6
 663     RORS     r6, r6, r8
 664 // CHECK: rors.w  r3, r2, r1              @ encoding: [0x72,0xfa,0x01,0xf3]
 665 // CHECK: rors    r0, r1                  @ encoding: [0xc8,0x41]
 666 // CHECK: rors.w  r1, r0, r1              @ encoding: [0x70,0xfa,0x01,0xf1]
 667 // CHECK: rors.w  r2, r2, r1              @ encoding: [0x72,0xfa,0x01,0xf2]
 668 // CHECK: rors.w  r2, r1, r2              @ encoding: [0x71,0xfa,0x02,0xf2]
 669 // CHECK: ror.w   r5, r1, r5              @ encoding: [0x61,0xfa,0x05,0xf5]
 670 // CHECK: rors    r7, r1                  @ encoding: [0xcf,0x41]
 671 // CHECK: rors.w  r8, r1, r8              @ encoding: [0x71,0xfa,0x08,0xf8]
 672 // CHECK: rors.w  r8, r8, r1              @ encoding: [0x78,0xfa,0x01,0xf8]
 673 // CHECK: rors.w  r6, r8, r6              @ encoding: [0x78,0xfa,0x06,0xf6]
 674 // CHECK: rors.w  r6, r6, r8              @ encoding: [0x76,0xfa,0x08,0xf6]
 675
 676     IT EQ
 677     ROREQ    r4, r2, r1          // Must be wide - 3 distinct registers
 678     IT EQ
 679     ROREQ    r4, r4, r1          // Should choose narrow
 680     IT EQ
 681     ROREQ    r1, r4, r1          // Should choose wide - not commutative
 682     IT EQ
 683     ROREQ.W  r4, r4, r1          // Explicitly wide
 684     IT EQ
 685     ROREQ.W  r0, r1, r0
 686     IT EQ
 687     RORSEQ   r0, r1, r0          // Must use wide encoding as flag-setting
 688     IT EQ
 689     ROREQ    r7, r7, r1          // Should use narrow
 690     IT EQ
 691     ROREQ    r8, r1, r8          // high registers so must use wide encoding
 692     IT EQ
 693     ROREQ    r8, r8, r1
 694     IT EQ
 695     ROREQ    r3, r8, r3
 696     IT EQ
 697     ROREQ    r1, r1, r8
 698 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 699 // CHECK: roreq.w  r4, r2, r1             @ encoding: [0x62,0xfa,0x01,0xf4]
 700 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 701 // CHECK: roreq    r4, r1                 @ encoding: [0xcc,0x41]
 702 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 703 // CHECK: roreq.w  r1, r4, r1             @ encoding: [0x64,0xfa,0x01,0xf1]
 704 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 705 // CHECK: roreq.w  r4, r4, r1             @ encoding: [0x64,0xfa,0x01,0xf4]
 706 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 707 // CHECK: roreq.w  r0, r1, r0             @ encoding: [0x61,0xfa,0x00,0xf0]
 708 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 709 // CHECK: rorseq.w r0, r1, r0             @ encoding: [0x71,0xfa,0x00,0xf0]
 710 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 711 // CHECK: roreq    r7, r1                 @ encoding: [0xcf,0x41]
 712 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 713 // CHECK: roreq.w  r8, r1, r8             @ encoding: [0x61,0xfa,0x08,0xf8]
 714 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 715 // CHECK: roreq.w  r8, r8, r1             @ encoding: [0x68,0xfa,0x01,0xf8]
 716 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 717 // CHECK: roreq.w  r3, r8, r3             @ encoding: [0x68,0xfa,0x03,0xf3]
 718 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 719 // CHECK: roreq.w  r1, r1, r8             @ encoding: [0x61,0xfa,0x08,0xf1]
 720
 721 // TST - only two register version available
 722 // RSB - only two register version available
 723 // CMP - only two register version available
 724 // CMN - only two register version available
 725
 726 // ORR (commutative)
 727     ORRS     r7, r2, r1          // Must be wide - 3 distinct registers
 728     ORRS     r2, r2, r1          // Should choose narrow
 729     ORRS     r3, r1, r3          // Should choose narrow - commutative
 730     ORRS.W   r4, r4, r1          // Explicitly wide
 731     ORRS.W   r5, r1, r5
 732     ORR      r2, r1, r2          // Must use wide encoding as not flag-setting
 733     ORRS     r7, r7, r1          // Should use narrow
 734     ORRS     r7, r1, r7          // Commutative
 735     ORRS     r8, r1, r8          // high registers so must use wide encoding
 736     ORRS     r8, r8, r1
 737     ORRS     r1, r8, r1
 738     ORRS     r0, r0, r8
 739     ORRS     r1, r1, r1, lsl #1  // Must use wide - shifted register
 740     ORRS     r0, r1, r0, lsr #1
 741 // CHECK: orrs.w  r7, r2, r1              @ encoding: [0x52,0xea,0x01,0x07]
 742 // CHECK: orrs    r2, r1                  @ encoding: [0x0a,0x43]
 743 // CHECK: orrs    r3, r1                  @ encoding: [0x0b,0x43]
 744 // CHECK: orrs.w  r4, r4, r1              @ encoding: [0x54,0xea,0x01,0x04]
 745 // CHECK: orrs.w  r5, r1, r5              @ encoding: [0x51,0xea,0x05,0x05]
 746 // CHECK: orr.w   r2, r1, r2              @ encoding: [0x41,0xea,0x02,0x02]
 747 // CHECK: orrs    r7, r1                  @ encoding: [0x0f,0x43]
 748 // CHECK: orrs    r7, r1                  @ encoding: [0x0f,0x43]
 749 // CHECK: orrs.w  r8, r1, r8              @ encoding: [0x51,0xea,0x08,0x08]
 750 // CHECK: orrs.w  r8, r8, r1              @ encoding: [0x58,0xea,0x01,0x08]
 751 // CHECK: orrs.w  r1, r8, r1              @ encoding: [0x58,0xea,0x01,0x01]
 752 // CHECK: orrs.w  r0, r0, r8              @ encoding: [0x50,0xea,0x08,0x00]
 753 // CHECK: orrs.w  r1, r1, r1, lsl #1      @ encoding: [0x51,0xea,0x41,0x01]
 754 // CHECK: orrs.w  r0, r1, r0, lsr #1      @ encoding: [0x51,0xea,0x50,0x00]
 755
 756     IT EQ
 757     ORREQ    r0, r2, r1          // Must be wide - 3 distinct registers
 758     IT EQ
 759     ORREQ    r5, r5, r1          // Should choose narrow
 760     IT EQ
 761     ORREQ    r5, r1, r5          // Should choose narrow - commutative
 762     IT EQ
 763     ORREQ.W  r2, r2, r1          // Explicitly wide
 764     IT EQ
 765     ORREQ.W  r3, r1, r3
 766     IT EQ
 767     ORRSEQ   r4, r1, r4          // Must use wide encoding as flag-setting
 768     IT EQ
 769     ORREQ    r7, r7, r1          // Should use narrow
 770     IT EQ
 771     ORREQ    r7, r1, r7          // Commutative
 772     IT EQ
 773     ORREQ    r8, r1, r8          // high registers so must use wide encoding
 774     IT EQ
 775     ORREQ    r8, r8, r1
 776     IT EQ
 777     ORREQ    r0, r8, r0
 778     IT EQ
 779     ORREQ    r0, r0, r8
 780     IT EQ
 781     ORREQ    r2, r2, r1, lsl #1  // Must use wide - shifted register
 782     IT EQ
 783     ORREQ    r2, r1, r2, lsr #1
 784 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 785 // CHECK: orreq.w  r0, r2, r1             @ encoding: [0x42,0xea,0x01,0x00]
 786 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 787 // CHECK: orreq    r5, r1                 @ encoding: [0x0d,0x43]
 788 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 789 // CHECK: orreq    r5, r1                 @ encoding: [0x0d,0x43]
 790 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 791 // CHECK: orreq.w  r2, r2, r1             @ encoding: [0x42,0xea,0x01,0x02]
 792 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 793 // CHECK: orreq.w  r3, r1, r3             @ encoding: [0x41,0xea,0x03,0x03]
 794 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 795 // CHECK: orrseq.w r4, r1, r4             @ encoding: [0x51,0xea,0x04,0x04]
 796 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 797 // CHECK: orreq    r7, r1                 @ encoding: [0x0f,0x43]
 798 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 799 // CHECK: orreq    r7, r1                 @ encoding: [0x0f,0x43]
 800 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 801 // CHECK: orreq.w  r8, r1, r8             @ encoding: [0x41,0xea,0x08,0x08]
 802 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 803 // CHECK: orreq.w  r8, r8, r1             @ encoding: [0x48,0xea,0x01,0x08]
 804 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 805 // CHECK: orreq.w  r0, r8, r0             @ encoding: [0x48,0xea,0x00,0x00]
 806 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 807 // CHECK: orreq.w  r0, r0, r8             @ encoding: [0x40,0xea,0x08,0x00]
 808 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 809 // CHECK: orreq.w  r2, r2, r1, lsl #1     @ encoding: [0x42,0xea,0x41,0x02]
 810 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 811 // CHECK: orreq.w  r2, r1, r2, lsr #1     @ encoding: [0x41,0xea,0x52,0x02]
 812
 813 // MUL - not affected by this change
 814
 815 // BIC
 816     BICS     r3, r2, r1          // Must be wide - 3 distinct registers
 817     BICS     r2, r2, r1          // Should choose narrow
 818     BICS     r1, r2, r1          // Should choose wide - not commutative
 819     BICS.W   r2, r2, r1          // Explicitly wide
 820     BICS.W   r0, r1, r0
 821     BIC      r0, r1, r0          // Must use wide encoding as not flag-setting
 822     BICS     r7, r7, r1          // Should use narrow
 823     BICS     r8, r1, r8          // high registers so must use wide encoding
 824     BICS     r8, r8, r1
 825     BICS     r7, r8, r7
 826     BICS     r5, r5, r8
 827     BICS     r3, r3, r1, lsl #1  // Must use wide - shifted register
 828     BICS     r4, r1, r4, lsr #1
 829 // CHECK: bics.w  r3, r2, r1              @ encoding: [0x32,0xea,0x01,0x03]
 830 // CHECK: bics    r2, r1                  @ encoding: [0x8a,0x43]
 831 // CHECK: bics.w  r1, r2, r1              @ encoding: [0x32,0xea,0x01,0x01]
 832 // CHECK: bics.w  r2, r2, r1              @ encoding: [0x32,0xea,0x01,0x02]
 833 // CHECK: bics.w  r0, r1, r0              @ encoding: [0x31,0xea,0x00,0x00]
 834 // CHECK: bic.w   r0, r1, r0              @ encoding: [0x21,0xea,0x00,0x00]
 835 // CHECK: bics    r7, r1                  @ encoding: [0x8f,0x43]
 836 // CHECK: bics.w  r8, r1, r8              @ encoding: [0x31,0xea,0x08,0x08]
 837 // CHECK: bics.w  r8, r8, r1              @ encoding: [0x38,0xea,0x01,0x08]
 838 // CHECK: bics.w  r7, r8, r7              @ encoding: [0x38,0xea,0x07,0x07]
 839 // CHECK: bics.w  r5, r5, r8              @ encoding: [0x35,0xea,0x08,0x05]
 840 // CHECK: bics.w  r3, r3, r1, lsl #1      @ encoding: [0x33,0xea,0x41,0x03]
 841 // CHECK: bics.w  r4, r1, r4, lsr #1      @ encoding: [0x31,0xea,0x54,0x04]
 842
 843     IT EQ
 844     BICEQ    r0, r2, r1          // Must be wide - 3 distinct registers
 845     IT EQ
 846     BICEQ    r5, r5, r1          // Should choose narrow
 847     IT EQ
 848     BICEQ    r1, r5, r1          // Should choose wide - not commutative
 849     IT EQ
 850     BICEQ.W  r4, r4, r1          // Explicitly wide
 851     IT EQ
 852     BICEQ.W  r2, r1, r2
 853     IT EQ
 854     BICSEQ   r5, r1, r5          // Must use wide encoding as flag-setting
 855     IT EQ
 856     BICEQ    r7, r7, r1          // Should use narrow
 857     IT EQ
 858     BICEQ    r8, r1, r8          // high registers so must use wide encoding
 859     IT EQ
 860     BICEQ    r8, r8, r1
 861     IT EQ
 862     BICEQ    r0, r8, r0
 863     IT EQ
 864     BICEQ    r2, r2, r8
 865     IT EQ
 866     BICEQ    r4, r4, r1, lsl #1  // Must use wide - shifted register
 867     IT EQ
 868     BICEQ    r5, r1, r5, lsr #1
 869 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 870 // CHECK: biceq.w  r0, r2, r1             @ encoding: [0x22,0xea,0x01,0x00]
 871 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 872 // CHECK: biceq    r5, r1                 @ encoding: [0x8d,0x43]
 873 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 874 // CHECK: biceq.w  r1, r5, r1             @ encoding: [0x25,0xea,0x01,0x01]
 875 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 876 // CHECK: biceq.w  r4, r4, r1             @ encoding: [0x24,0xea,0x01,0x04]
 877 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 878 // CHECK: biceq.w  r2, r1, r2             @ encoding: [0x21,0xea,0x02,0x02]
 879 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 880 // CHECK: bicseq.w r5, r1, r5             @ encoding: [0x31,0xea,0x05,0x05]
 881 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 882 // CHECK: biceq    r7, r1                 @ encoding: [0x8f,0x43]
 883 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 884 // CHECK: biceq.w  r8, r1, r8             @ encoding: [0x21,0xea,0x08,0x08]
 885 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 886 // CHECK: biceq.w  r8, r8, r1             @ encoding: [0x28,0xea,0x01,0x08]
 887 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 888 // CHECK: biceq.w  r0, r8, r0             @ encoding: [0x28,0xea,0x00,0x00]
 889 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 890 // CHECK: biceq.w  r2, r2, r8             @ encoding: [0x22,0xea,0x08,0x02]
 891 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 892 // CHECK: biceq.w  r4, r4, r1, lsl #1     @ encoding: [0x24,0xea,0x41,0x04]
 893 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 894 // CHECK: biceq.w  r5, r1, r5, lsr #1     @ encoding: [0x21,0xea,0x55,0x05]
 895
 896 // CMN - only two register version available