1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s
3 declare i32 @llvm.x86.avx512.kortestz.w(i16, i16) nounwind readnone
4 ; CHECK-LABEL: test_kortestz
7 define i32 @test_kortestz(i16 %a0, i16 %a1) {
8 %res = call i32 @llvm.x86.avx512.kortestz.w(i16 %a0, i16 %a1)
12 declare i32 @llvm.x86.avx512.kortestc.w(i16, i16) nounwind readnone
13 ; CHECK-LABEL: test_kortestc
16 define i32 @test_kortestc(i16 %a0, i16 %a1) {
17 %res = call i32 @llvm.x86.avx512.kortestc.w(i16 %a0, i16 %a1)
21 declare i16 @llvm.x86.avx512.kand.w(i16, i16) nounwind readnone
22 ; CHECK-LABEL: test_kand
25 define i16 @test_kand(i16 %a0, i16 %a1) {
26 %t1 = call i16 @llvm.x86.avx512.kand.w(i16 %a0, i16 8)
27 %t2 = call i16 @llvm.x86.avx512.kand.w(i16 %t1, i16 %a1)
31 declare i16 @llvm.x86.avx512.knot.w(i16) nounwind readnone
32 ; CHECK-LABEL: test_knot
34 define i16 @test_knot(i16 %a0) {
35 %res = call i16 @llvm.x86.avx512.knot.w(i16 %a0)
39 declare i16 @llvm.x86.avx512.kunpck.bw(i16, i16) nounwind readnone
41 ; CHECK-LABEL: unpckbw_test
44 define i16 @unpckbw_test(i16 %a0, i16 %a1) {
45 %res = call i16 @llvm.x86.avx512.kunpck.bw(i16 %a0, i16 %a1)
49 define <16 x float> @test_rcp_ps_512(<16 x float> %a0) {
50 ; CHECK: vrcp14ps {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x4c,0xc0]
51 %res = call <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1) ; <<16 x float>> [#uses=1]
54 declare <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float>, <16 x float>, i16) nounwind readnone
56 define <8 x double> @test_rcp_pd_512(<8 x double> %a0) {
57 ; CHECK: vrcp14pd {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x4c,0xc0]
58 %res = call <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1) ; <<8 x double>> [#uses=1]
61 declare <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double>, <8 x double>, i8) nounwind readnone
63 declare <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double>, i32, <8 x double>, i8, i32)
65 define <8 x double> @test7(<8 x double> %a) {
66 ; CHECK: vrndscalepd {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x0b]
67 %res = call <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double> %a, i32 11, <8 x double> %a, i8 -1, i32 4)
71 declare <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float>, i32, <16 x float>, i16, i32)
73 define <16 x float> @test8(<16 x float> %a) {
74 ; CHECK: vrndscaleps {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x0b]
75 %res = call <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float> %a, i32 11, <16 x float> %a, i16 -1, i32 4)
79 define <16 x float> @test_rsqrt_ps_512(<16 x float> %a0) {
80 ; CHECK: vrsqrt14ps {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x4e,0xc0]
81 %res = call <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1) ; <<16 x float>> [#uses=1]
84 declare <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float>, <16 x float>, i16) nounwind readnone
86 define <4 x float> @test_rsqrt14_ss(<4 x float> %a0) {
87 ; CHECK: vrsqrt14ss {{.*}}encoding: [0x62,0xf2,0x7d,0x08,0x4f,0xc0]
88 %res = call <4 x float> @llvm.x86.avx512.rsqrt14.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1) ; <<4 x float>> [#uses=1]
91 declare <4 x float> @llvm.x86.avx512.rsqrt14.ss(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone
93 define <4 x float> @test_rcp14_ss(<4 x float> %a0) {
94 ; CHECK: vrcp14ss {{.*}}encoding: [0x62,0xf2,0x7d,0x08,0x4d,0xc0]
95 %res = call <4 x float> @llvm.x86.avx512.rcp14.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1) ; <<4 x float>> [#uses=1]
98 declare <4 x float> @llvm.x86.avx512.rcp14.ss(<4 x float>, <4 x float>, <4 x float>, i8) nounwind readnone
100 define <8 x double> @test_sqrt_pd_512(<8 x double> %a0) {
101 ; CHECK-LABEL: test_sqrt_pd_512
103 %res = call <8 x double> @llvm.x86.avx512.mask.sqrt.pd.512(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1, i32 4)
104 ret <8 x double> %res
106 declare <8 x double> @llvm.x86.avx512.mask.sqrt.pd.512(<8 x double>, <8 x double>, i8, i32) nounwind readnone
108 define <16 x float> @test_sqrt_ps_512(<16 x float> %a0) {
109 ; CHECK-LABEL: test_sqrt_ps_512
111 %res = call <16 x float> @llvm.x86.avx512.mask.sqrt.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 4)
112 ret <16 x float> %res
114 define <16 x float> @test_sqrt_round_ps_512(<16 x float> %a0) {
115 ; CHECK-LABEL: test_sqrt_round_ps_512
116 ; CHECK: vsqrtps {rz-sae}
117 %res = call <16 x float> @llvm.x86.avx512.mask.sqrt.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 3)
118 ret <16 x float> %res
120 declare <16 x float> @llvm.x86.avx512.mask.sqrt.ps.512(<16 x float>, <16 x float>, i16, i32) nounwind readnone
122 define <8 x double> @test_getexp_pd_512(<8 x double> %a0) {
123 ; CHECK-LABEL: test_getexp_pd_512
125 %res = call <8 x double> @llvm.x86.avx512.mask.getexp.pd.512(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1, i32 4)
126 ret <8 x double> %res
128 define <8 x double> @test_getexp_round_pd_512(<8 x double> %a0) {
129 ; CHECK-LABEL: test_getexp_round_pd_512
130 ; CHECK: vgetexppd {sae}
131 %res = call <8 x double> @llvm.x86.avx512.mask.getexp.pd.512(<8 x double> %a0, <8 x double> zeroinitializer, i8 -1, i32 8)
132 ret <8 x double> %res
134 declare <8 x double> @llvm.x86.avx512.mask.getexp.pd.512(<8 x double>, <8 x double>, i8, i32) nounwind readnone
136 define <16 x float> @test_getexp_ps_512(<16 x float> %a0) {
137 ; CHECK-LABEL: test_getexp_ps_512
139 %res = call <16 x float> @llvm.x86.avx512.mask.getexp.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 4)
140 ret <16 x float> %res
143 define <16 x float> @test_getexp_round_ps_512(<16 x float> %a0) {
144 ; CHECK-LABEL: test_getexp_round_ps_512
145 ; CHECK: vgetexpps {sae}
146 %res = call <16 x float> @llvm.x86.avx512.mask.getexp.ps.512(<16 x float> %a0, <16 x float> zeroinitializer, i16 -1, i32 8)
147 ret <16 x float> %res
149 declare <16 x float> @llvm.x86.avx512.mask.getexp.ps.512(<16 x float>, <16 x float>, i16, i32) nounwind readnone
151 define <4 x float> @test_sqrt_ss(<4 x float> %a0, <4 x float> %a1) {
152 ; CHECK: vsqrtss {{.*}}encoding: [0x62
153 %res = call <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
156 declare <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float>, <4 x float>) nounwind readnone
158 define <2 x double> @test_sqrt_sd(<2 x double> %a0, <2 x double> %a1) {
159 ; CHECK: vsqrtsd {{.*}}encoding: [0x62
160 %res = call <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
161 ret <2 x double> %res
163 declare <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double>, <2 x double>) nounwind readnone
165 define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) {
166 ; CHECK: vcvtsd2si {{.*}}encoding: [0x62
167 %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
170 declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
172 define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) {
173 ; CHECK: vcvtsi2sdq {{.*}}encoding: [0x62
174 %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
175 ret <2 x double> %res
177 declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
179 define <2 x double> @test_x86_avx512_cvtusi642sd(<2 x double> %a0, i64 %a1) {
180 ; CHECK: vcvtusi2sdq {{.*}}encoding: [0x62
181 %res = call <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
182 ret <2 x double> %res
184 declare <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double>, i64) nounwind readnone
186 define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
187 ; CHECK: vcvttsd2si {{.*}}encoding: [0x62
188 %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
191 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
194 define i64 @test_x86_sse_cvtss2si64(<4 x float> %a0) {
195 ; CHECK: vcvtss2si {{.*}}encoding: [0x62
196 %res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0) ; <i64> [#uses=1]
199 declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone
202 define <4 x float> @test_x86_sse_cvtsi642ss(<4 x float> %a0, i64 %a1) {
203 ; CHECK: vcvtsi2ssq {{.*}}encoding: [0x62
204 %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1]
207 declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
210 define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) {
211 ; CHECK: vcvttss2si {{.*}}encoding: [0x62
212 %res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0) ; <i64> [#uses=1]
215 declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone
217 define i64 @test_x86_avx512_cvtsd2usi64(<2 x double> %a0) {
218 ; CHECK: vcvtsd2usi {{.*}}encoding: [0x62
219 %res = call i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double> %a0) ; <i64> [#uses=1]
222 declare i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double>) nounwind readnone
224 define <16 x float> @test_x86_vcvtph2ps_512(<16 x i16> %a0) {
225 ; CHECK: vcvtph2ps %ymm0, %zmm0 ## encoding: [0x62,0xf2,0x7d,0x48,0x13,0xc0]
226 %res = call <16 x float> @llvm.x86.avx512.mask.vcvtph2ps.512(<16 x i16> %a0, <16 x float> zeroinitializer, i16 -1, i32 4)
227 ret <16 x float> %res
229 declare <16 x float> @llvm.x86.avx512.mask.vcvtph2ps.512(<16 x i16>, <16 x float>, i16, i32) nounwind readonly
232 define <16 x i16> @test_x86_vcvtps2ph_256(<16 x float> %a0) {
233 ; CHECK: vcvtps2ph $2, %zmm0, %ymm0 ## encoding: [0x62,0xf3,0x7d,0x48,0x1d,0xc0,0x02]
234 %res = call <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float> %a0, i32 2, <16 x i16> zeroinitializer, i16 -1)
238 declare <16 x i16> @llvm.x86.avx512.mask.vcvtps2ph.512(<16 x float>, i32, <16 x i16>, i16) nounwind readonly
240 define <16 x float> @test_x86_vbroadcast_ss_512(i8* %a0) {
241 ; CHECK: vbroadcastss
242 %res = call <16 x float> @llvm.x86.avx512.vbroadcast.ss.512(i8* %a0) ; <<16 x float>> [#uses=1]
243 ret <16 x float> %res
245 declare <16 x float> @llvm.x86.avx512.vbroadcast.ss.512(i8*) nounwind readonly
247 define <8 x double> @test_x86_vbroadcast_sd_512(i8* %a0) {
248 ; CHECK: vbroadcastsd
249 %res = call <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8* %a0) ; <<8 x double>> [#uses=1]
250 ret <8 x double> %res
252 declare <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8*) nounwind readonly
254 define <16 x float> @test_x86_vbroadcast_ss_ps_512(<4 x float> %a0) {
255 ; CHECK: vbroadcastss
256 %res = call <16 x float> @llvm.x86.avx512.vbroadcast.ss.ps.512(<4 x float> %a0) ; <<16 x float>> [#uses=1]
257 ret <16 x float> %res
259 declare <16 x float> @llvm.x86.avx512.vbroadcast.ss.ps.512(<4 x float>) nounwind readonly
261 define <8 x double> @test_x86_vbroadcast_sd_pd_512(<2 x double> %a0) {
262 ; CHECK: vbroadcastsd
263 %res = call <8 x double> @llvm.x86.avx512.vbroadcast.sd.pd.512(<2 x double> %a0) ; <<8 x double>> [#uses=1]
264 ret <8 x double> %res
266 declare <8 x double> @llvm.x86.avx512.vbroadcast.sd.pd.512(<2 x double>) nounwind readonly
268 define <16 x i32> @test_x86_pbroadcastd_512(<4 x i32> %a0) {
269 ; CHECK: vpbroadcastd
270 %res = call <16 x i32> @llvm.x86.avx512.pbroadcastd.512(<4 x i32> %a0) ; <<16 x i32>> [#uses=1]
273 declare <16 x i32> @llvm.x86.avx512.pbroadcastd.512(<4 x i32>) nounwind readonly
275 define <16 x i32> @test_x86_pbroadcastd_i32_512(i32 %a0) {
276 ; CHECK: vpbroadcastd
277 %res = call <16 x i32> @llvm.x86.avx512.pbroadcastd.i32.512(i32 %a0) ; <<16 x i32>> [#uses=1]
280 declare <16 x i32> @llvm.x86.avx512.pbroadcastd.i32.512(i32) nounwind readonly
282 define <8 x i64> @test_x86_pbroadcastq_512(<2 x i64> %a0) {
283 ; CHECK: vpbroadcastq
284 %res = call <8 x i64> @llvm.x86.avx512.pbroadcastq.512(<2 x i64> %a0) ; <<8 x i64>> [#uses=1]
287 declare <8 x i64> @llvm.x86.avx512.pbroadcastq.512(<2 x i64>) nounwind readonly
289 define <8 x i64> @test_x86_pbroadcastq_i64_512(i64 %a0) {
290 ; CHECK: vpbroadcastq
291 %res = call <8 x i64> @llvm.x86.avx512.pbroadcastq.i64.512(i64 %a0) ; <<8 x i64>> [#uses=1]
294 declare <8 x i64> @llvm.x86.avx512.pbroadcastq.i64.512(i64) nounwind readonly
296 define <16 x i32> @test_conflict_d(<16 x i32> %a) {
297 ; CHECK: movw $-1, %ax
300 %res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 -1)
304 declare <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
306 define <8 x i64> @test_conflict_q(<8 x i64> %a) {
307 ; CHECK: movb $-1, %al
310 %res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> zeroinitializer, i8 -1)
314 declare <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
316 define <16 x i32> @test_maskz_conflict_d(<16 x i32> %a, i16 %mask) {
318 %res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 %mask)
322 define <8 x i64> @test_mask_conflict_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
324 %res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
328 define <16 x i32> @test_lzcnt_d(<16 x i32> %a) {
329 ; CHECK: movw $-1, %ax
332 %res = call <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 -1)
336 declare <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
338 define <8 x i64> @test_lzcnt_q(<8 x i64> %a) {
339 ; CHECK: movb $-1, %al
342 %res = call <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64> %a, <8 x i64> zeroinitializer, i8 -1)
346 declare <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
349 define <16 x i32> @test_mask_lzcnt_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
351 %res = call <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
355 define <8 x i64> @test_mask_lzcnt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
357 %res = call <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
361 define <16 x i32> @test_ctlz_d(<16 x i32> %a) {
362 ; CHECK-LABEL: test_ctlz_d
364 %res = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %a, i1 false)
368 declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>, i1) nounwind readonly
370 define <8 x i64> @test_ctlz_q(<8 x i64> %a) {
371 ; CHECK-LABEL: test_ctlz_q
373 %res = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %a, i1 false)
377 declare <8 x i64> @llvm.ctlz.v8i64(<8 x i64>, i1) nounwind readonly
379 define <16 x float> @test_x86_mask_blend_ps_512(i16 %a0, <16 x float> %a1, <16 x float> %a2) {
380 ; CHECK: vblendmps %zmm1, %zmm0
381 %res = call <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x float> %a1, <16 x float> %a2, i16 %a0) ; <<16 x float>> [#uses=1]
382 ret <16 x float> %res
385 declare <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x float>, <16 x float>, i16) nounwind readonly
387 define <8 x double> @test_x86_mask_blend_pd_512(i8 %a0, <8 x double> %a1, <8 x double> %a2) {
388 ; CHECK: vblendmpd %zmm1, %zmm0
389 %res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a1, <8 x double> %a2, i8 %a0) ; <<8 x double>> [#uses=1]
390 ret <8 x double> %res
393 define <8 x double> @test_x86_mask_blend_pd_512_memop(<8 x double> %a, <8 x double>* %ptr, i8 %mask) {
394 ; CHECK-LABEL: test_x86_mask_blend_pd_512_memop
395 ; CHECK: vblendmpd (%
396 %b = load <8 x double>, <8 x double>* %ptr
397 %res = call <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double> %a, <8 x double> %b, i8 %mask) ; <<8 x double>> [#uses=1]
398 ret <8 x double> %res
400 declare <8 x double> @llvm.x86.avx512.mask.blend.pd.512(<8 x double>, <8 x double>, i8) nounwind readonly
402 define <16 x i32> @test_x86_mask_blend_d_512(i16 %a0, <16 x i32> %a1, <16 x i32> %a2) {
404 %res = call <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i32> %a1, <16 x i32> %a2, i16 %a0) ; <<16 x i32>> [#uses=1]
407 declare <16 x i32> @llvm.x86.avx512.mask.blend.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
409 define <8 x i64> @test_x86_mask_blend_q_512(i8 %a0, <8 x i64> %a1, <8 x i64> %a2) {
411 %res = call <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64> %a1, <8 x i64> %a2, i8 %a0) ; <<8 x i64>> [#uses=1]
414 declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
416 define <8 x i32> @test_cvtpd2udq(<8 x double> %a) {
417 ;CHECK: vcvtpd2udq {ru-sae}{{.*}}encoding: [0x62,0xf1,0xfc,0x58,0x79,0xc0]
418 %res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %a, <8 x i32>zeroinitializer, i8 -1, i32 2)
421 declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double>, <8 x i32>, i8, i32)
423 define <16 x i32> @test_cvtps2udq(<16 x float> %a) {
424 ;CHECK: vcvtps2udq {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x38,0x79,0xc0]
425 %res = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> %a, <16 x i32>zeroinitializer, i16 -1, i32 1)
428 declare <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float>, <16 x i32>, i16, i32)
430 define i16 @test_cmpps(<16 x float> %a, <16 x float> %b) {
431 ;CHECK: vcmpleps {sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x18,0xc2,0xc1,0x02]
432 %res = call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, i16 -1, i32 8)
435 declare i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> , <16 x float> , i32, i16, i32)
437 define i8 @test_cmppd(<8 x double> %a, <8 x double> %b) {
438 ;CHECK: vcmpneqpd %zmm{{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xc2,0xc1,0x04]
439 %res = call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 4, i8 -1, i32 4)
442 declare i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> , <8 x double> , i32, i8, i32)
445 define <16 x float> @test_cvtdq2ps(<16 x i32> %a) {
446 ;CHECK: vcvtdq2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x38,0x5b,0xc0]
447 %res = call <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32> %a, <16 x float>zeroinitializer, i16 -1, i32 1)
450 declare <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32>, <16 x float>, i16, i32)
452 define <16 x float> @test_cvtudq2ps(<16 x i32> %a) {
453 ;CHECK: vcvtudq2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7f,0x38,0x7a,0xc0]
454 %res = call <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32> %a, <16 x float>zeroinitializer, i16 -1, i32 1)
457 declare <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32>, <16 x float>, i16, i32)
459 define <8 x double> @test_cvtdq2pd(<8 x i32> %a) {
460 ;CHECK: vcvtdq2pd {{.*}}encoding: [0x62,0xf1,0x7e,0x48,0xe6,0xc0]
461 %res = call <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32> %a, <8 x double>zeroinitializer, i8 -1)
464 declare <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32>, <8 x double>, i8)
466 define <8 x double> @test_cvtudq2pd(<8 x i32> %a) {
467 ;CHECK: vcvtudq2pd {{.*}}encoding: [0x62,0xf1,0x7e,0x48,0x7a,0xc0]
468 %res = call <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32> %a, <8 x double>zeroinitializer, i8 -1)
471 declare <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32>, <8 x double>, i8)
474 define <8 x double> @test_vmaxpd(<8 x double> %a0, <8 x double> %a1) {
476 %res = call <8 x double> @llvm.x86.avx512.mask.max.pd.512(<8 x double> %a0, <8 x double> %a1,
477 <8 x double>zeroinitializer, i8 -1, i32 4)
478 ret <8 x double> %res
480 declare <8 x double> @llvm.x86.avx512.mask.max.pd.512(<8 x double>, <8 x double>,
481 <8 x double>, i8, i32)
483 define <8 x double> @test_vminpd(<8 x double> %a0, <8 x double> %a1) {
485 %res = call <8 x double> @llvm.x86.avx512.mask.min.pd.512(<8 x double> %a0, <8 x double> %a1,
486 <8 x double>zeroinitializer, i8 -1, i32 4)
487 ret <8 x double> %res
489 declare <8 x double> @llvm.x86.avx512.mask.min.pd.512(<8 x double>, <8 x double>,
490 <8 x double>, i8, i32)
492 define <8 x float> @test_cvtpd2ps(<8 x double> %a) {
493 ;CHECK: vcvtpd2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0xfd,0x38,0x5a,0xc0]
494 %res = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %a, <8 x float>zeroinitializer, i8 -1, i32 1)
497 declare <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double>, <8 x float>, i8, i32)
499 define <16 x i32> @test_pabsd(<16 x i32> %a) {
500 ;CHECK: vpabsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x1e,0xc0]
501 %res = call <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32> %a, <16 x i32>zeroinitializer, i16 -1)
504 declare <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32>, <16 x i32>, i16)
506 define <8 x i64> @test_pabsq(<8 x i64> %a) {
507 ;CHECK: vpabsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x1f,0xc0]
508 %res = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %a, <8 x i64>zeroinitializer, i8 -1)
511 declare <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64>, <8 x i64>, i8)
513 define i8 @test_vptestmq(<8 x i64> %a0, <8 x i64> %a1) {
514 ; CHECK: vptestmq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc1]
515 %res = call i8 @llvm.x86.avx512.mask.ptestm.q.512(<8 x i64> %a0, <8 x i64> %a1, i8 -1)
518 declare i8 @llvm.x86.avx512.mask.ptestm.q.512(<8 x i64>, <8 x i64>, i8)
520 define i16 @test_vptestmd(<16 x i32> %a0, <16 x i32> %a1) {
521 ; CHECK: vptestmd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x27,0xc1]
522 %res = call i16 @llvm.x86.avx512.mask.ptestm.d.512(<16 x i32> %a0, <16 x i32> %a1, i16 -1)
525 declare i16 @llvm.x86.avx512.mask.ptestm.d.512(<16 x i32>, <16 x i32>, i16)
527 define void @test_store1(<16 x float> %data, i8* %ptr, i16 %mask) {
528 ; CHECK: vmovups {{.*}}encoding: [0x62,0xf1,0x7c,0x49,0x11,0x07]
529 call void @llvm.x86.avx512.mask.storeu.ps.512(i8* %ptr, <16 x float> %data, i16 %mask)
533 declare void @llvm.x86.avx512.mask.storeu.ps.512(i8*, <16 x float>, i16 )
535 define void @test_store2(<8 x double> %data, i8* %ptr, i8 %mask) {
536 ; CHECK: vmovupd {{.*}}encoding: [0x62,0xf1,0xfd,0x49,0x11,0x07]
537 call void @llvm.x86.avx512.mask.storeu.pd.512(i8* %ptr, <8 x double> %data, i8 %mask)
541 declare void @llvm.x86.avx512.mask.storeu.pd.512(i8*, <8 x double>, i8)
543 define void @test_mask_store_aligned_ps(<16 x float> %data, i8* %ptr, i16 %mask) {
544 ; CHECK-LABEL: test_mask_store_aligned_ps:
546 ; CHECK-NEXT: kmovw %esi, %k1
547 ; CHECK-NEXT: vmovaps %zmm0, (%rdi) {%k1}
549 call void @llvm.x86.avx512.mask.store.ps.512(i8* %ptr, <16 x float> %data, i16 %mask)
553 declare void @llvm.x86.avx512.mask.store.ps.512(i8*, <16 x float>, i16 )
555 define void @test_mask_store_aligned_pd(<8 x double> %data, i8* %ptr, i8 %mask) {
556 ; CHECK-LABEL: test_mask_store_aligned_pd:
558 ; CHECK-NEXT: kmovw %esi, %k1
559 ; CHECK-NEXT: vmovapd %zmm0, (%rdi) {%k1}
561 call void @llvm.x86.avx512.mask.store.pd.512(i8* %ptr, <8 x double> %data, i8 %mask)
565 declare void @llvm.x86.avx512.mask.store.pd.512(i8*, <8 x double>, i8)
567 define <16 x float> @test_maskz_load_aligned_ps(<16 x float> %data, i8* %ptr, i16 %mask) {
568 ; CHECK-LABEL: test_maskz_load_aligned_ps:
570 ; CHECK-NEXT: kmovw %esi, %k1
571 ; CHECK-NEXT: vmovaps (%rdi), %zmm0 {%k1} {z}
573 %res = call <16 x float> @llvm.x86.avx512.mask.load.ps.512(i8* %ptr, <16 x float> zeroinitializer, i16 %mask)
574 ret <16 x float> %res
577 declare <16 x float> @llvm.x86.avx512.mask.load.ps.512(i8*, <16 x float>, i16)
579 define <8 x double> @test_maskz_load_aligned_pd(<8 x double> %data, i8* %ptr, i8 %mask) {
580 ; CHECK-LABEL: test_maskz_load_aligned_pd:
582 ; CHECK-NEXT: kmovw %esi, %k1
583 ; CHECK-NEXT: vmovapd (%rdi), %zmm0 {%k1} {z}
585 %res = call <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 %mask)
586 ret <8 x double> %res
589 declare <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8*, <8 x double>, i8)
591 define <16 x float> @test_load_aligned_ps(<16 x float> %data, i8* %ptr, i16 %mask) {
592 ; CHECK-LABEL: test_load_aligned_ps:
594 ; CHECK-NEXT: vmovaps (%rdi), %zmm0
596 %res = call <16 x float> @llvm.x86.avx512.mask.load.ps.512(i8* %ptr, <16 x float> zeroinitializer, i16 -1)
597 ret <16 x float> %res
600 define <8 x double> @test_load_aligned_pd(<8 x double> %data, i8* %ptr, i8 %mask) {
601 ; CHECK-LABEL: test_load_aligned_pd:
603 ; CHECK-NEXT: vmovapd (%rdi), %zmm0
605 %res = call <8 x double> @llvm.x86.avx512.mask.load.pd.512(i8* %ptr, <8 x double> zeroinitializer, i8 -1)
606 ret <8 x double> %res
609 define <16 x float> @test_vpermt2ps(<16 x float>%x, <16 x float>%y, <16 x i32>%perm) {
610 ; CHECK: vpermt2ps {{.*}}encoding: [0x62,0xf2,0x6d,0x48,0x7f,0xc1]
611 %res = call <16 x float> @llvm.x86.avx512.mask.vpermt.ps.512(<16 x i32>%perm, <16 x float>%x, <16 x float>%y, i16 -1)
612 ret <16 x float> %res
615 define <16 x float> @test_vpermt2ps_mask(<16 x float>%x, <16 x float>%y, <16 x i32>%perm, i16 %mask) {
616 ; CHECK-LABEL: test_vpermt2ps_mask:
617 ; CHECK: vpermt2ps %zmm1, %zmm2, %zmm0 {%k1} ## encoding: [0x62,0xf2,0x6d,0x49,0x7f,0xc1]
618 %res = call <16 x float> @llvm.x86.avx512.mask.vpermt.ps.512(<16 x i32>%perm, <16 x float>%x, <16 x float>%y, i16 %mask)
619 ret <16 x float> %res
622 declare <16 x float> @llvm.x86.avx512.mask.vpermt.ps.512(<16 x i32>, <16 x float>, <16 x float>, i16)
624 define <8 x i64> @test_vmovntdqa(i8 *%x) {
625 ; CHECK-LABEL: test_vmovntdqa:
626 ; CHECK: vmovntdqa (%rdi), %zmm0 ## encoding: [0x62,0xf2,0x7d,0x48,0x2a,0x07]
627 %res = call <8 x i64> @llvm.x86.avx512.movntdqa(i8* %x)
631 declare <8 x i64> @llvm.x86.avx512.movntdqa(i8*)
633 define <8 x i64> @test_valign_q(<8 x i64> %a, <8 x i64> %b) {
634 ; CHECK-LABEL: test_valign_q:
635 ; CHECK: valignq $2, %zmm1, %zmm0, %zmm0
636 %res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i8 2, <8 x i64> zeroinitializer, i8 -1)
640 define <8 x i64> @test_mask_valign_q(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src, i8 %mask) {
641 ; CHECK-LABEL: test_mask_valign_q:
642 ; CHECK: valignq $2, %zmm1, %zmm0, %zmm2 {%k1}
643 %res = call <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64> %a, <8 x i64> %b, i8 2, <8 x i64> %src, i8 %mask)
647 declare <8 x i64> @llvm.x86.avx512.mask.valign.q.512(<8 x i64>, <8 x i64>, i8, <8 x i64>, i8)
649 define <16 x i32> @test_maskz_valign_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
650 ; CHECK-LABEL: test_maskz_valign_d:
651 ; CHECK: valignd $5, %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf3,0x7d,0xc9,0x03,0xc1,0x05]
652 %res = call <16 x i32> @llvm.x86.avx512.mask.valign.d.512(<16 x i32> %a, <16 x i32> %b, i8 5, <16 x i32> zeroinitializer, i16 %mask)
656 declare <16 x i32> @llvm.x86.avx512.mask.valign.d.512(<16 x i32>, <16 x i32>, i8, <16 x i32>, i16)
658 define void @test_mask_store_ss(i8* %ptr, <4 x float> %data, i8 %mask) {
659 ; CHECK-LABEL: test_mask_store_ss
660 ; CHECK: vmovss %xmm0, (%rdi) {%k1} ## encoding: [0x62,0xf1,0x7e,0x09,0x11,0x07]
661 call void @llvm.x86.avx512.mask.store.ss(i8* %ptr, <4 x float> %data, i8 %mask)
665 declare void @llvm.x86.avx512.mask.store.ss(i8*, <4 x float>, i8 )
667 define i16 @test_pcmpeq_d(<16 x i32> %a, <16 x i32> %b) {
668 ; CHECK-LABEL: test_pcmpeq_d
669 ; CHECK: vpcmpeqd %zmm1, %zmm0, %k0 ##
670 %res = call i16 @llvm.x86.avx512.mask.pcmpeq.d.512(<16 x i32> %a, <16 x i32> %b, i16 -1)
674 define i16 @test_mask_pcmpeq_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
675 ; CHECK-LABEL: test_mask_pcmpeq_d
676 ; CHECK: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ##
677 %res = call i16 @llvm.x86.avx512.mask.pcmpeq.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
681 declare i16 @llvm.x86.avx512.mask.pcmpeq.d.512(<16 x i32>, <16 x i32>, i16)
683 define i8 @test_pcmpeq_q(<8 x i64> %a, <8 x i64> %b) {
684 ; CHECK-LABEL: test_pcmpeq_q
685 ; CHECK: vpcmpeqq %zmm1, %zmm0, %k0 ##
686 %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1)
690 define i8 @test_mask_pcmpeq_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
691 ; CHECK-LABEL: test_mask_pcmpeq_q
692 ; CHECK: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ##
693 %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
697 declare i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64>, <8 x i64>, i8)
699 define i16 @test_pcmpgt_d(<16 x i32> %a, <16 x i32> %b) {
700 ; CHECK-LABEL: test_pcmpgt_d
701 ; CHECK: vpcmpgtd %zmm1, %zmm0, %k0 ##
702 %res = call i16 @llvm.x86.avx512.mask.pcmpgt.d.512(<16 x i32> %a, <16 x i32> %b, i16 -1)
706 define i16 @test_mask_pcmpgt_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
707 ; CHECK-LABEL: test_mask_pcmpgt_d
708 ; CHECK: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ##
709 %res = call i16 @llvm.x86.avx512.mask.pcmpgt.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
713 declare i16 @llvm.x86.avx512.mask.pcmpgt.d.512(<16 x i32>, <16 x i32>, i16)
715 define i8 @test_pcmpgt_q(<8 x i64> %a, <8 x i64> %b) {
716 ; CHECK-LABEL: test_pcmpgt_q
717 ; CHECK: vpcmpgtq %zmm1, %zmm0, %k0 ##
718 %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1)
722 define i8 @test_mask_pcmpgt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
723 ; CHECK-LABEL: test_mask_pcmpgt_q
724 ; CHECK: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ##
725 %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
729 declare i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64>, <8 x i64>, i8)
731 define <8 x i16> @test_cmp_d_512(<16 x i32> %a0, <16 x i32> %a1) {
732 ; CHECK_LABEL: test_cmp_d_512
733 ; CHECK: vpcmpeqd %zmm1, %zmm0, %k0 ##
734 %res0 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 0, i16 -1)
735 %vec0 = insertelement <8 x i16> undef, i16 %res0, i32 0
736 ; CHECK: vpcmpltd %zmm1, %zmm0, %k0 ##
737 %res1 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 1, i16 -1)
738 %vec1 = insertelement <8 x i16> %vec0, i16 %res1, i32 1
739 ; CHECK: vpcmpled %zmm1, %zmm0, %k0 ##
740 %res2 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 2, i16 -1)
741 %vec2 = insertelement <8 x i16> %vec1, i16 %res2, i32 2
742 ; CHECK: vpcmpunordd %zmm1, %zmm0, %k0 ##
743 %res3 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 3, i16 -1)
744 %vec3 = insertelement <8 x i16> %vec2, i16 %res3, i32 3
745 ; CHECK: vpcmpneqd %zmm1, %zmm0, %k0 ##
746 %res4 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 4, i16 -1)
747 %vec4 = insertelement <8 x i16> %vec3, i16 %res4, i32 4
748 ; CHECK: vpcmpnltd %zmm1, %zmm0, %k0 ##
749 %res5 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 5, i16 -1)
750 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
751 ; CHECK: vpcmpnled %zmm1, %zmm0, %k0 ##
752 %res6 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 6, i16 -1)
753 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
754 ; CHECK: vpcmpordd %zmm1, %zmm0, %k0 ##
755 %res7 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 7, i16 -1)
756 %vec7 = insertelement <8 x i16> %vec6, i16 %res7, i32 7
760 define <8 x i16> @test_mask_cmp_d_512(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
761 ; CHECK_LABEL: test_mask_cmp_d_512
762 ; CHECK: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ##
763 %res0 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 0, i16 %mask)
764 %vec0 = insertelement <8 x i16> undef, i16 %res0, i32 0
765 ; CHECK: vpcmpltd %zmm1, %zmm0, %k0 {%k1} ##
766 %res1 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 1, i16 %mask)
767 %vec1 = insertelement <8 x i16> %vec0, i16 %res1, i32 1
768 ; CHECK: vpcmpled %zmm1, %zmm0, %k0 {%k1} ##
769 %res2 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 2, i16 %mask)
770 %vec2 = insertelement <8 x i16> %vec1, i16 %res2, i32 2
771 ; CHECK: vpcmpunordd %zmm1, %zmm0, %k0 {%k1} ##
772 %res3 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 3, i16 %mask)
773 %vec3 = insertelement <8 x i16> %vec2, i16 %res3, i32 3
774 ; CHECK: vpcmpneqd %zmm1, %zmm0, %k0 {%k1} ##
775 %res4 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 4, i16 %mask)
776 %vec4 = insertelement <8 x i16> %vec3, i16 %res4, i32 4
777 ; CHECK: vpcmpnltd %zmm1, %zmm0, %k0 {%k1} ##
778 %res5 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 5, i16 %mask)
779 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
780 ; CHECK: vpcmpnled %zmm1, %zmm0, %k0 {%k1} ##
781 %res6 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 6, i16 %mask)
782 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
783 ; CHECK: vpcmpordd %zmm1, %zmm0, %k0 {%k1} ##
784 %res7 = call i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 7, i16 %mask)
785 %vec7 = insertelement <8 x i16> %vec6, i16 %res7, i32 7
789 declare i16 @llvm.x86.avx512.mask.cmp.d.512(<16 x i32>, <16 x i32>, i32, i16) nounwind readnone
791 define <8 x i16> @test_ucmp_d_512(<16 x i32> %a0, <16 x i32> %a1) {
792 ; CHECK_LABEL: test_ucmp_d_512
793 ; CHECK: vpcmpequd %zmm1, %zmm0, %k0 ##
794 %res0 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 0, i16 -1)
795 %vec0 = insertelement <8 x i16> undef, i16 %res0, i32 0
796 ; CHECK: vpcmpltud %zmm1, %zmm0, %k0 ##
797 %res1 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 1, i16 -1)
798 %vec1 = insertelement <8 x i16> %vec0, i16 %res1, i32 1
799 ; CHECK: vpcmpleud %zmm1, %zmm0, %k0 ##
800 %res2 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 2, i16 -1)
801 %vec2 = insertelement <8 x i16> %vec1, i16 %res2, i32 2
802 ; CHECK: vpcmpunordud %zmm1, %zmm0, %k0 ##
803 %res3 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 3, i16 -1)
804 %vec3 = insertelement <8 x i16> %vec2, i16 %res3, i32 3
805 ; CHECK: vpcmpnequd %zmm1, %zmm0, %k0 ##
806 %res4 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 4, i16 -1)
807 %vec4 = insertelement <8 x i16> %vec3, i16 %res4, i32 4
808 ; CHECK: vpcmpnltud %zmm1, %zmm0, %k0 ##
809 %res5 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 5, i16 -1)
810 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
811 ; CHECK: vpcmpnleud %zmm1, %zmm0, %k0 ##
812 %res6 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 6, i16 -1)
813 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
814 ; CHECK: vpcmpordud %zmm1, %zmm0, %k0 ##
815 %res7 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 7, i16 -1)
816 %vec7 = insertelement <8 x i16> %vec6, i16 %res7, i32 7
820 define <8 x i16> @test_mask_ucmp_d_512(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
821 ; CHECK_LABEL: test_mask_ucmp_d_512
822 ; CHECK: vpcmpequd %zmm1, %zmm0, %k0 {%k1} ##
823 %res0 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 0, i16 %mask)
824 %vec0 = insertelement <8 x i16> undef, i16 %res0, i32 0
825 ; CHECK: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ##
826 %res1 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 1, i16 %mask)
827 %vec1 = insertelement <8 x i16> %vec0, i16 %res1, i32 1
828 ; CHECK: vpcmpleud %zmm1, %zmm0, %k0 {%k1} ##
829 %res2 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 2, i16 %mask)
830 %vec2 = insertelement <8 x i16> %vec1, i16 %res2, i32 2
831 ; CHECK: vpcmpunordud %zmm1, %zmm0, %k0 {%k1} ##
832 %res3 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 3, i16 %mask)
833 %vec3 = insertelement <8 x i16> %vec2, i16 %res3, i32 3
834 ; CHECK: vpcmpnequd %zmm1, %zmm0, %k0 {%k1} ##
835 %res4 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 4, i16 %mask)
836 %vec4 = insertelement <8 x i16> %vec3, i16 %res4, i32 4
837 ; CHECK: vpcmpnltud %zmm1, %zmm0, %k0 {%k1} ##
838 %res5 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 5, i16 %mask)
839 %vec5 = insertelement <8 x i16> %vec4, i16 %res5, i32 5
840 ; CHECK: vpcmpnleud %zmm1, %zmm0, %k0 {%k1} ##
841 %res6 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 6, i16 %mask)
842 %vec6 = insertelement <8 x i16> %vec5, i16 %res6, i32 6
843 ; CHECK: vpcmpordud %zmm1, %zmm0, %k0 {%k1} ##
844 %res7 = call i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> %a0, <16 x i32> %a1, i32 7, i16 %mask)
845 %vec7 = insertelement <8 x i16> %vec6, i16 %res7, i32 7
849 declare i16 @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32>, <16 x i32>, i32, i16) nounwind readnone
851 define <8 x i8> @test_cmp_q_512(<8 x i64> %a0, <8 x i64> %a1) {
852 ; CHECK_LABEL: test_cmp_q_512
853 ; CHECK: vpcmpeqq %zmm1, %zmm0, %k0 ##
854 %res0 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 0, i8 -1)
855 %vec0 = insertelement <8 x i8> undef, i8 %res0, i32 0
856 ; CHECK: vpcmpltq %zmm1, %zmm0, %k0 ##
857 %res1 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 1, i8 -1)
858 %vec1 = insertelement <8 x i8> %vec0, i8 %res1, i32 1
859 ; CHECK: vpcmpleq %zmm1, %zmm0, %k0 ##
860 %res2 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 2, i8 -1)
861 %vec2 = insertelement <8 x i8> %vec1, i8 %res2, i32 2
862 ; CHECK: vpcmpunordq %zmm1, %zmm0, %k0 ##
863 %res3 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 3, i8 -1)
864 %vec3 = insertelement <8 x i8> %vec2, i8 %res3, i32 3
865 ; CHECK: vpcmpneqq %zmm1, %zmm0, %k0 ##
866 %res4 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 4, i8 -1)
867 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
868 ; CHECK: vpcmpnltq %zmm1, %zmm0, %k0 ##
869 %res5 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 5, i8 -1)
870 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
871 ; CHECK: vpcmpnleq %zmm1, %zmm0, %k0 ##
872 %res6 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 6, i8 -1)
873 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
874 ; CHECK: vpcmpordq %zmm1, %zmm0, %k0 ##
875 %res7 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 -1)
876 %vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7
880 define <8 x i8> @test_mask_cmp_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
881 ; CHECK_LABEL: test_mask_cmp_q_512
882 ; CHECK: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ##
883 %res0 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 0, i8 %mask)
884 %vec0 = insertelement <8 x i8> undef, i8 %res0, i32 0
885 ; CHECK: vpcmpltq %zmm1, %zmm0, %k0 {%k1} ##
886 %res1 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 1, i8 %mask)
887 %vec1 = insertelement <8 x i8> %vec0, i8 %res1, i32 1
888 ; CHECK: vpcmpleq %zmm1, %zmm0, %k0 {%k1} ##
889 %res2 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 2, i8 %mask)
890 %vec2 = insertelement <8 x i8> %vec1, i8 %res2, i32 2
891 ; CHECK: vpcmpunordq %zmm1, %zmm0, %k0 {%k1} ##
892 %res3 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 3, i8 %mask)
893 %vec3 = insertelement <8 x i8> %vec2, i8 %res3, i32 3
894 ; CHECK: vpcmpneqq %zmm1, %zmm0, %k0 {%k1} ##
895 %res4 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 4, i8 %mask)
896 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
897 ; CHECK: vpcmpnltq %zmm1, %zmm0, %k0 {%k1} ##
898 %res5 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 5, i8 %mask)
899 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
900 ; CHECK: vpcmpnleq %zmm1, %zmm0, %k0 {%k1} ##
901 %res6 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 6, i8 %mask)
902 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
903 ; CHECK: vpcmpordq %zmm1, %zmm0, %k0 {%k1} ##
904 %res7 = call i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 %mask)
905 %vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7
909 declare i8 @llvm.x86.avx512.mask.cmp.q.512(<8 x i64>, <8 x i64>, i32, i8) nounwind readnone
911 define <8 x i8> @test_ucmp_q_512(<8 x i64> %a0, <8 x i64> %a1) {
912 ; CHECK_LABEL: test_ucmp_q_512
913 ; CHECK: vpcmpequq %zmm1, %zmm0, %k0 ##
914 %res0 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 0, i8 -1)
915 %vec0 = insertelement <8 x i8> undef, i8 %res0, i32 0
916 ; CHECK: vpcmpltuq %zmm1, %zmm0, %k0 ##
917 %res1 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 1, i8 -1)
918 %vec1 = insertelement <8 x i8> %vec0, i8 %res1, i32 1
919 ; CHECK: vpcmpleuq %zmm1, %zmm0, %k0 ##
920 %res2 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 2, i8 -1)
921 %vec2 = insertelement <8 x i8> %vec1, i8 %res2, i32 2
922 ; CHECK: vpcmpunorduq %zmm1, %zmm0, %k0 ##
923 %res3 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 3, i8 -1)
924 %vec3 = insertelement <8 x i8> %vec2, i8 %res3, i32 3
925 ; CHECK: vpcmpnequq %zmm1, %zmm0, %k0 ##
926 %res4 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 4, i8 -1)
927 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
928 ; CHECK: vpcmpnltuq %zmm1, %zmm0, %k0 ##
929 %res5 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 5, i8 -1)
930 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
931 ; CHECK: vpcmpnleuq %zmm1, %zmm0, %k0 ##
932 %res6 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 6, i8 -1)
933 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
934 ; CHECK: vpcmporduq %zmm1, %zmm0, %k0 ##
935 %res7 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 -1)
936 %vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7
940 define <8 x i8> @test_mask_ucmp_q_512(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
941 ; CHECK_LABEL: test_mask_ucmp_q_512
942 ; CHECK: vpcmpequq %zmm1, %zmm0, %k0 {%k1} ##
943 %res0 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 0, i8 %mask)
944 %vec0 = insertelement <8 x i8> undef, i8 %res0, i32 0
945 ; CHECK: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ##
946 %res1 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 1, i8 %mask)
947 %vec1 = insertelement <8 x i8> %vec0, i8 %res1, i32 1
948 ; CHECK: vpcmpleuq %zmm1, %zmm0, %k0 {%k1} ##
949 %res2 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 2, i8 %mask)
950 %vec2 = insertelement <8 x i8> %vec1, i8 %res2, i32 2
951 ; CHECK: vpcmpunorduq %zmm1, %zmm0, %k0 {%k1} ##
952 %res3 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 3, i8 %mask)
953 %vec3 = insertelement <8 x i8> %vec2, i8 %res3, i32 3
954 ; CHECK: vpcmpnequq %zmm1, %zmm0, %k0 {%k1} ##
955 %res4 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 4, i8 %mask)
956 %vec4 = insertelement <8 x i8> %vec3, i8 %res4, i32 4
957 ; CHECK: vpcmpnltuq %zmm1, %zmm0, %k0 {%k1} ##
958 %res5 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 5, i8 %mask)
959 %vec5 = insertelement <8 x i8> %vec4, i8 %res5, i32 5
960 ; CHECK: vpcmpnleuq %zmm1, %zmm0, %k0 {%k1} ##
961 %res6 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 6, i8 %mask)
962 %vec6 = insertelement <8 x i8> %vec5, i8 %res6, i32 6
963 ; CHECK: vpcmporduq %zmm1, %zmm0, %k0 {%k1} ##
964 %res7 = call i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> %a0, <8 x i64> %a1, i32 7, i8 %mask)
965 %vec7 = insertelement <8 x i8> %vec6, i8 %res7, i32 7
969 declare i8 @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64>, <8 x i64>, i32, i8) nounwind readnone
971 define <4 x float> @test_mask_vextractf32x4(<4 x float> %b, <16 x float> %a, i8 %mask) {
972 ; CHECK-LABEL: test_mask_vextractf32x4:
973 ; CHECK: vextractf32x4 $2, %zmm1, %xmm0 {%k1}
974 %res = call <4 x float> @llvm.x86.avx512.mask.vextractf32x4.512(<16 x float> %a, i8 2, <4 x float> %b, i8 %mask)
978 declare <4 x float> @llvm.x86.avx512.mask.vextractf32x4.512(<16 x float>, i8, <4 x float>, i8)
980 define <4 x i64> @test_mask_vextracti64x4(<4 x i64> %b, <8 x i64> %a, i8 %mask) {
981 ; CHECK-LABEL: test_mask_vextracti64x4:
982 ; CHECK: vextracti64x4 $2, %zmm1, %ymm0 {%k1}
983 %res = call <4 x i64> @llvm.x86.avx512.mask.vextracti64x4.512(<8 x i64> %a, i8 2, <4 x i64> %b, i8 %mask)
987 declare <4 x i64> @llvm.x86.avx512.mask.vextracti64x4.512(<8 x i64>, i8, <4 x i64>, i8)
989 define <4 x i32> @test_maskz_vextracti32x4(<16 x i32> %a, i8 %mask) {
990 ; CHECK-LABEL: test_maskz_vextracti32x4:
991 ; CHECK: vextracti32x4 $2, %zmm0, %xmm0 {%k1} {z}
992 %res = call <4 x i32> @llvm.x86.avx512.mask.vextracti32x4.512(<16 x i32> %a, i8 2, <4 x i32> zeroinitializer, i8 %mask)
996 declare <4 x i32> @llvm.x86.avx512.mask.vextracti32x4.512(<16 x i32>, i8, <4 x i32>, i8)
998 define <4 x double> @test_vextractf64x4(<8 x double> %a) {
999 ; CHECK-LABEL: test_vextractf64x4:
1000 ; CHECK: vextractf64x4 $2, %zmm0, %ymm0 ##
1001 %res = call <4 x double> @llvm.x86.avx512.mask.vextractf64x4.512(<8 x double> %a, i8 2, <4 x double> zeroinitializer, i8 -1)
1002 ret <4 x double> %res
1005 declare <4 x double> @llvm.x86.avx512.mask.vextractf64x4.512(<8 x double>, i8, <4 x double>, i8)
1007 define <16 x i32> @test_x86_avx512_pslli_d(<16 x i32> %a0) {
1008 ; CHECK-LABEL: test_x86_avx512_pslli_d
1010 %res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)
1014 define <16 x i32> @test_x86_avx512_mask_pslli_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
1015 ; CHECK-LABEL: test_x86_avx512_mask_pslli_d
1016 ; CHECK: vpslld $7, %zmm0, %zmm1 {%k1}
1017 %res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)
1021 define <16 x i32> @test_x86_avx512_maskz_pslli_d(<16 x i32> %a0, i16 %mask) {
1022 ; CHECK-LABEL: test_x86_avx512_maskz_pslli_d
1023 ; CHECK: vpslld $7, %zmm0, %zmm0 {%k1} {z}
1024 %res = call <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)
1028 declare <16 x i32> @llvm.x86.avx512.mask.pslli.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone
1030 define <8 x i64> @test_x86_avx512_pslli_q(<8 x i64> %a0) {
1031 ; CHECK-LABEL: test_x86_avx512_pslli_q
1033 %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)
1037 define <8 x i64> @test_x86_avx512_mask_pslli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
1038 ; CHECK-LABEL: test_x86_avx512_mask_pslli_q
1039 ; CHECK: vpsllq $7, %zmm0, %zmm1 {%k1}
1040 %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
1044 define <8 x i64> @test_x86_avx512_maskz_pslli_q(<8 x i64> %a0, i8 %mask) {
1045 ; CHECK-LABEL: test_x86_avx512_maskz_pslli_q
1046 ; CHECK: vpsllq $7, %zmm0, %zmm0 {%k1} {z}
1047 %res = call <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)
1051 declare <8 x i64> @llvm.x86.avx512.mask.pslli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone
1053 define <16 x i32> @test_x86_avx512_psrli_d(<16 x i32> %a0) {
1054 ; CHECK-LABEL: test_x86_avx512_psrli_d
1056 %res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)
1060 define <16 x i32> @test_x86_avx512_mask_psrli_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
1061 ; CHECK-LABEL: test_x86_avx512_mask_psrli_d
1062 ; CHECK: vpsrld $7, %zmm0, %zmm1 {%k1}
1063 %res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)
1067 define <16 x i32> @test_x86_avx512_maskz_psrli_d(<16 x i32> %a0, i16 %mask) {
1068 ; CHECK-LABEL: test_x86_avx512_maskz_psrli_d
1069 ; CHECK: vpsrld $7, %zmm0, %zmm0 {%k1} {z}
1070 %res = call <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)
1074 declare <16 x i32> @llvm.x86.avx512.mask.psrli.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone
1076 define <8 x i64> @test_x86_avx512_psrli_q(<8 x i64> %a0) {
1077 ; CHECK-LABEL: test_x86_avx512_psrli_q
1079 %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)
1083 define <8 x i64> @test_x86_avx512_mask_psrli_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
1084 ; CHECK-LABEL: test_x86_avx512_mask_psrli_q
1085 ; CHECK: vpsrlq $7, %zmm0, %zmm1 {%k1}
1086 %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
1090 define <8 x i64> @test_x86_avx512_maskz_psrli_q(<8 x i64> %a0, i8 %mask) {
1091 ; CHECK-LABEL: test_x86_avx512_maskz_psrli_q
1092 ; CHECK: vpsrlq $7, %zmm0, %zmm0 {%k1} {z}
1093 %res = call <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)
1097 declare <8 x i64> @llvm.x86.avx512.mask.psrli.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone
1099 define <16 x i32> @test_x86_avx512_psrai_d(<16 x i32> %a0) {
1100 ; CHECK-LABEL: test_x86_avx512_psrai_d
1102 %res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 -1)
1106 define <16 x i32> @test_x86_avx512_mask_psrai_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
1107 ; CHECK-LABEL: test_x86_avx512_mask_psrai_d
1108 ; CHECK: vpsrad $7, %zmm0, %zmm1 {%k1}
1109 %res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> %a1, i16 %mask)
1113 define <16 x i32> @test_x86_avx512_maskz_psrai_d(<16 x i32> %a0, i16 %mask) {
1114 ; CHECK-LABEL: test_x86_avx512_maskz_psrai_d
1115 ; CHECK: vpsrad $7, %zmm0, %zmm0 {%k1} {z}
1116 %res = call <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32> %a0, i32 7, <16 x i32> zeroinitializer, i16 %mask)
1120 declare <16 x i32> @llvm.x86.avx512.mask.psrai.d(<16 x i32>, i32, <16 x i32>, i16) nounwind readnone
1122 define <8 x i64> @test_x86_avx512_psrai_q(<8 x i64> %a0) {
1123 ; CHECK-LABEL: test_x86_avx512_psrai_q
1125 %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 -1)
1129 define <8 x i64> @test_x86_avx512_mask_psrai_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
1130 ; CHECK-LABEL: test_x86_avx512_mask_psrai_q
1131 ; CHECK: vpsraq $7, %zmm0, %zmm1 {%k1}
1132 %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> %a1, i8 %mask)
1136 define <8 x i64> @test_x86_avx512_maskz_psrai_q(<8 x i64> %a0, i8 %mask) {
1137 ; CHECK-LABEL: test_x86_avx512_maskz_psrai_q
1138 ; CHECK: vpsraq $7, %zmm0, %zmm0 {%k1} {z}
1139 %res = call <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64> %a0, i32 7, <8 x i64> zeroinitializer, i8 %mask)
1143 declare <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone
1145 define <16 x i32> @test_x86_avx512_psll_d(<16 x i32> %a0, <4 x i32> %a1) {
1146 ; CHECK-LABEL: test_x86_avx512_psll_d
1148 %res = call <16 x i32> @llvm.x86.avx512.mask.psll.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 -1)
1152 define <16 x i32> @test_x86_avx512_mask_psll_d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask) {
1153 ; CHECK-LABEL: test_x86_avx512_mask_psll_d
1154 ; CHECK: vpslld %xmm1, %zmm0, %zmm2 {%k1}
1155 %res = call <16 x i32> @llvm.x86.avx512.mask.psll.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask)
1159 define <16 x i32> @test_x86_avx512_maskz_psll_d(<16 x i32> %a0, <4 x i32> %a1, i16 %mask) {
1160 ; CHECK-LABEL: test_x86_avx512_maskz_psll_d
1161 ; CHECK: vpslld %xmm1, %zmm0, %zmm0 {%k1} {z}
1162 %res = call <16 x i32> @llvm.x86.avx512.mask.psll.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 %mask)
1166 declare <16 x i32> @llvm.x86.avx512.mask.psll.d(<16 x i32>, <4 x i32>, <16 x i32>, i16) nounwind readnone
1168 define <8 x i64> @test_x86_avx512_psll_q(<8 x i64> %a0, <2 x i64> %a1) {
1169 ; CHECK-LABEL: test_x86_avx512_psll_q
1171 %res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
1175 define <8 x i64> @test_x86_avx512_mask_psll_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) {
1176 ; CHECK-LABEL: test_x86_avx512_mask_psll_q
1177 ; CHECK: vpsllq %xmm1, %zmm0, %zmm2 {%k1}
1178 %res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask)
1182 define <8 x i64> @test_x86_avx512_maskz_psll_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) {
1183 ; CHECK-LABEL: test_x86_avx512_maskz_psll_q
1184 ; CHECK: vpsllq %xmm1, %zmm0, %zmm0 {%k1} {z}
1185 %res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
1189 declare <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone
1191 define <16 x i32> @test_x86_avx512_psrl_d(<16 x i32> %a0, <4 x i32> %a1) {
1192 ; CHECK-LABEL: test_x86_avx512_psrl_d
1194 %res = call <16 x i32> @llvm.x86.avx512.mask.psrl.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 -1)
1198 define <16 x i32> @test_x86_avx512_mask_psrl_d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask) {
1199 ; CHECK-LABEL: test_x86_avx512_mask_psrl_d
1200 ; CHECK: vpsrld %xmm1, %zmm0, %zmm2 {%k1}
1201 %res = call <16 x i32> @llvm.x86.avx512.mask.psrl.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask)
1205 define <16 x i32> @test_x86_avx512_maskz_psrl_d(<16 x i32> %a0, <4 x i32> %a1, i16 %mask) {
1206 ; CHECK-LABEL: test_x86_avx512_maskz_psrl_d
1207 ; CHECK: vpsrld %xmm1, %zmm0, %zmm0 {%k1} {z}
1208 %res = call <16 x i32> @llvm.x86.avx512.mask.psrl.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 %mask)
1212 declare <16 x i32> @llvm.x86.avx512.mask.psrl.d(<16 x i32>, <4 x i32>, <16 x i32>, i16) nounwind readnone
1214 define <8 x i64> @test_x86_avx512_psrl_q(<8 x i64> %a0, <2 x i64> %a1) {
1215 ; CHECK-LABEL: test_x86_avx512_psrl_q
1217 %res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
1221 define <8 x i64> @test_x86_avx512_mask_psrl_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) {
1222 ; CHECK-LABEL: test_x86_avx512_mask_psrl_q
1223 ; CHECK: vpsrlq %xmm1, %zmm0, %zmm2 {%k1}
1224 %res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask)
1228 define <8 x i64> @test_x86_avx512_maskz_psrl_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) {
1229 ; CHECK-LABEL: test_x86_avx512_maskz_psrl_q
1230 ; CHECK: vpsrlq %xmm1, %zmm0, %zmm0 {%k1} {z}
1231 %res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
1235 declare <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone
1237 define <16 x i32> @test_x86_avx512_psra_d(<16 x i32> %a0, <4 x i32> %a1) {
1238 ; CHECK-LABEL: test_x86_avx512_psra_d
1240 %res = call <16 x i32> @llvm.x86.avx512.mask.psra.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 -1)
1244 define <16 x i32> @test_x86_avx512_mask_psra_d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask) {
1245 ; CHECK-LABEL: test_x86_avx512_mask_psra_d
1246 ; CHECK: vpsrad %xmm1, %zmm0, %zmm2 {%k1}
1247 %res = call <16 x i32> @llvm.x86.avx512.mask.psra.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask)
1251 define <16 x i32> @test_x86_avx512_maskz_psra_d(<16 x i32> %a0, <4 x i32> %a1, i16 %mask) {
1252 ; CHECK-LABEL: test_x86_avx512_maskz_psra_d
1253 ; CHECK: vpsrad %xmm1, %zmm0, %zmm0 {%k1} {z}
1254 %res = call <16 x i32> @llvm.x86.avx512.mask.psra.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 %mask)
1258 declare <16 x i32> @llvm.x86.avx512.mask.psra.d(<16 x i32>, <4 x i32>, <16 x i32>, i16) nounwind readnone
1260 define <8 x i64> @test_x86_avx512_psra_q(<8 x i64> %a0, <2 x i64> %a1) {
1261 ; CHECK-LABEL: test_x86_avx512_psra_q
1263 %res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
1267 define <8 x i64> @test_x86_avx512_mask_psra_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) {
1268 ; CHECK-LABEL: test_x86_avx512_mask_psra_q
1269 ; CHECK: vpsraq %xmm1, %zmm0, %zmm2 {%k1}
1270 %res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask)
1274 define <8 x i64> @test_x86_avx512_maskz_psra_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) {
1275 ; CHECK-LABEL: test_x86_avx512_maskz_psra_q
1276 ; CHECK: vpsraq %xmm1, %zmm0, %zmm0 {%k1} {z}
1277 %res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
1281 declare <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone
1283 define <16 x i32> @test_x86_avx512_psllv_d(<16 x i32> %a0, <16 x i32> %a1) {
1284 ; CHECK-LABEL: test_x86_avx512_psllv_d
1286 %res = call <16 x i32> @llvm.x86.avx512.mask.psllv.d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> zeroinitializer, i16 -1)
1290 define <16 x i32> @test_x86_avx512_mask_psllv_d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> %a2, i16 %mask) {
1291 ; CHECK-LABEL: test_x86_avx512_mask_psllv_d
1292 ; CHECK: vpsllvd %zmm1, %zmm0, %zmm2 {%k1}
1293 %res = call <16 x i32> @llvm.x86.avx512.mask.psllv.d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> %a2, i16 %mask)
1297 define <16 x i32> @test_x86_avx512_maskz_psllv_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
1298 ; CHECK-LABEL: test_x86_avx512_maskz_psllv_d
1299 ; CHECK: vpsllvd %zmm1, %zmm0, %zmm0 {%k1} {z}
1300 %res = call <16 x i32> @llvm.x86.avx512.mask.psllv.d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> zeroinitializer, i16 %mask)
1304 declare <16 x i32> @llvm.x86.avx512.mask.psllv.d(<16 x i32>, <16 x i32>, <16 x i32>, i16) nounwind readnone
1306 define <8 x i64> @test_x86_avx512_psllv_q(<8 x i64> %a0, <8 x i64> %a1) {
1307 ; CHECK-LABEL: test_x86_avx512_psllv_q
1309 %res = call <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
1313 define <8 x i64> @test_x86_avx512_mask_psllv_q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) {
1314 ; CHECK-LABEL: test_x86_avx512_mask_psllv_q
1315 ; CHECK: vpsllvq %zmm1, %zmm0, %zmm2 {%k1}
1316 %res = call <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask)
1320 define <8 x i64> @test_x86_avx512_maskz_psllv_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
1321 ; CHECK-LABEL: test_x86_avx512_maskz_psllv_q
1322 ; CHECK: vpsllvq %zmm1, %zmm0, %zmm0 {%k1} {z}
1323 %res = call <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
1327 declare <8 x i64> @llvm.x86.avx512.mask.psllv.q(<8 x i64>, <8 x i64>, <8 x i64>, i8) nounwind readnone
1330 define <16 x i32> @test_x86_avx512_psrav_d(<16 x i32> %a0, <16 x i32> %a1) {
1331 ; CHECK-LABEL: test_x86_avx512_psrav_d
1333 %res = call <16 x i32> @llvm.x86.avx512.mask.psrav.d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> zeroinitializer, i16 -1)
1337 define <16 x i32> @test_x86_avx512_mask_psrav_d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> %a2, i16 %mask) {
1338 ; CHECK-LABEL: test_x86_avx512_mask_psrav_d
1339 ; CHECK: vpsravd %zmm1, %zmm0, %zmm2 {%k1}
1340 %res = call <16 x i32> @llvm.x86.avx512.mask.psrav.d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> %a2, i16 %mask)
1344 define <16 x i32> @test_x86_avx512_maskz_psrav_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
1345 ; CHECK-LABEL: test_x86_avx512_maskz_psrav_d
1346 ; CHECK: vpsravd %zmm1, %zmm0, %zmm0 {%k1} {z}
1347 %res = call <16 x i32> @llvm.x86.avx512.mask.psrav.d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> zeroinitializer, i16 %mask)
1351 declare <16 x i32> @llvm.x86.avx512.mask.psrav.d(<16 x i32>, <16 x i32>, <16 x i32>, i16) nounwind readnone
1353 define <8 x i64> @test_x86_avx512_psrav_q(<8 x i64> %a0, <8 x i64> %a1) {
1354 ; CHECK-LABEL: test_x86_avx512_psrav_q
1356 %res = call <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
1360 define <8 x i64> @test_x86_avx512_mask_psrav_q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) {
1361 ; CHECK-LABEL: test_x86_avx512_mask_psrav_q
1362 ; CHECK: vpsravq %zmm1, %zmm0, %zmm2 {%k1}
1363 %res = call <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask)
1367 define <8 x i64> @test_x86_avx512_maskz_psrav_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
1368 ; CHECK-LABEL: test_x86_avx512_maskz_psrav_q
1369 ; CHECK: vpsravq %zmm1, %zmm0, %zmm0 {%k1} {z}
1370 %res = call <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
1374 declare <8 x i64> @llvm.x86.avx512.mask.psrav.q(<8 x i64>, <8 x i64>, <8 x i64>, i8) nounwind readnone
1376 define <16 x i32> @test_x86_avx512_psrlv_d(<16 x i32> %a0, <16 x i32> %a1) {
1377 ; CHECK-LABEL: test_x86_avx512_psrlv_d
1379 %res = call <16 x i32> @llvm.x86.avx512.mask.psrlv.d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> zeroinitializer, i16 -1)
1383 define <16 x i32> @test_x86_avx512_mask_psrlv_d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> %a2, i16 %mask) {
1384 ; CHECK-LABEL: test_x86_avx512_mask_psrlv_d
1385 ; CHECK: vpsrlvd %zmm1, %zmm0, %zmm2 {%k1}
1386 %res = call <16 x i32> @llvm.x86.avx512.mask.psrlv.d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> %a2, i16 %mask)
1390 define <16 x i32> @test_x86_avx512_maskz_psrlv_d(<16 x i32> %a0, <16 x i32> %a1, i16 %mask) {
1391 ; CHECK-LABEL: test_x86_avx512_maskz_psrlv_d
1392 ; CHECK: vpsrlvd %zmm1, %zmm0, %zmm0 {%k1} {z}
1393 %res = call <16 x i32> @llvm.x86.avx512.mask.psrlv.d(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> zeroinitializer, i16 %mask)
1397 declare <16 x i32> @llvm.x86.avx512.mask.psrlv.d(<16 x i32>, <16 x i32>, <16 x i32>, i16) nounwind readnone
1399 define <8 x i64> @test_x86_avx512_psrlv_q(<8 x i64> %a0, <8 x i64> %a1) {
1400 ; CHECK-LABEL: test_x86_avx512_psrlv_q
1402 %res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)
1406 define <8 x i64> @test_x86_avx512_mask_psrlv_q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask) {
1407 ; CHECK-LABEL: test_x86_avx512_mask_psrlv_q
1408 ; CHECK: vpsrlvq %zmm1, %zmm0, %zmm2 {%k1}
1409 %res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> %a2, i8 %mask)
1413 define <8 x i64> @test_x86_avx512_maskz_psrlv_q(<8 x i64> %a0, <8 x i64> %a1, i8 %mask) {
1414 ; CHECK-LABEL: test_x86_avx512_maskz_psrlv_q
1415 ; CHECK: vpsrlvq %zmm1, %zmm0, %zmm0 {%k1} {z}
1416 %res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)
1420 declare <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64>, <8 x i64>, <8 x i64>, i8) nounwind readnone
1422 define <8 x i64> @test_x86_avx512_psrlv_q_memop(<8 x i64> %a0, <8 x i64>* %ptr) {
1423 ; CHECK-LABEL: test_x86_avx512_psrlv_q_memop
1425 %b = load <8 x i64>, <8 x i64>* %ptr
1426 %res = call <8 x i64> @llvm.x86.avx512.mask.psrlv.q(<8 x i64> %a0, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
1430 declare <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
1431 declare <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
1432 declare <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
1434 define <16 x float> @test_vsubps_rn(<16 x float> %a0, <16 x float> %a1) {
1435 ; CHECK-LABEL: test_vsubps_rn
1436 ; CHECK: vsubps {rn-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x18,0x5c,0xc1]
1437 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1,
1438 <16 x float> zeroinitializer, i16 -1, i32 0)
1439 ret <16 x float> %res
1442 define <16 x float> @test_vsubps_rd(<16 x float> %a0, <16 x float> %a1) {
1443 ; CHECK-LABEL: test_vsubps_rd
1444 ; CHECK: vsubps {rd-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x38,0x5c,0xc1]
1445 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1,
1446 <16 x float> zeroinitializer, i16 -1, i32 1)
1447 ret <16 x float> %res
1450 define <16 x float> @test_vsubps_ru(<16 x float> %a0, <16 x float> %a1) {
1451 ; CHECK-LABEL: test_vsubps_ru
1452 ; CHECK: vsubps {ru-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x58,0x5c,0xc1]
1453 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1,
1454 <16 x float> zeroinitializer, i16 -1, i32 2)
1455 ret <16 x float> %res
1458 define <16 x float> @test_vsubps_rz(<16 x float> %a0, <16 x float> %a1) {
1459 ; CHECK-LABEL: test_vsubps_rz
1460 ; CHECK: vsubps {rz-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x78,0x5c,0xc1]
1461 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1,
1462 <16 x float> zeroinitializer, i16 -1, i32 3)
1463 ret <16 x float> %res
1466 define <16 x float> @test_vmulps_rn(<16 x float> %a0, <16 x float> %a1) {
1467 ; CHECK-LABEL: test_vmulps_rn
1468 ; CHECK: vmulps {rn-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x18,0x59,0xc1]
1469 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1470 <16 x float> zeroinitializer, i16 -1, i32 0)
1471 ret <16 x float> %res
1474 define <16 x float> @test_vmulps_rd(<16 x float> %a0, <16 x float> %a1) {
1475 ; CHECK-LABEL: test_vmulps_rd
1476 ; CHECK: vmulps {rd-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x38,0x59,0xc1]
1477 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1478 <16 x float> zeroinitializer, i16 -1, i32 1)
1479 ret <16 x float> %res
1482 define <16 x float> @test_vmulps_ru(<16 x float> %a0, <16 x float> %a1) {
1483 ; CHECK-LABEL: test_vmulps_ru
1484 ; CHECK: vmulps {ru-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x58,0x59,0xc1]
1485 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1486 <16 x float> zeroinitializer, i16 -1, i32 2)
1487 ret <16 x float> %res
1490 define <16 x float> @test_vmulps_rz(<16 x float> %a0, <16 x float> %a1) {
1491 ; CHECK-LABEL: test_vmulps_rz
1492 ; CHECK: vmulps {rz-sae}{{.*}} ## encoding: [0x62,0xf1,0x7c,0x78,0x59,0xc1]
1493 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1494 <16 x float> zeroinitializer, i16 -1, i32 3)
1495 ret <16 x float> %res
1499 define <16 x float> @test_vmulps_mask_rn(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
1500 ; CHECK-LABEL: test_vmulps_mask_rn
1501 ; CHECK: vmulps {rn-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0x7c,0x99,0x59,0xc1]
1502 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1503 <16 x float> zeroinitializer, i16 %mask, i32 0)
1504 ret <16 x float> %res
1507 define <16 x float> @test_vmulps_mask_rd(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
1508 ; CHECK-LABEL: test_vmulps_mask_rd
1509 ; CHECK: vmulps {rd-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xb9,0x59,0xc1]
1510 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1511 <16 x float> zeroinitializer, i16 %mask, i32 1)
1512 ret <16 x float> %res
1515 define <16 x float> @test_vmulps_mask_ru(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
1516 ; CHECK-LABEL: test_vmulps_mask_ru
1517 ; CHECK: vmulps {ru-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xd9,0x59,0xc1]
1518 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1519 <16 x float> zeroinitializer, i16 %mask, i32 2)
1520 ret <16 x float> %res
1523 define <16 x float> @test_vmulps_mask_rz(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
1524 ; CHECK-LABEL: test_vmulps_mask_rz
1525 ; CHECK: vmulps {rz-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xf9,0x59,0xc1]
1526 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1527 <16 x float> zeroinitializer, i16 %mask, i32 3)
1528 ret <16 x float> %res
1531 ;; With Passthru value
1532 define <16 x float> @test_vmulps_mask_passthru_rn(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) {
1533 ; CHECK-LABEL: test_vmulps_mask_passthru_rn
1534 ; CHECK: vmulps {rn-sae}{{.*}}{%k1} ## encoding: [0x62,0xf1,0x7c,0x19,0x59,0xd1]
1535 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1536 <16 x float> %passthru, i16 %mask, i32 0)
1537 ret <16 x float> %res
1540 define <16 x float> @test_vmulps_mask_passthru_rd(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) {
1541 ; CHECK-LABEL: test_vmulps_mask_passthru_rd
1542 ; CHECK: vmulps {rd-sae}{{.*}}{%k1} ## encoding: [0x62,0xf1,0x7c,0x39,0x59,0xd1]
1543 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1544 <16 x float> %passthru, i16 %mask, i32 1)
1545 ret <16 x float> %res
1548 define <16 x float> @test_vmulps_mask_passthru_ru(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) {
1549 ; CHECK-LABEL: test_vmulps_mask_passthru_ru
1550 ; CHECK: vmulps {ru-sae}{{.*}}{%k1} ## encoding: [0x62,0xf1,0x7c,0x59,0x59,0xd1]
1551 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1552 <16 x float> %passthru, i16 %mask, i32 2)
1553 ret <16 x float> %res
1556 define <16 x float> @test_vmulps_mask_passthru_rz(<16 x float> %a0, <16 x float> %a1, <16 x float> %passthru, i16 %mask) {
1557 ; CHECK-LABEL: test_vmulps_mask_passthru_rz
1558 ; CHECK: vmulps {rz-sae}{{.*}}{%k1} ## encoding: [0x62,0xf1,0x7c,0x79,0x59,0xd1]
1559 %res = call <16 x float> @llvm.x86.avx512.mask.mul.ps.512(<16 x float> %a0, <16 x float> %a1,
1560 <16 x float> %passthru, i16 %mask, i32 3)
1561 ret <16 x float> %res
1565 define <8 x double> @test_vmulpd_mask_rn(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
1566 ; CHECK-LABEL: test_vmulpd_mask_rn
1567 ; CHECK: vmulpd {rn-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x99,0x59,0xc1]
1568 %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
1569 <8 x double> zeroinitializer, i8 %mask, i32 0)
1570 ret <8 x double> %res
1573 define <8 x double> @test_vmulpd_mask_rd(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
1574 ; CHECK-LABEL: test_vmulpd_mask_rd
1575 ; CHECK: vmulpd {rd-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xb9,0x59,0xc1]
1576 %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
1577 <8 x double> zeroinitializer, i8 %mask, i32 1)
1578 ret <8 x double> %res
1581 define <8 x double> @test_vmulpd_mask_ru(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
1582 ; CHECK-LABEL: test_vmulpd_mask_ru
1583 ; CHECK: vmulpd {ru-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xd9,0x59,0xc1]
1584 %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
1585 <8 x double> zeroinitializer, i8 %mask, i32 2)
1586 ret <8 x double> %res
1589 define <8 x double> @test_vmulpd_mask_rz(<8 x double> %a0, <8 x double> %a1, i8 %mask) {
1590 ; CHECK-LABEL: test_vmulpd_mask_rz
1591 ; CHECK: vmulpd {rz-sae}{{.*}}{%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xf9,0x59,0xc1]
1592 %res = call <8 x double> @llvm.x86.avx512.mask.mul.pd.512(<8 x double> %a0, <8 x double> %a1,
1593 <8 x double> zeroinitializer, i8 %mask, i32 3)
1594 ret <8 x double> %res
1597 define <16 x i32> @test_xor_epi32(<16 x i32> %a, <16 x i32> %b) {
1598 ;CHECK-LABEL: test_xor_epi32
1599 ;CHECK: vpxord {{.*}}encoding: [0x62,0xf1,0x7d,0x48,0xef,0xc1]
1600 %res = call <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
1601 ret < 16 x i32> %res
1604 define <16 x i32> @test_mask_xor_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
1605 ;CHECK-LABEL: test_mask_xor_epi32
1606 ;CHECK: vpxord %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xef,0xd1]
1607 %res = call <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1608 ret < 16 x i32> %res
1611 declare <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
1613 define <16 x i32> @test_or_epi32(<16 x i32> %a, <16 x i32> %b) {
1614 ;CHECK-LABEL: test_or_epi32
1615 ;CHECK: vpord {{.*}}encoding: [0x62,0xf1,0x7d,0x48,0xeb,0xc1]
1616 %res = call <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
1617 ret < 16 x i32> %res
1620 define <16 x i32> @test_mask_or_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
1621 ;CHECK-LABEL: test_mask_or_epi32
1622 ;CHECK: vpord %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xeb,0xd1]
1623 %res = call <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1624 ret < 16 x i32> %res
1627 declare <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
1629 define <16 x i32> @test_and_epi32(<16 x i32> %a, <16 x i32> %b) {
1630 ;CHECK-LABEL: test_and_epi32
1631 ;CHECK: vpandd {{.*}}encoding: [0x62,0xf1,0x7d,0x48,0xdb,0xc1]
1632 %res = call <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
1633 ret < 16 x i32> %res
1636 define <16 x i32> @test_mask_and_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
1637 ;CHECK-LABEL: test_mask_and_epi32
1638 ;CHECK: vpandd %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xdb,0xd1]
1639 %res = call <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1640 ret < 16 x i32> %res
1643 declare <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
1645 define <8 x i64> @test_xor_epi64(<8 x i64> %a, <8 x i64> %b) {
1646 ;CHECK-LABEL: test_xor_epi64
1647 ;CHECK: vpxorq {{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xef,0xc1]
1648 %res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
1652 define <8 x i64> @test_mask_xor_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
1653 ;CHECK-LABEL: test_mask_xor_epi64
1654 ;CHECK: vpxorq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xef,0xd1]
1655 %res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1659 declare <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
1661 define <8 x i64> @test_or_epi64(<8 x i64> %a, <8 x i64> %b) {
1662 ;CHECK-LABEL: test_or_epi64
1663 ;CHECK: vporq {{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xeb,0xc1]
1664 %res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
1668 define <8 x i64> @test_mask_or_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
1669 ;CHECK-LABEL: test_mask_or_epi64
1670 ;CHECK: vporq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xeb,0xd1]
1671 %res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1675 declare <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
1677 define <8 x i64> @test_and_epi64(<8 x i64> %a, <8 x i64> %b) {
1678 ;CHECK-LABEL: test_and_epi64
1679 ;CHECK: vpandq {{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xdb,0xc1]
1680 %res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
1684 define <8 x i64> @test_mask_and_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
1685 ;CHECK-LABEL: test_mask_and_epi64
1686 ;CHECK: vpandq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xdb,0xd1]
1687 %res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1691 declare <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
1694 define <16 x i32> @test_mask_add_epi32_rr(<16 x i32> %a, <16 x i32> %b) {
1695 ;CHECK-LABEL: test_mask_add_epi32_rr
1696 ;CHECK: vpaddd %zmm1, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0x7d,0x48,0xfe,0xc1]
1697 %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
1698 ret < 16 x i32> %res
1701 define <16 x i32> @test_mask_add_epi32_rrk(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
1702 ;CHECK-LABEL: test_mask_add_epi32_rrk
1703 ;CHECK: vpaddd %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xfe,0xd1]
1704 %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1705 ret < 16 x i32> %res
1708 define <16 x i32> @test_mask_add_epi32_rrkz(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
1709 ;CHECK-LABEL: test_mask_add_epi32_rrkz
1710 ;CHECK: vpaddd %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xfe,0xc1]
1711 %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
1712 ret < 16 x i32> %res
1715 define <16 x i32> @test_mask_add_epi32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
1716 ;CHECK-LABEL: test_mask_add_epi32_rm
1717 ;CHECK: vpaddd (%rdi), %zmm0, %zmm0 ## encoding: [0x62,0xf1,0x7d,0x48,0xfe,0x07]
1718 %b = load <16 x i32>, <16 x i32>* %ptr_b
1719 %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
1720 ret < 16 x i32> %res
1723 define <16 x i32> @test_mask_add_epi32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <16 x i32> %passThru, i16 %mask) {
1724 ;CHECK-LABEL: test_mask_add_epi32_rmk
1725 ;CHECK: vpaddd (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xfe,0x0f]
1726 %b = load <16 x i32>, <16 x i32>* %ptr_b
1727 %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1728 ret < 16 x i32> %res
1731 define <16 x i32> @test_mask_add_epi32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i16 %mask) {
1732 ;CHECK-LABEL: test_mask_add_epi32_rmkz
1733 ;CHECK: vpaddd (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xfe,0x07]
1734 %b = load <16 x i32>, <16 x i32>* %ptr_b
1735 %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
1736 ret < 16 x i32> %res
1739 define <16 x i32> @test_mask_add_epi32_rmb(<16 x i32> %a, i32* %ptr_b) {
1740 ;CHECK-LABEL: test_mask_add_epi32_rmb
1741 ;CHECK: vpaddd (%rdi){1to16}, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0x7d,0x58,0xfe,0x07]
1742 %q = load i32, i32* %ptr_b
1743 %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
1744 %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
1745 %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
1746 ret < 16 x i32> %res
1749 define <16 x i32> @test_mask_add_epi32_rmbk(<16 x i32> %a, i32* %ptr_b, <16 x i32> %passThru, i16 %mask) {
1750 ;CHECK-LABEL: test_mask_add_epi32_rmbk
1751 ;CHECK: vpaddd (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x59,0xfe,0x0f]
1752 %q = load i32, i32* %ptr_b
1753 %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
1754 %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
1755 %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1756 ret < 16 x i32> %res
1759 define <16 x i32> @test_mask_add_epi32_rmbkz(<16 x i32> %a, i32* %ptr_b, i16 %mask) {
1760 ;CHECK-LABEL: test_mask_add_epi32_rmbkz
1761 ;CHECK: vpaddd (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xd9,0xfe,0x07]
1762 %q = load i32, i32* %ptr_b
1763 %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
1764 %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
1765 %res = call <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
1766 ret < 16 x i32> %res
1769 declare <16 x i32> @llvm.x86.avx512.mask.padd.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
1771 define <16 x i32> @test_mask_sub_epi32_rr(<16 x i32> %a, <16 x i32> %b) {
1772 ;CHECK-LABEL: test_mask_sub_epi32_rr
1773 ;CHECK: vpsubd %zmm1, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0x7d,0x48,0xfa,0xc1]
1774 %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
1775 ret < 16 x i32> %res
1778 define <16 x i32> @test_mask_sub_epi32_rrk(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
1779 ;CHECK-LABEL: test_mask_sub_epi32_rrk
1780 ;CHECK: vpsubd %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xfa,0xd1]
1781 %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1782 ret < 16 x i32> %res
1785 define <16 x i32> @test_mask_sub_epi32_rrkz(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
1786 ;CHECK-LABEL: test_mask_sub_epi32_rrkz
1787 ;CHECK: vpsubd %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xfa,0xc1]
1788 %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
1789 ret < 16 x i32> %res
1792 define <16 x i32> @test_mask_sub_epi32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
1793 ;CHECK-LABEL: test_mask_sub_epi32_rm
1794 ;CHECK: vpsubd (%rdi), %zmm0, %zmm0 ## encoding: [0x62,0xf1,0x7d,0x48,0xfa,0x07]
1795 %b = load <16 x i32>, <16 x i32>* %ptr_b
1796 %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
1797 ret < 16 x i32> %res
1800 define <16 x i32> @test_mask_sub_epi32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <16 x i32> %passThru, i16 %mask) {
1801 ;CHECK-LABEL: test_mask_sub_epi32_rmk
1802 ;CHECK: vpsubd (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0xfa,0x0f]
1803 %b = load <16 x i32>, <16 x i32>* %ptr_b
1804 %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1805 ret < 16 x i32> %res
1808 define <16 x i32> @test_mask_sub_epi32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i16 %mask) {
1809 ;CHECK-LABEL: test_mask_sub_epi32_rmkz
1810 ;CHECK: vpsubd (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0xfa,0x07]
1811 %b = load <16 x i32>, <16 x i32>* %ptr_b
1812 %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
1813 ret < 16 x i32> %res
1816 define <16 x i32> @test_mask_sub_epi32_rmb(<16 x i32> %a, i32* %ptr_b) {
1817 ;CHECK-LABEL: test_mask_sub_epi32_rmb
1818 ;CHECK: vpsubd (%rdi){1to16}, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0x7d,0x58,0xfa,0x07]
1819 %q = load i32, i32* %ptr_b
1820 %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
1821 %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
1822 %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
1823 ret < 16 x i32> %res
1826 define <16 x i32> @test_mask_sub_epi32_rmbk(<16 x i32> %a, i32* %ptr_b, <16 x i32> %passThru, i16 %mask) {
1827 ;CHECK-LABEL: test_mask_sub_epi32_rmbk
1828 ;CHECK: vpsubd (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x59,0xfa,0x0f]
1829 %q = load i32, i32* %ptr_b
1830 %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
1831 %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
1832 %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1833 ret < 16 x i32> %res
1836 define <16 x i32> @test_mask_sub_epi32_rmbkz(<16 x i32> %a, i32* %ptr_b, i16 %mask) {
1837 ;CHECK-LABEL: test_mask_sub_epi32_rmbkz
1838 ;CHECK: vpsubd (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xd9,0xfa,0x07]
1839 %q = load i32, i32* %ptr_b
1840 %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
1841 %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
1842 %res = call <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
1843 ret < 16 x i32> %res
1846 declare <16 x i32> @llvm.x86.avx512.mask.psub.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
1848 define <8 x i64> @test_mask_add_epi64_rr(<8 x i64> %a, <8 x i64> %b) {
1849 ;CHECK-LABEL: test_mask_add_epi64_rr
1850 ;CHECK: vpaddq %zmm1, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0xfd,0x48,0xd4,0xc1]
1851 %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
1855 define <8 x i64> @test_mask_add_epi64_rrk(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
1856 ;CHECK-LABEL: test_mask_add_epi64_rrk
1857 ;CHECK: vpaddq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xd4,0xd1]
1858 %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1862 define <8 x i64> @test_mask_add_epi64_rrkz(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
1863 ;CHECK-LABEL: test_mask_add_epi64_rrkz
1864 ;CHECK: vpaddq %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xd4,0xc1]
1865 %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
1869 define <8 x i64> @test_mask_add_epi64_rm(<8 x i64> %a, <8 x i64>* %ptr_b) {
1870 ;CHECK-LABEL: test_mask_add_epi64_rm
1871 ;CHECK: vpaddq (%rdi), %zmm0, %zmm0 ## encoding: [0x62,0xf1,0xfd,0x48,0xd4,0x07]
1872 %b = load <8 x i64>, <8 x i64>* %ptr_b
1873 %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
1877 define <8 x i64> @test_mask_add_epi64_rmk(<8 x i64> %a, <8 x i64>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
1878 ;CHECK-LABEL: test_mask_add_epi64_rmk
1879 ;CHECK: vpaddq (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xd4,0x0f]
1880 %b = load <8 x i64>, <8 x i64>* %ptr_b
1881 %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1885 define <8 x i64> @test_mask_add_epi64_rmkz(<8 x i64> %a, <8 x i64>* %ptr_b, i8 %mask) {
1886 ;CHECK-LABEL: test_mask_add_epi64_rmkz
1887 ;CHECK: vpaddq (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xd4,0x07]
1888 %b = load <8 x i64>, <8 x i64>* %ptr_b
1889 %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
1893 define <8 x i64> @test_mask_add_epi64_rmb(<8 x i64> %a, i64* %ptr_b) {
1894 ;CHECK-LABEL: test_mask_add_epi64_rmb
1895 ;CHECK: vpaddq (%rdi){1to8}, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0xfd,0x58,0xd4,0x07]
1896 %q = load i64, i64* %ptr_b
1897 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
1898 %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
1899 %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
1903 define <8 x i64> @test_mask_add_epi64_rmbk(<8 x i64> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
1904 ;CHECK-LABEL: test_mask_add_epi64_rmbk
1905 ;CHECK: vpaddq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x59,0xd4,0x0f]
1906 %q = load i64, i64* %ptr_b
1907 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
1908 %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
1909 %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1913 define <8 x i64> @test_mask_add_epi64_rmbkz(<8 x i64> %a, i64* %ptr_b, i8 %mask) {
1914 ;CHECK-LABEL: test_mask_add_epi64_rmbkz
1915 ;CHECK: vpaddq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xd9,0xd4,0x07]
1916 %q = load i64, i64* %ptr_b
1917 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
1918 %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
1919 %res = call <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
1923 declare <8 x i64> @llvm.x86.avx512.mask.padd.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
1925 define <8 x i64> @test_mask_sub_epi64_rr(<8 x i64> %a, <8 x i64> %b) {
1926 ;CHECK-LABEL: test_mask_sub_epi64_rr
1927 ;CHECK: vpsubq %zmm1, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0xfd,0x48,0xfb,0xc1]
1928 %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
1932 define <8 x i64> @test_mask_sub_epi64_rrk(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
1933 ;CHECK-LABEL: test_mask_sub_epi64_rrk
1934 ;CHECK: vpsubq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xfb,0xd1]
1935 %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1939 define <8 x i64> @test_mask_sub_epi64_rrkz(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
1940 ;CHECK-LABEL: test_mask_sub_epi64_rrkz
1941 ;CHECK: vpsubq %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xfb,0xc1]
1942 %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
1946 define <8 x i64> @test_mask_sub_epi64_rm(<8 x i64> %a, <8 x i64>* %ptr_b) {
1947 ;CHECK-LABEL: test_mask_sub_epi64_rm
1948 ;CHECK: vpsubq (%rdi), %zmm0, %zmm0 ## encoding: [0x62,0xf1,0xfd,0x48,0xfb,0x07]
1949 %b = load <8 x i64>, <8 x i64>* %ptr_b
1950 %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
1954 define <8 x i64> @test_mask_sub_epi64_rmk(<8 x i64> %a, <8 x i64>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
1955 ;CHECK-LABEL: test_mask_sub_epi64_rmk
1956 ;CHECK: vpsubq (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xfb,0x0f]
1957 %b = load <8 x i64>, <8 x i64>* %ptr_b
1958 %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1962 define <8 x i64> @test_mask_sub_epi64_rmkz(<8 x i64> %a, <8 x i64>* %ptr_b, i8 %mask) {
1963 ;CHECK-LABEL: test_mask_sub_epi64_rmkz
1964 ;CHECK: vpsubq (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xfb,0x07]
1965 %b = load <8 x i64>, <8 x i64>* %ptr_b
1966 %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
1970 define <8 x i64> @test_mask_sub_epi64_rmb(<8 x i64> %a, i64* %ptr_b) {
1971 ;CHECK-LABEL: test_mask_sub_epi64_rmb
1972 ;CHECK: vpsubq (%rdi){1to8}, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0xfd,0x58,0xfb,0x07]
1973 %q = load i64, i64* %ptr_b
1974 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
1975 %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
1976 %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 -1)
1980 define <8 x i64> @test_mask_sub_epi64_rmbk(<8 x i64> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
1981 ;CHECK-LABEL: test_mask_sub_epi64_rmbk
1982 ;CHECK: vpsubq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x59,0xfb,0x0f]
1983 %q = load i64, i64* %ptr_b
1984 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
1985 %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
1986 %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1990 define <8 x i64> @test_mask_sub_epi64_rmbkz(<8 x i64> %a, i64* %ptr_b, i8 %mask) {
1991 ;CHECK-LABEL: test_mask_sub_epi64_rmbkz
1992 ;CHECK: vpsubq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xd9,0xfb,0x07]
1993 %q = load i64, i64* %ptr_b
1994 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
1995 %b = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
1996 %res = call <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> zeroinitializer, i8 %mask)
2000 declare <8 x i64> @llvm.x86.avx512.mask.psub.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
2002 define <8 x i64> @test_mask_mul_epi32_rr(<16 x i32> %a, <16 x i32> %b) {
2003 ;CHECK-LABEL: test_mask_mul_epi32_rr
2004 ;CHECK: vpmuldq %zmm1, %zmm0, %zmm0 ## encoding: [0x62,0xf2,0xfd,0x48,0x28,0xc1]
2005 %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
2009 define <8 x i64> @test_mask_mul_epi32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) {
2010 ;CHECK-LABEL: test_mask_mul_epi32_rrk
2011 ;CHECK: vpmuldq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x49,0x28,0xd1]
2012 %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
2016 define <8 x i64> @test_mask_mul_epi32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) {
2017 ;CHECK-LABEL: test_mask_mul_epi32_rrkz
2018 ;CHECK: vpmuldq %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xc9,0x28,0xc1]
2019 %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
2023 define <8 x i64> @test_mask_mul_epi32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
2024 ;CHECK-LABEL: test_mask_mul_epi32_rm
2025 ;CHECK: vpmuldq (%rdi), %zmm0, %zmm0 ## encoding: [0x62,0xf2,0xfd,0x48,0x28,0x07]
2026 %b = load <16 x i32>, <16 x i32>* %ptr_b
2027 %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
2031 define <8 x i64> @test_mask_mul_epi32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
2032 ;CHECK-LABEL: test_mask_mul_epi32_rmk
2033 ;CHECK: vpmuldq (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x49,0x28,0x0f]
2034 %b = load <16 x i32>, <16 x i32>* %ptr_b
2035 %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
2039 define <8 x i64> @test_mask_mul_epi32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) {
2040 ;CHECK-LABEL: test_mask_mul_epi32_rmkz
2041 ;CHECK: vpmuldq (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xc9,0x28,0x07]
2042 %b = load <16 x i32>, <16 x i32>* %ptr_b
2043 %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
2047 define <8 x i64> @test_mask_mul_epi32_rmb(<16 x i32> %a, i64* %ptr_b) {
2048 ;CHECK-LABEL: test_mask_mul_epi32_rmb
2049 ;CHECK: vpmuldq (%rdi){1to8}, %zmm0, %zmm0 ## encoding: [0x62,0xf2,0xfd,0x58,0x28,0x07]
2050 %q = load i64, i64* %ptr_b
2051 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
2052 %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
2053 %b = bitcast <8 x i64> %b64 to <16 x i32>
2054 %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
2058 define <8 x i64> @test_mask_mul_epi32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
2059 ;CHECK-LABEL: test_mask_mul_epi32_rmbk
2060 ;CHECK: vpmuldq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x59,0x28,0x0f]
2061 %q = load i64, i64* %ptr_b
2062 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
2063 %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
2064 %b = bitcast <8 x i64> %b64 to <16 x i32>
2065 %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
2069 define <8 x i64> @test_mask_mul_epi32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) {
2070 ;CHECK-LABEL: test_mask_mul_epi32_rmbkz
2071 ;CHECK: vpmuldq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xd9,0x28,0x07]
2072 %q = load i64, i64* %ptr_b
2073 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
2074 %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
2075 %b = bitcast <8 x i64> %b64 to <16 x i32>
2076 %res = call <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
2080 declare <8 x i64> @llvm.x86.avx512.mask.pmul.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8)
2082 define <8 x i64> @test_mask_mul_epu32_rr(<16 x i32> %a, <16 x i32> %b) {
2083 ;CHECK-LABEL: test_mask_mul_epu32_rr
2084 ;CHECK: vpmuludq %zmm1, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0xfd,0x48,0xf4,0xc1]
2085 %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
2089 define <8 x i64> @test_mask_mul_epu32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) {
2090 ;CHECK-LABEL: test_mask_mul_epu32_rrk
2091 ;CHECK: vpmuludq %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xf4,0xd1]
2092 %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
2096 define <8 x i64> @test_mask_mul_epu32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) {
2097 ;CHECK-LABEL: test_mask_mul_epu32_rrkz
2098 ;CHECK: vpmuludq %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xf4,0xc1]
2099 %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
2103 define <8 x i64> @test_mask_mul_epu32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
2104 ;CHECK-LABEL: test_mask_mul_epu32_rm
2105 ;CHECK: vpmuludq (%rdi), %zmm0, %zmm0 ## encoding: [0x62,0xf1,0xfd,0x48,0xf4,0x07]
2106 %b = load <16 x i32>, <16 x i32>* %ptr_b
2107 %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
2111 define <8 x i64> @test_mask_mul_epu32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
2112 ;CHECK-LABEL: test_mask_mul_epu32_rmk
2113 ;CHECK: vpmuludq (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0xf4,0x0f]
2114 %b = load <16 x i32>, <16 x i32>* %ptr_b
2115 %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
2119 define <8 x i64> @test_mask_mul_epu32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) {
2120 ;CHECK-LABEL: test_mask_mul_epu32_rmkz
2121 ;CHECK: vpmuludq (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0xf4,0x07]
2122 %b = load <16 x i32>, <16 x i32>* %ptr_b
2123 %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
2127 define <8 x i64> @test_mask_mul_epu32_rmb(<16 x i32> %a, i64* %ptr_b) {
2128 ;CHECK-LABEL: test_mask_mul_epu32_rmb
2129 ;CHECK: vpmuludq (%rdi){1to8}, %zmm0, %zmm0 ## encoding: [0x62,0xf1,0xfd,0x58,0xf4,0x07]
2130 %q = load i64, i64* %ptr_b
2131 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
2132 %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
2133 %b = bitcast <8 x i64> %b64 to <16 x i32>
2134 %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 -1)
2138 define <8 x i64> @test_mask_mul_epu32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
2139 ;CHECK-LABEL: test_mask_mul_epu32_rmbk
2140 ;CHECK: vpmuludq (%rdi){1to8}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x59,0xf4,0x0f]
2141 %q = load i64, i64* %ptr_b
2142 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
2143 %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
2144 %b = bitcast <8 x i64> %b64 to <16 x i32>
2145 %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask)
2149 define <8 x i64> @test_mask_mul_epu32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) {
2150 ;CHECK-LABEL: test_mask_mul_epu32_rmbkz
2151 ;CHECK: vpmuludq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xd9,0xf4,0x07]
2152 %q = load i64, i64* %ptr_b
2153 %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
2154 %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
2155 %b = bitcast <8 x i64> %b64 to <16 x i32>
2156 %res = call <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b, <8 x i64> zeroinitializer, i8 %mask)
2160 declare <8 x i64> @llvm.x86.avx512.mask.pmulu.dq.512(<16 x i32>, <16 x i32>, <8 x i64>, i8)
2162 define <16 x i32> @test_mask_mullo_epi32_rr_512(<16 x i32> %a, <16 x i32> %b) {
2163 ;CHECK-LABEL: test_mask_mullo_epi32_rr_512
2164 ;CHECK: vpmulld %zmm1, %zmm0, %zmm0 ## encoding: [0x62,0xf2,0x7d,0x48,0x40,0xc1]
2165 %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
2169 define <16 x i32> @test_mask_mullo_epi32_rrk_512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
2170 ;CHECK-LABEL: test_mask_mullo_epi32_rrk_512
2171 ;CHECK: vpmulld %zmm1, %zmm0, %zmm2 {%k1} ## encoding: [0x62,0xf2,0x7d,0x49,0x40,0xd1]
2172 %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
2173 ret < 16 x i32> %res
2176 define <16 x i32> @test_mask_mullo_epi32_rrkz_512(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
2177 ;CHECK-LABEL: test_mask_mullo_epi32_rrkz_512
2178 ;CHECK: vpmulld %zmm1, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xc9,0x40,0xc1]
2179 %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
2180 ret < 16 x i32> %res
2183 define <16 x i32> @test_mask_mullo_epi32_rm_512(<16 x i32> %a, <16 x i32>* %ptr_b) {
2184 ;CHECK-LABEL: test_mask_mullo_epi32_rm_512
2185 ;CHECK: vpmulld (%rdi), %zmm0, %zmm0 ## encoding: [0x62,0xf2,0x7d,0x48,0x40,0x07]
2186 %b = load <16 x i32>, <16 x i32>* %ptr_b
2187 %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
2188 ret < 16 x i32> %res
2191 define <16 x i32> @test_mask_mullo_epi32_rmk_512(<16 x i32> %a, <16 x i32>* %ptr_b, <16 x i32> %passThru, i16 %mask) {
2192 ;CHECK-LABEL: test_mask_mullo_epi32_rmk_512
2193 ;CHECK: vpmulld (%rdi), %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf2,0x7d,0x49,0x40,0x0f]
2194 %b = load <16 x i32>, <16 x i32>* %ptr_b
2195 %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
2196 ret < 16 x i32> %res
2199 define <16 x i32> @test_mask_mullo_epi32_rmkz_512(<16 x i32> %a, <16 x i32>* %ptr_b, i16 %mask) {
2200 ;CHECK-LABEL: test_mask_mullo_epi32_rmkz_512
2201 ;CHECK: vpmulld (%rdi), %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xc9,0x40,0x07]
2202 %b = load <16 x i32>, <16 x i32>* %ptr_b
2203 %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
2204 ret < 16 x i32> %res
2207 define <16 x i32> @test_mask_mullo_epi32_rmb_512(<16 x i32> %a, i32* %ptr_b) {
2208 ;CHECK-LABEL: test_mask_mullo_epi32_rmb_512
2209 ;CHECK: vpmulld (%rdi){1to16}, %zmm0, %zmm0 ## encoding: [0x62,0xf2,0x7d,0x58,0x40,0x07]
2210 %q = load i32, i32* %ptr_b
2211 %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
2212 %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
2213 %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 -1)
2214 ret < 16 x i32> %res
2217 define <16 x i32> @test_mask_mullo_epi32_rmbk_512(<16 x i32> %a, i32* %ptr_b, <16 x i32> %passThru, i16 %mask) {
2218 ;CHECK-LABEL: test_mask_mullo_epi32_rmbk_512
2219 ;CHECK: vpmulld (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf2,0x7d,0x59,0x40,0x0f]
2220 %q = load i32, i32* %ptr_b
2221 %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
2222 %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
2223 %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
2224 ret < 16 x i32> %res
2227 define <16 x i32> @test_mask_mullo_epi32_rmbkz_512(<16 x i32> %a, i32* %ptr_b, i16 %mask) {
2228 ;CHECK-LABEL: test_mask_mullo_epi32_rmbkz_512
2229 ;CHECK: vpmulld (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xd9,0x40,0x07]
2230 %q = load i32, i32* %ptr_b
2231 %vecinit.i = insertelement <16 x i32> undef, i32 %q, i32 0
2232 %b = shufflevector <16 x i32> %vecinit.i, <16 x i32> undef, <16 x i32> zeroinitializer
2233 %res = call <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> zeroinitializer, i16 %mask)
2234 ret < 16 x i32> %res
2237 declare <16 x i32> @llvm.x86.avx512.mask.pmull.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
2239 define <16 x float> @test_mm512_maskz_add_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2240 ;CHECK-LABEL: test_mm512_maskz_add_round_ps_rn_sae
2241 ;CHECK: vaddps {rn-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
2242 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 0)
2243 ret <16 x float> %res
2245 define <16 x float> @test_mm512_maskz_add_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2246 ;CHECK-LABEL: test_mm512_maskz_add_round_ps_rd_sae
2247 ;CHECK: vaddps {rd-sae}, %zmm1, %zmm0, %zmm0
2248 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 1)
2249 ret <16 x float> %res
2251 define <16 x float> @test_mm512_maskz_add_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2252 ;CHECK-LABEL: test_mm512_maskz_add_round_ps_ru_sae
2253 ;CHECK: vaddps {ru-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
2254 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 2)
2255 ret <16 x float> %res
2258 define <16 x float> @test_mm512_maskz_add_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2259 ;CHECK-LABEL: test_mm512_maskz_add_round_ps_rz_sae
2260 ;CHECK: vaddps {rz-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
2261 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 3)
2262 ret <16 x float> %res
2266 define <16 x float> @test_mm512_maskz_add_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2267 ;CHECK-LABEL: test_mm512_maskz_add_round_ps_current
2268 ;CHECK: vaddps %zmm1, %zmm0, %zmm0 {%k1} {z}
2269 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 4)
2270 ret <16 x float> %res
2273 define <16 x float> @test_mm512_mask_add_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2274 ;CHECK-LABEL: test_mm512_mask_add_round_ps_rn_sae
2275 ;CHECK: vaddps {rn-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2276 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 0)
2277 ret <16 x float> %res
2279 define <16 x float> @test_mm512_mask_add_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2280 ;CHECK-LABEL: test_mm512_mask_add_round_ps_rd_sae
2281 ;CHECK: vaddps {rd-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2282 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 1)
2283 ret <16 x float> %res
2285 define <16 x float> @test_mm512_mask_add_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2286 ;CHECK-LABEL: test_mm512_mask_add_round_ps_ru_sae
2287 ;CHECK: vaddps {ru-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2288 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 2)
2289 ret <16 x float> %res
2292 define <16 x float> @test_mm512_mask_add_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2293 ;CHECK-LABEL: test_mm512_mask_add_round_ps_rz_sae
2294 ;CHECK: vaddps {rz-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2295 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 3)
2296 ret <16 x float> %res
2300 define <16 x float> @test_mm512_mask_add_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2301 ;CHECK-LABEL: test_mm512_mask_add_round_ps_current
2302 ;CHECK: vaddps %zmm1, %zmm0, %zmm2 {%k1}
2303 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 4)
2304 ret <16 x float> %res
2308 define <16 x float> @test_mm512_add_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2309 ;CHECK-LABEL: test_mm512_add_round_ps_rn_sae
2310 ;CHECK: vaddps {rn-sae}, %zmm1, %zmm0, %zmm0
2311 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 0)
2312 ret <16 x float> %res
2314 define <16 x float> @test_mm512_add_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2315 ;CHECK-LABEL: test_mm512_add_round_ps_rd_sae
2316 ;CHECK: vaddps {rd-sae}, %zmm1, %zmm0, %zmm0
2317 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 1)
2318 ret <16 x float> %res
2320 define <16 x float> @test_mm512_add_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2321 ;CHECK-LABEL: test_mm512_add_round_ps_ru_sae
2322 ;CHECK: vaddps {ru-sae}, %zmm1, %zmm0, %zmm0
2323 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 2)
2324 ret <16 x float> %res
2327 define <16 x float> @test_mm512_add_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2328 ;CHECK-LABEL: test_mm512_add_round_ps_rz_sae
2329 ;CHECK: vaddps {rz-sae}, %zmm1, %zmm0, %zmm0
2330 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 3)
2331 ret <16 x float> %res
2334 define <16 x float> @test_mm512_add_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2335 ;CHECK-LABEL: test_mm512_add_round_ps_current
2336 ;CHECK: vaddps %zmm1, %zmm0, %zmm0
2337 %res = call <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 4)
2338 ret <16 x float> %res
2340 declare <16 x float> @llvm.x86.avx512.mask.add.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
2342 define <16 x float> @test_mm512_mask_sub_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2343 ;CHECK-LABEL: test_mm512_mask_sub_round_ps_rn_sae
2344 ;CHECK: vsubps {rn-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2345 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 0)
2346 ret <16 x float> %res
2348 define <16 x float> @test_mm512_mask_sub_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2349 ;CHECK-LABEL: test_mm512_mask_sub_round_ps_rd_sae
2350 ;CHECK: vsubps {rd-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2351 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 1)
2352 ret <16 x float> %res
2354 define <16 x float> @test_mm512_mask_sub_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2355 ;CHECK-LABEL: test_mm512_mask_sub_round_ps_ru_sae
2356 ;CHECK: vsubps {ru-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2357 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 2)
2358 ret <16 x float> %res
2361 define <16 x float> @test_mm512_mask_sub_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2362 ;CHECK-LABEL: test_mm512_mask_sub_round_ps_rz_sae
2363 ;CHECK: vsubps {rz-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2364 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 3)
2365 ret <16 x float> %res
2369 define <16 x float> @test_mm512_mask_sub_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2370 ;CHECK-LABEL: test_mm512_mask_sub_round_ps_current
2371 ;CHECK: vsubps %zmm1, %zmm0, %zmm2 {%k1}
2372 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 4)
2373 ret <16 x float> %res
2376 define <16 x float> @test_mm512_sub_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2377 ;CHECK-LABEL: test_mm512_sub_round_ps_rn_sae
2378 ;CHECK: vsubps {rn-sae}, %zmm1, %zmm0, %zmm0
2379 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 0)
2380 ret <16 x float> %res
2382 define <16 x float> @test_mm512_sub_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2383 ;CHECK-LABEL: test_mm512_sub_round_ps_rd_sae
2384 ;CHECK: vsubps {rd-sae}, %zmm1, %zmm0, %zmm0
2385 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 1)
2386 ret <16 x float> %res
2388 define <16 x float> @test_mm512_sub_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2389 ;CHECK-LABEL: test_mm512_sub_round_ps_ru_sae
2390 ;CHECK: vsubps {ru-sae}, %zmm1, %zmm0, %zmm0
2391 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 2)
2392 ret <16 x float> %res
2395 define <16 x float> @test_mm512_sub_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2396 ;CHECK-LABEL: test_mm512_sub_round_ps_rz_sae
2397 ;CHECK: vsubps {rz-sae}, %zmm1, %zmm0, %zmm0
2398 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 3)
2399 ret <16 x float> %res
2402 define <16 x float> @test_mm512_sub_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2403 ;CHECK-LABEL: test_mm512_sub_round_ps_current
2404 ;CHECK: vsubps %zmm1, %zmm0, %zmm0
2405 %res = call <16 x float> @llvm.x86.avx512.mask.sub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 4)
2406 ret <16 x float> %res
2409 define <16 x float> @test_mm512_maskz_div_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2410 ;CHECK-LABEL: test_mm512_maskz_div_round_ps_rn_sae
2411 ;CHECK: vdivps {rn-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
2412 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 0)
2413 ret <16 x float> %res
2415 define <16 x float> @test_mm512_maskz_div_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2416 ;CHECK-LABEL: test_mm512_maskz_div_round_ps_rd_sae
2417 ;CHECK: vdivps {rd-sae}, %zmm1, %zmm0, %zmm0
2418 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 1)
2419 ret <16 x float> %res
2421 define <16 x float> @test_mm512_maskz_div_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2422 ;CHECK-LABEL: test_mm512_maskz_div_round_ps_ru_sae
2423 ;CHECK: vdivps {ru-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
2424 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 2)
2425 ret <16 x float> %res
2428 define <16 x float> @test_mm512_maskz_div_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2429 ;CHECK-LABEL: test_mm512_maskz_div_round_ps_rz_sae
2430 ;CHECK: vdivps {rz-sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
2431 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 3)
2432 ret <16 x float> %res
2436 define <16 x float> @test_mm512_maskz_div_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2437 ;CHECK-LABEL: test_mm512_maskz_div_round_ps_current
2438 ;CHECK: vdivps %zmm1, %zmm0, %zmm0 {%k1} {z}
2439 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 4)
2440 ret <16 x float> %res
2443 define <16 x float> @test_mm512_mask_div_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2444 ;CHECK-LABEL: test_mm512_mask_div_round_ps_rn_sae
2445 ;CHECK: vdivps {rn-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2446 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 0)
2447 ret <16 x float> %res
2449 define <16 x float> @test_mm512_mask_div_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2450 ;CHECK-LABEL: test_mm512_mask_div_round_ps_rd_sae
2451 ;CHECK: vdivps {rd-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2452 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 1)
2453 ret <16 x float> %res
2455 define <16 x float> @test_mm512_mask_div_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2456 ;CHECK-LABEL: test_mm512_mask_div_round_ps_ru_sae
2457 ;CHECK: vdivps {ru-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2458 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 2)
2459 ret <16 x float> %res
2462 define <16 x float> @test_mm512_mask_div_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2463 ;CHECK-LABEL: test_mm512_mask_div_round_ps_rz_sae
2464 ;CHECK: vdivps {rz-sae}, %zmm1, %zmm0, %zmm2 {%k1}
2465 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 3)
2466 ret <16 x float> %res
2470 define <16 x float> @test_mm512_mask_div_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2471 ;CHECK-LABEL: test_mm512_mask_div_round_ps_current
2472 ;CHECK: vdivps %zmm1, %zmm0, %zmm2 {%k1}
2473 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 4)
2474 ret <16 x float> %res
2478 define <16 x float> @test_mm512_div_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2479 ;CHECK-LABEL: test_mm512_div_round_ps_rn_sae
2480 ;CHECK: vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
2481 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 0)
2482 ret <16 x float> %res
2484 define <16 x float> @test_mm512_div_round_ps_rd_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2485 ;CHECK-LABEL: test_mm512_div_round_ps_rd_sae
2486 ;CHECK: vdivps {rd-sae}, %zmm1, %zmm0, %zmm0
2487 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 1)
2488 ret <16 x float> %res
2490 define <16 x float> @test_mm512_div_round_ps_ru_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2491 ;CHECK-LABEL: test_mm512_div_round_ps_ru_sae
2492 ;CHECK: vdivps {ru-sae}, %zmm1, %zmm0, %zmm0
2493 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 2)
2494 ret <16 x float> %res
2497 define <16 x float> @test_mm512_div_round_ps_rz_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2498 ;CHECK-LABEL: test_mm512_div_round_ps_rz_sae
2499 ;CHECK: vdivps {rz-sae}, %zmm1, %zmm0, %zmm0
2500 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 3)
2501 ret <16 x float> %res
2504 define <16 x float> @test_mm512_div_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2505 ;CHECK-LABEL: test_mm512_div_round_ps_current
2506 ;CHECK: vdivps %zmm1, %zmm0, %zmm0
2507 %res = call <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 4)
2508 ret <16 x float> %res
2510 declare <16 x float> @llvm.x86.avx512.mask.div.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
2512 define <16 x float> @test_mm512_maskz_min_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2513 ;CHECK-LABEL: test_mm512_maskz_min_round_ps_sae
2514 ;CHECK: vminps {sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
2515 %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 8)
2516 ret <16 x float> %res
2519 define <16 x float> @test_mm512_maskz_min_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2520 ;CHECK-LABEL: test_mm512_maskz_min_round_ps_current
2521 ;CHECK: vminps %zmm1, %zmm0, %zmm0 {%k1} {z}
2522 %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 4)
2523 ret <16 x float> %res
2526 define <16 x float> @test_mm512_mask_min_round_ps_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2527 ;CHECK-LABEL: test_mm512_mask_min_round_ps_sae
2528 ;CHECK: vminps {sae}, %zmm1, %zmm0, %zmm2 {%k1}
2529 %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 8)
2530 ret <16 x float> %res
2533 define <16 x float> @test_mm512_mask_min_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2534 ;CHECK-LABEL: test_mm512_mask_min_round_ps_current
2535 ;CHECK: vminps %zmm1, %zmm0, %zmm2 {%k1}
2536 %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 4)
2537 ret <16 x float> %res
2540 define <16 x float> @test_mm512_min_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2541 ;CHECK-LABEL: test_mm512_min_round_ps_sae
2542 ;CHECK: vminps {sae}, %zmm1, %zmm0, %zmm0
2543 %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 8)
2544 ret <16 x float> %res
2547 define <16 x float> @test_mm512_min_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2548 ;CHECK-LABEL: test_mm512_min_round_ps_current
2549 ;CHECK: vminps %zmm1, %zmm0, %zmm0
2550 %res = call <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 4)
2551 ret <16 x float> %res
2553 declare <16 x float> @llvm.x86.avx512.mask.min.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
2555 define <16 x float> @test_mm512_maskz_max_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2556 ;CHECK-LABEL: test_mm512_maskz_max_round_ps_sae
2557 ;CHECK: vmaxps {sae}, %zmm1, %zmm0, %zmm0 {%k1} {z}
2558 %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 8)
2559 ret <16 x float> %res
2562 define <16 x float> @test_mm512_maskz_max_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2563 ;CHECK-LABEL: test_mm512_maskz_max_round_ps_current
2564 ;CHECK: vmaxps %zmm1, %zmm0, %zmm0 {%k1} {z}
2565 %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 %mask, i32 4)
2566 ret <16 x float> %res
2569 define <16 x float> @test_mm512_mask_max_round_ps_sae(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2570 ;CHECK-LABEL: test_mm512_mask_max_round_ps_sae
2571 ;CHECK: vmaxps {sae}, %zmm1, %zmm0, %zmm2 {%k1}
2572 %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 8)
2573 ret <16 x float> %res
2576 define <16 x float> @test_mm512_mask_max_round_ps_current(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask) {
2577 ;CHECK-LABEL: test_mm512_mask_max_round_ps_current
2578 ;CHECK: vmaxps %zmm1, %zmm0, %zmm2 {%k1}
2579 %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %src, i16 %mask, i32 4)
2580 ret <16 x float> %res
2583 define <16 x float> @test_mm512_max_round_ps_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2584 ;CHECK-LABEL: test_mm512_max_round_ps_sae
2585 ;CHECK: vmaxps {sae}, %zmm1, %zmm0, %zmm0
2586 %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 8)
2587 ret <16 x float> %res
2590 define <16 x float> @test_mm512_max_round_ps_current(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
2591 ;CHECK-LABEL: test_mm512_max_round_ps_current
2592 ;CHECK: vmaxps %zmm1, %zmm0, %zmm0
2593 %res = call <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float>zeroinitializer, i16 -1, i32 4)
2594 ret <16 x float> %res
2596 declare <16 x float> @llvm.x86.avx512.mask.max.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
2598 declare <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
2600 define <4 x float> @test_mask_add_ss_rn(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
2601 ; CHECK-LABEL: test_mask_add_ss_rn
2602 ; CHECK: vaddss {rn-sae}, %xmm1, %xmm0, %xmm2 {%k1}
2603 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 0)
2604 ret <4 x float> %res
2607 define <4 x float> @test_mask_add_ss_rd(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
2608 ; CHECK-LABEL: test_mask_add_ss_rd
2609 ; CHECK: vaddss {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}
2610 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 1)
2611 ret <4 x float> %res
2614 define <4 x float> @test_mask_add_ss_ru(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
2615 ; CHECK-LABEL: test_mask_add_ss_ru
2616 ; CHECK: vaddss {ru-sae}, %xmm1, %xmm0, %xmm2 {%k1}
2617 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 2)
2618 ret <4 x float> %res
2621 define <4 x float> @test_mask_add_ss_rz(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
2622 ; CHECK-LABEL: test_mask_add_ss_rz
2623 ; CHECK: vaddss {rz-sae}, %xmm1, %xmm0, %xmm2 {%k1}
2624 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 3)
2625 ret <4 x float> %res
2628 define <4 x float> @test_mask_add_ss_current(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
2629 ; CHECK-LABEL: test_mask_add_ss_current
2630 ; CHECK: vaddss %xmm1, %xmm0, %xmm2 {%k1}
2631 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)
2632 ret <4 x float> %res
2635 define <4 x float> @test_maskz_add_ss_rn(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
2636 ; CHECK-LABEL: test_maskz_add_ss_rn
2637 ; CHECK: vaddss {rn-sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
2638 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 0)
2639 ret <4 x float> %res
2642 define <4 x float> @test_add_ss_rn(<4 x float> %a0, <4 x float> %a1) {
2643 ; CHECK-LABEL: test_add_ss_rn
2644 ; CHECK: vaddss {rn-sae}, %xmm1, %xmm0, %xmm0
2645 %res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 0)
2646 ret <4 x float> %res
2649 declare <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone
2651 define <2 x double> @test_mask_add_sd_rn(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
2652 ; CHECK-LABEL: test_mask_add_sd_rn
2653 ; CHECK: vaddsd {rn-sae}, %xmm1, %xmm0, %xmm2 {%k1}
2654 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 0)
2655 ret <2 x double> %res
2658 define <2 x double> @test_mask_add_sd_rd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
2659 ; CHECK-LABEL: test_mask_add_sd_rd
2660 ; CHECK: vaddsd {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}
2661 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 1)
2662 ret <2 x double> %res
2665 define <2 x double> @test_mask_add_sd_ru(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
2666 ; CHECK-LABEL: test_mask_add_sd_ru
2667 ; CHECK: vaddsd {ru-sae}, %xmm1, %xmm0, %xmm2 {%k1}
2668 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 2)
2669 ret <2 x double> %res
2672 define <2 x double> @test_mask_add_sd_rz(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
2673 ; CHECK-LABEL: test_mask_add_sd_rz
2674 ; CHECK: vaddsd {rz-sae}, %xmm1, %xmm0, %xmm2 {%k1}
2675 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 3)
2676 ret <2 x double> %res
2679 define <2 x double> @test_mask_add_sd_current(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
2680 ; CHECK-LABEL: test_mask_add_sd_current
2681 ; CHECK: vaddsd %xmm1, %xmm0, %xmm2 {%k1}
2682 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)
2683 ret <2 x double> %res
2686 define <2 x double> @test_maskz_add_sd_rn(<2 x double> %a0, <2 x double> %a1, i8 %mask) {
2687 ; CHECK-LABEL: test_maskz_add_sd_rn
2688 ; CHECK: vaddsd {rn-sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
2689 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 0)
2690 ret <2 x double> %res
2693 define <2 x double> @test_add_sd_rn(<2 x double> %a0, <2 x double> %a1) {
2694 ; CHECK-LABEL: test_add_sd_rn
2695 ; CHECK: vaddsd {rn-sae}, %xmm1, %xmm0, %xmm0
2696 %res = call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 0)
2697 ret <2 x double> %res
2700 declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
2702 define <4 x float> @test_mask_max_ss_sae(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
2703 ; CHECK-LABEL: test_mask_max_ss_sae
2704 ; CHECK: vmaxss {sae}, %xmm1, %xmm0, %xmm2 {%k1}
2705 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 8)
2706 ret <4 x float> %res
2709 define <4 x float> @test_maskz_max_ss_sae(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
2710 ; CHECK-LABEL: test_maskz_max_ss_sae
2711 ; CHECK: vmaxss {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
2712 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 8)
2713 ret <4 x float> %res
2716 define <4 x float> @test_max_ss_sae(<4 x float> %a0, <4 x float> %a1) {
2717 ; CHECK-LABEL: test_max_ss_sae
2718 ; CHECK: vmaxss {sae}, %xmm1, %xmm0, %xmm0
2719 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 8)
2720 ret <4 x float> %res
2723 define <4 x float> @test_mask_max_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, i8 %mask) {
2724 ; CHECK-LABEL: test_mask_max_ss
2725 ; CHECK: vmaxss %xmm1, %xmm0, %xmm2 {%k1}
2726 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> %a2, i8 %mask, i32 4)
2727 ret <4 x float> %res
2730 define <4 x float> @test_maskz_max_ss(<4 x float> %a0, <4 x float> %a1, i8 %mask) {
2731 ; CHECK-LABEL: test_maskz_max_ss
2732 ; CHECK: vmaxss %xmm1, %xmm0, %xmm0 {%k1} {z}
2733 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %mask, i32 4)
2734 ret <4 x float> %res
2737 define <4 x float> @test_max_ss(<4 x float> %a0, <4 x float> %a1) {
2738 ; CHECK-LABEL: test_max_ss
2739 ; CHECK: vmaxss %xmm1, %xmm0, %xmm0
2740 %res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 -1, i32 4)
2741 ret <4 x float> %res
2743 declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone
2745 define <2 x double> @test_mask_max_sd_sae(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
2746 ; CHECK-LABEL: test_mask_max_sd_sae
2747 ; CHECK: vmaxsd {sae}, %xmm1, %xmm0, %xmm2 {%k1}
2748 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 8)
2749 ret <2 x double> %res
2752 define <2 x double> @test_maskz_max_sd_sae(<2 x double> %a0, <2 x double> %a1, i8 %mask) {
2753 ; CHECK-LABEL: test_maskz_max_sd_sae
2754 ; CHECK: vmaxsd {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z}
2755 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 8)
2756 ret <2 x double> %res
2759 define <2 x double> @test_max_sd_sae(<2 x double> %a0, <2 x double> %a1) {
2760 ; CHECK-LABEL: test_max_sd_sae
2761 ; CHECK: vmaxsd {sae}, %xmm1, %xmm0, %xmm0
2762 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 8)
2763 ret <2 x double> %res
2766 define <2 x double> @test_mask_max_sd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, i8 %mask) {
2767 ; CHECK-LABEL: test_mask_max_sd
2768 ; CHECK: vmaxsd %xmm1, %xmm0, %xmm2 {%k1}
2769 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> %a2, i8 %mask, i32 4)
2770 ret <2 x double> %res
2773 define <2 x double> @test_maskz_max_sd(<2 x double> %a0, <2 x double> %a1, i8 %mask) {
2774 ; CHECK-LABEL: test_maskz_max_sd
2775 ; CHECK: vmaxsd %xmm1, %xmm0, %xmm0 {%k1} {z}
2776 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 %mask, i32 4)
2777 ret <2 x double> %res
2780 define <2 x double> @test_max_sd(<2 x double> %a0, <2 x double> %a1) {
2781 ; CHECK-LABEL: test_max_sd
2782 ; CHECK: vmaxsd %xmm1, %xmm0, %xmm0
2783 %res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 4)
2784 ret <2 x double> %res
2787 define <2 x double> @test_x86_avx512_cvtsi2sd32(<2 x double> %a, i32 %b) {
2788 ; CHECK-LABEL: test_x86_avx512_cvtsi2sd32:
2790 ; CHECK-NEXT: vcvtsi2sdl %edi, {rz-sae}, %xmm0, %xmm0
2792 %res = call <2 x double> @llvm.x86.avx512.cvtsi2sd32(<2 x double> %a, i32 %b, i32 3) ; <<<2 x double>> [#uses=1]
2793 ret <2 x double> %res
2795 declare <2 x double> @llvm.x86.avx512.cvtsi2sd32(<2 x double>, i32, i32) nounwind readnone
2797 define <2 x double> @test_x86_avx512_cvtsi2sd64(<2 x double> %a, i64 %b) {
2798 ; CHECK-LABEL: test_x86_avx512_cvtsi2sd64:
2800 ; CHECK-NEXT: vcvtsi2sdq %rdi, {rz-sae}, %xmm0, %xmm0
2802 %res = call <2 x double> @llvm.x86.avx512.cvtsi2sd64(<2 x double> %a, i64 %b, i32 3) ; <<<2 x double>> [#uses=1]
2803 ret <2 x double> %res
2805 declare <2 x double> @llvm.x86.avx512.cvtsi2sd64(<2 x double>, i64, i32) nounwind readnone
2807 define <4 x float> @test_x86_avx512_cvtsi2ss32(<4 x float> %a, i32 %b) {
2808 ; CHECK-LABEL: test_x86_avx512_cvtsi2ss32:
2810 ; CHECK-NEXT: vcvtsi2ssl %edi, {rz-sae}, %xmm0, %xmm0
2812 %res = call <4 x float> @llvm.x86.avx512.cvtsi2ss32(<4 x float> %a, i32 %b, i32 3) ; <<<4 x float>> [#uses=1]
2813 ret <4 x float> %res
2815 declare <4 x float> @llvm.x86.avx512.cvtsi2ss32(<4 x float>, i32, i32) nounwind readnone
2817 define <4 x float> @test_x86_avx512_cvtsi2ss64(<4 x float> %a, i64 %b) {
2818 ; CHECK-LABEL: test_x86_avx512_cvtsi2ss64:
2820 ; CHECK-NEXT: vcvtsi2ssq %rdi, {rz-sae}, %xmm0, %xmm0
2822 %res = call <4 x float> @llvm.x86.avx512.cvtsi2ss64(<4 x float> %a, i64 %b, i32 3) ; <<<4 x float>> [#uses=1]
2823 ret <4 x float> %res
2825 declare <4 x float> @llvm.x86.avx512.cvtsi2ss64(<4 x float>, i64, i32) nounwind readnone
2827 define <8 x i64> @test_vpmaxq(<8 x i64> %a0, <8 x i64> %a1) {
2828 ; CHECK: vpmaxsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x3d,0xc1]
2829 %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %a0, <8 x i64> %a1,
2830 <8 x i64>zeroinitializer, i8 -1)
2833 declare <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
2835 define <16 x i32> @test_vpminud(<16 x i32> %a0, <16 x i32> %a1) {
2836 ; CHECK: vpminud {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3b,0xc1]
2837 %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %a0, <16 x i32> %a1,
2838 <16 x i32>zeroinitializer, i16 -1)
2841 declare <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
2843 define <16 x i32> @test_vpmaxsd(<16 x i32> %a0, <16 x i32> %a1) {
2844 ; CHECK: vpmaxsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3d,0xc1]
2845 %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %a0, <16 x i32> %a1,
2846 <16 x i32>zeroinitializer, i16 -1)
2849 declare <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
2851 ; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_512
2853 ; CHECK: vpmaxsd %zmm
2855 define <16 x i32>@test_int_x86_avx512_mask_pmaxs_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {
2856 %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)
2857 %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)
2858 %res2 = add <16 x i32> %res, %res1
2859 ret <16 x i32> %res2
2862 ; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_512
2864 ; CHECK: vpmaxsq %zmm
2866 define <8 x i64>@test_int_x86_avx512_mask_pmaxs_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
2867 %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
2868 %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
2869 %res2 = add <8 x i64> %res, %res1
2873 declare <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
2875 ; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_512
2877 ; CHECK: vpmaxud %zmm
2879 define <16 x i32>@test_int_x86_avx512_mask_pmaxu_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {
2880 %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)
2881 %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)
2882 %res2 = add <16 x i32> %res, %res1
2883 ret <16 x i32> %res2
2886 declare <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
2888 ; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_512
2890 ; CHECK: vpmaxuq %zmm
2892 define <8 x i64>@test_int_x86_avx512_mask_pmaxu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
2893 %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
2894 %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
2895 %res2 = add <8 x i64> %res, %res1
2899 declare <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
2901 ; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_512
2903 ; CHECK: vpminsd %zmm
2905 define <16 x i32>@test_int_x86_avx512_mask_pmins_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {
2906 %res = call <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)
2907 %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)
2908 %res2 = add <16 x i32> %res, %res1
2909 ret <16 x i32> %res2
2912 declare <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
2914 ; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_512
2916 ; CHECK: vpminsq %zmm
2918 define <8 x i64>@test_int_x86_avx512_mask_pmins_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
2919 %res = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
2920 %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
2921 %res2 = add <8 x i64> %res, %res1
2925 ; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_512
2927 ; CHECK: vpminud %zmm
2929 define <16 x i32>@test_int_x86_avx512_mask_pminu_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {
2930 %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)
2931 %res1 = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)
2932 %res2 = add <16 x i32> %res, %res1
2933 ret <16 x i32> %res2
2936 declare <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
2938 ; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_512
2940 ; CHECK: vpminuq %zmm
2942 define <8 x i64>@test_int_x86_avx512_mask_pminu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {
2943 %res = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
2944 %res1 = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)
2945 %res2 = add <8 x i64> %res, %res1