1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
3 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
5 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
6 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
7 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
9 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
10 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone
11 declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone
13 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
15 ; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i32:
16 ; SI: s_load_dword [[VAL:s[0-9]+]],
17 ; SI: s_flbit_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]]
18 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
19 ; SI: buffer_store_dword [[VRESULT]],
21 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
22 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
23 define void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
24 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
25 store i32 %ctlz, i32 addrspace(1)* %out, align 4
29 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32:
30 ; SI: buffer_load_dword [[VAL:v[0-9]+]],
31 ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
32 ; SI: buffer_store_dword [[RESULT]],
34 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
35 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
36 define void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
37 %val = load i32, i32 addrspace(1)* %valptr, align 4
38 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone
39 store i32 %ctlz, i32 addrspace(1)* %out, align 4
43 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v2i32:
44 ; SI: buffer_load_dwordx2
47 ; SI: buffer_store_dwordx2
49 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
50 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
51 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
52 define void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind {
53 %val = load <2 x i32>, <2 x i32> addrspace(1)* %valptr, align 8
54 %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 true) nounwind readnone
55 store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8
59 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v4i32:
60 ; SI: buffer_load_dwordx4
65 ; SI: buffer_store_dwordx4
67 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
68 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
69 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
70 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
71 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
72 define void @v_ctlz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind {
73 %val = load <4 x i32>, <4 x i32> addrspace(1)* %valptr, align 16
74 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 true) nounwind readnone
75 store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16
79 ; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64:
80 ; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
81 ; SI-DAG: v_cmp_eq_i32_e64 vcc, 0, s[[HI]]
82 ; SI-DAG: s_flbit_i32_b32 [[FFBH_LO:s[0-9]+]], s[[LO]]
83 ; SI-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32
84 ; SI-DAG: s_flbit_i32_b32 [[FFBH_HI:s[0-9]+]], s[[HI]]
85 ; SI-DAG: v_mov_b32_e32 [[VFFBH_LO:v[0-9]+]], [[FFBH_LO]]
86 ; SI-DAG: v_mov_b32_e32 [[VFFBH_HI:v[0-9]+]], [[FFBH_HI]]
87 ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
88 ; SI-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}}
89 ; SI: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
90 define void @s_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 %val) nounwind {
91 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)
92 store i64 %ctlz, i64 addrspace(1)* %out
96 ; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64_trunc:
97 define void @s_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind {
98 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)
99 %trunc = trunc i64 %ctlz to i32
100 store i32 %trunc, i32 addrspace(1)* %out
104 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64:
105 ; SI: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
106 ; SI-DAG: v_cmp_eq_i32_e64 [[CMPHI:s\[[0-9]+:[0-9]+\]]], 0, v[[HI]]
107 ; SI-DAG: v_ffbh_u32_e32 [[FFBH_LO:v[0-9]+]], v[[LO]]
108 ; SI-DAG: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 32, [[FFBH_LO]]
109 ; SI-DAG: v_ffbh_u32_e32 [[FFBH_HI:v[0-9]+]], v[[HI]]
110 ; SI-DAG: v_cndmask_b32_e64 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]]
111 ; SI-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}}
112 ; SI: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
113 define void @v_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
114 %tid = call i32 @llvm.r600.read.tidig.x()
115 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
116 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
117 %val = load i64, i64 addrspace(1)* %in.gep
118 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)
119 store i64 %ctlz, i64 addrspace(1)* %out.gep
123 ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64_trunc:
124 define void @v_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
125 %tid = call i32 @llvm.r600.read.tidig.x()
126 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
127 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
128 %val = load i64, i64 addrspace(1)* %in.gep
129 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true)
130 %trunc = trunc i64 %ctlz to i32
131 store i32 %trunc, i32 addrspace(1)* %out.gep