1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 define float @test_vrecpss_f32(float %a, float %b) {
4 ; CHECK: test_vrecpss_f32
5 ; CHECK: frecps {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
6 %1 = insertelement <1 x float> undef, float %a, i32 0
7 %2 = insertelement <1 x float> undef, float %b, i32 0
8 %3 = call <1 x float> @llvm.arm.neon.vrecps.v1f32(<1 x float> %1, <1 x float> %2)
9 %4 = extractelement <1 x float> %3, i32 0
13 define double @test_vrecpsd_f64(double %a, double %b) {
14 ; CHECK: test_vrecpsd_f64
15 ; CHECK: frecps {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
16 %1 = insertelement <1 x double> undef, double %a, i32 0
17 %2 = insertelement <1 x double> undef, double %b, i32 0
18 %3 = call <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double> %1, <1 x double> %2)
19 %4 = extractelement <1 x double> %3, i32 0
23 declare <1 x float> @llvm.arm.neon.vrecps.v1f32(<1 x float>, <1 x float>)
24 declare <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double>, <1 x double>)
26 define float @test_vrsqrtss_f32(float %a, float %b) {
27 ; CHECK: test_vrsqrtss_f32
28 ; CHECK: frsqrts {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
29 %1 = insertelement <1 x float> undef, float %a, i32 0
30 %2 = insertelement <1 x float> undef, float %b, i32 0
31 %3 = call <1 x float> @llvm.arm.neon.vrsqrts.v1f32(<1 x float> %1, <1 x float> %2)
32 %4 = extractelement <1 x float> %3, i32 0
36 define double @test_vrsqrtsd_f64(double %a, double %b) {
37 ; CHECK: test_vrsqrtsd_f64
38 ; CHECK: frsqrts {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
39 %1 = insertelement <1 x double> undef, double %a, i32 0
40 %2 = insertelement <1 x double> undef, double %b, i32 0
41 %3 = call <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double> %1, <1 x double> %2)
42 %4 = extractelement <1 x double> %3, i32 0
46 declare <1 x float> @llvm.arm.neon.vrsqrts.v1f32(<1 x float>, <1 x float>)
47 declare <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double>, <1 x double>)
49 define float @test_vrecpes_f32(float %a) {
50 ; CHECK: test_vrecpes_f32
51 ; CHECK: frecpe {{s[0-9]+}}, {{s[0-9]+}}
53 %vrecpe.i = insertelement <1 x float> undef, float %a, i32 0
54 %vrecpe1.i = tail call <1 x float> @llvm.arm.neon.vrecpe.v1f32(<1 x float> %vrecpe.i)
55 %0 = extractelement <1 x float> %vrecpe1.i, i32 0
59 define double @test_vrecped_f64(double %a) {
60 ; CHECK: test_vrecped_f64
61 ; CHECK: frecpe {{d[0-9]+}}, {{d[0-9]+}}
63 %vrecpe.i = insertelement <1 x double> undef, double %a, i32 0
64 %vrecpe1.i = tail call <1 x double> @llvm.arm.neon.vrecpe.v1f64(<1 x double> %vrecpe.i)
65 %0 = extractelement <1 x double> %vrecpe1.i, i32 0
69 declare <1 x float> @llvm.arm.neon.vrecpe.v1f32(<1 x float>)
70 declare <1 x double> @llvm.arm.neon.vrecpe.v1f64(<1 x double>)
72 define float @test_vrecpxs_f32(float %a) {
73 ; CHECK: test_vrecpxs_f32
74 ; CHECK: frecpx {{s[0-9]+}}, {{s[0-9]+}}
76 %vrecpx.i = insertelement <1 x float> undef, float %a, i32 0
77 %vrecpx1.i = tail call <1 x float> @llvm.aarch64.neon.vrecpx.v1f32(<1 x float> %vrecpx.i)
78 %0 = extractelement <1 x float> %vrecpx1.i, i32 0
82 define double @test_vrecpxd_f64(double %a) {
83 ; CHECK: test_vrecpxd_f64
84 ; CHECK: frecpx {{d[0-9]+}}, {{d[0-9]+}}
86 %vrecpx.i = insertelement <1 x double> undef, double %a, i32 0
87 %vrecpx1.i = tail call <1 x double> @llvm.aarch64.neon.vrecpx.v1f64(<1 x double> %vrecpx.i)
88 %0 = extractelement <1 x double> %vrecpx1.i, i32 0
92 declare <1 x float> @llvm.aarch64.neon.vrecpx.v1f32(<1 x float>)
93 declare <1 x double> @llvm.aarch64.neon.vrecpx.v1f64(<1 x double>)
95 define float @test_vrsqrtes_f32(float %a) {
96 ; CHECK: test_vrsqrtes_f32
97 ; CHECK: frsqrte {{s[0-9]+}}, {{s[0-9]+}}
99 %vrsqrte.i = insertelement <1 x float> undef, float %a, i32 0
100 %vrsqrte1.i = tail call <1 x float> @llvm.arm.neon.vrsqrte.v1f32(<1 x float> %vrsqrte.i)
101 %0 = extractelement <1 x float> %vrsqrte1.i, i32 0
105 define double @test_vrsqrted_f64(double %a) {
106 ; CHECK: test_vrsqrted_f64
107 ; CHECK: frsqrte {{d[0-9]+}}, {{d[0-9]+}}
109 %vrsqrte.i = insertelement <1 x double> undef, double %a, i32 0
110 %vrsqrte1.i = tail call <1 x double> @llvm.arm.neon.vrsqrte.v1f64(<1 x double> %vrsqrte.i)
111 %0 = extractelement <1 x double> %vrsqrte1.i, i32 0
115 declare <1 x float> @llvm.arm.neon.vrsqrte.v1f32(<1 x float>)
116 declare <1 x double> @llvm.arm.neon.vrsqrte.v1f64(<1 x double>)