1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// X86 target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "x86tti"
19 #include "X86TargetMachine.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/TargetTransformInfo.h"
25 // Declare the pass initialization routine locally as target-specific passes
26 // don't havve a target-wide initialization entry point, and so we rely on the
27 // pass constructor initialization.
29 void initializeX86TTIPass(PassRegistry &);
34 class X86TTI : public ImmutablePass, public TargetTransformInfo {
35 const X86TargetMachine *TM;
36 const X86Subtarget *ST;
37 const X86TargetLowering *TLI;
39 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
40 /// are set if the result needs to be inserted and/or extracted from vectors.
41 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
44 X86TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
45 llvm_unreachable("This pass cannot be directly constructed");
48 X86TTI(const X86TargetMachine *TM)
49 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
50 TLI(TM->getTargetLowering()) {
51 initializeX86TTIPass(*PassRegistry::getPassRegistry());
54 virtual void initializePass() {
58 virtual void finalizePass() {
62 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
63 TargetTransformInfo::getAnalysisUsage(AU);
66 /// Pass identification.
69 /// Provide necessary pointer adjustments for the two base classes.
70 virtual void *getAdjustedAnalysisPointer(const void *ID) {
71 if (ID == &TargetTransformInfo::ID)
72 return (TargetTransformInfo*)this;
76 /// \name Scalar TTI Implementations
79 virtual PopcntHwSupport getPopcntHwSupport(unsigned TyWidth) const;
83 /// \name Vector TTI Implementations
86 virtual unsigned getNumberOfRegisters(bool Vector) const;
87 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
88 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
89 int Index, Type *SubTp) const;
90 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
92 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
94 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
95 unsigned Index) const;
96 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
98 unsigned AddressSpace) const;
103 } // end anonymous namespace
105 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
106 "X86 Target Transform Info", true, true, false)
110 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
111 return new X86TTI(TM);
115 //===----------------------------------------------------------------------===//
119 //===----------------------------------------------------------------------===//
122 struct X86CostTblEntry {
130 FindInTable(const X86CostTblEntry *Tbl, unsigned len, int ISD, MVT Ty) {
131 for (unsigned int i = 0; i < len; ++i)
132 if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty)
135 // Could not find an entry.
140 struct X86TypeConversionCostTblEntry {
149 FindInConvertTable(const X86TypeConversionCostTblEntry *Tbl, unsigned len,
150 int ISD, MVT Dst, MVT Src) {
151 for (unsigned int i = 0; i < len; ++i)
152 if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)
155 // Could not find an entry.
160 X86TTI::PopcntHwSupport X86TTI::getPopcntHwSupport(unsigned TyWidth) const {
161 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
162 // TODO: Currently the __builtin_popcount() implementation using SSE3
163 // instructions is inefficient. Once the problem is fixed, we should
164 // call ST->hasSSE3() instead of ST->hasSSE4().
165 return ST->hasSSE41() ? Fast : None;
168 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
174 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty) const {
175 // Legalize the type.
176 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
178 int ISD = TLI->InstructionOpcodeToISD(Opcode);
179 assert(ISD && "Invalid opcode");
181 static const X86CostTblEntry AVX1CostTable[] = {
182 // We don't have to scalarize unsupported ops. We can issue two half-sized
183 // operations and we only need to extract the upper YMM half.
184 // Two ops + 1 extract + 1 insert = 4.
185 { ISD::MUL, MVT::v8i32, 4 },
186 { ISD::SUB, MVT::v8i32, 4 },
187 { ISD::ADD, MVT::v8i32, 4 },
188 { ISD::MUL, MVT::v4i64, 4 },
189 { ISD::SUB, MVT::v4i64, 4 },
190 { ISD::ADD, MVT::v4i64, 4 },
193 // Look for AVX1 lowering tricks.
195 int Idx = FindInTable(AVX1CostTable, array_lengthof(AVX1CostTable), ISD,
198 return LT.first * AVX1CostTable[Idx].Cost;
200 // Fallback to the default implementation.
201 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty);
204 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
206 // We only estimate the cost of reverse shuffles.
208 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
210 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
212 if (LT.second.getSizeInBits() > 128)
213 Cost = 3; // Extract + insert + copy.
215 // Multiple by the number of parts.
216 return Cost * LT.first;
219 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
220 int ISD = TLI->InstructionOpcodeToISD(Opcode);
221 assert(ISD && "Invalid opcode");
223 EVT SrcTy = TLI->getValueType(Src);
224 EVT DstTy = TLI->getValueType(Dst);
226 if (!SrcTy.isSimple() || !DstTy.isSimple())
227 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
229 static const X86TypeConversionCostTblEntry AVXConversionTbl[] = {
230 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
231 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
232 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
233 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
234 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
235 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
236 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
237 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
238 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
239 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
240 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
241 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
242 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
243 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
244 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
248 int Idx = FindInConvertTable(AVXConversionTbl,
249 array_lengthof(AVXConversionTbl),
250 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
252 return AVXConversionTbl[Idx].Cost;
255 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
258 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
259 Type *CondTy) const {
260 // Legalize the type.
261 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
265 int ISD = TLI->InstructionOpcodeToISD(Opcode);
266 assert(ISD && "Invalid opcode");
268 static const X86CostTblEntry SSE42CostTbl[] = {
269 { ISD::SETCC, MVT::v2f64, 1 },
270 { ISD::SETCC, MVT::v4f32, 1 },
271 { ISD::SETCC, MVT::v2i64, 1 },
272 { ISD::SETCC, MVT::v4i32, 1 },
273 { ISD::SETCC, MVT::v8i16, 1 },
274 { ISD::SETCC, MVT::v16i8, 1 },
277 static const X86CostTblEntry AVX1CostTbl[] = {
278 { ISD::SETCC, MVT::v4f64, 1 },
279 { ISD::SETCC, MVT::v8f32, 1 },
280 // AVX1 does not support 8-wide integer compare.
281 { ISD::SETCC, MVT::v4i64, 4 },
282 { ISD::SETCC, MVT::v8i32, 4 },
283 { ISD::SETCC, MVT::v16i16, 4 },
284 { ISD::SETCC, MVT::v32i8, 4 },
287 static const X86CostTblEntry AVX2CostTbl[] = {
288 { ISD::SETCC, MVT::v4i64, 1 },
289 { ISD::SETCC, MVT::v8i32, 1 },
290 { ISD::SETCC, MVT::v16i16, 1 },
291 { ISD::SETCC, MVT::v32i8, 1 },
295 int Idx = FindInTable(AVX2CostTbl, array_lengthof(AVX2CostTbl), ISD, MTy);
297 return LT.first * AVX2CostTbl[Idx].Cost;
301 int Idx = FindInTable(AVX1CostTbl, array_lengthof(AVX1CostTbl), ISD, MTy);
303 return LT.first * AVX1CostTbl[Idx].Cost;
306 if (ST->hasSSE42()) {
307 int Idx = FindInTable(SSE42CostTbl, array_lengthof(SSE42CostTbl), ISD, MTy);
309 return LT.first * SSE42CostTbl[Idx].Cost;
312 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
315 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
316 unsigned Index) const {
317 assert(Val->isVectorTy() && "This must be a vector type");
320 // Legalize the type.
321 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
323 // This type is legalized to a scalar type.
324 if (!LT.second.isVector())
327 // The type may be split. Normalize the index to the new type.
328 unsigned Width = LT.second.getVectorNumElements();
329 Index = Index % Width;
331 // Floating point scalars are already located in index #0.
332 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
336 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
339 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
340 unsigned AddressSpace) const {
341 // Legalize the type.
342 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
343 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
346 // Each load/store unit costs 1.
347 unsigned Cost = LT.first * 1;
349 // On Sandybridge 256bit load/stores are double pumped
350 // (but not on Haswell).
351 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())